Sense ampliers
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The document discusses sense amplifiers, which are used in memory circuits to amplify weak signals from memory cells to recognizable logic levels. Modern sense amplifiers use 2-6 transistors, while early designs used up to 13 transistors. The key roles of sense amplifiers are amplification, delay reduction, power reduction, and signal restoration. Differential amplifiers are commonly used in SRAM as they offer a true differential output. Bit lines are precharged before reads and the sense amplifier is enabled once a sufficient signal is built up on the bit lines. Various types of sense amplifiers are discussed, including those based on inverters, charge redistribution, and single to differential conversion to overcome noise in larger memories.
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Terminators are used to reduce unwanted signal reflections on transmission lines. There are two main cases where terminators are needed: 1) for long lines where the cable length exceeds 1/6 of the signal rise time and 2) for short, capacitively loaded lines. There are different types of terminators including end, source, and middle terminators. End terminators locate the terminating resistor at the receiving end to dampen reflections, while source terminators use a series resistor at the driving end. Middle terminators can be used to reduce reflections in complex networks without defined sources or destinations. Proper terminator selection and placement is needed to minimize reflections based on transmission line characteristics and circuit configurations.
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Sense ampliers
- 1. By RENUKA N
- 2. Sense Amplifier reads the low power signals of memory cell, amplifies to recognizable logic levels. Modern sense amplifier circuits consists of 2 to 6 transistors, while early one were having as many as 13 transistors. Major role of sense amplifier is in functionality, performance and reliability of memory circuits
- 3. Amplification: In 1T DRAM, amplification is very much needed for proper functionality Delay Reduction: The amplifier compensates for the restricted fan-out driving capability of the memory cell by accelerating the bit line transition, or by detecting & amplifying small transitions on the bit line Power Reduction: Reducing the signal swing on the bit lines can eliminate the power dissipation Signal Restoration: As read and refresh functions are intrinsically linked, it is necessary to drive the bit lines to full signal range after sensing
- 5. A differential amplifier takes small signal differential inputs, and amplifies them to a large signal single ended output Most advantageous part is CMRR and PSRR Its widely used in SRAM memories, as these are the only memory cells that offer a true differential output The gain of Differential-to-single-ended amplifiers is given by Asense = -gm1(r02 ||r04 )
- 7. Bit lines are precharged to VDD by pulling PC low,EQ-PMOS transistor becomes ON,ensuring initial voltages identical,called as equalization The read operation is started by disabling the precharge & equalization devices,enabling word lines Once a sufficient signal is built up,the sense amplifier is turned on by raising SE. Finally the output is produced at the o/p terminals of the inverter
- 9. CMOS Inverter exhibits a High Gain when positioned in transient region Once sufficient voltage is built up sense amplifier is enabled using SE Depending on input according output is created Cross coupled is usually used in 1T DRAM, as here rail to rail transition is enforced on bit lines, refreshing can be easily done
- 10. Usually EEPROMs,DRAMs are single ended ,we can also use a precharges asymmetrically biased inverter as a sense amplifier and are called as charge redistribution amplifier Two Capacitors Clarge and csmall are isolated by pass transistor M1
- 11. Initial voltages VL & Vs precharged to (Vref –Vth) & VDD by connecting S to supply voltage Once M2 is turned ON, charge capacitance discharges slowly, once voltage drops below ( Vref –Vth),M1 pass transistor turns ON, a charge redistribution is initiated, then nodes L and S Equalise As Csmall is very, within small time a greater output is established at the output node, hence it can be used as an amplifier The resulting output can be fed to an inverter with a switching Threshold > (Vref –Vth) to produce a rail to rail swing Only disadvantage is very small Noise margin
- 12. Larger memories >1Mbit affects by noise disturbances, to overcome that single to differential conversion is used Depending upon the values on BL ,amplifier toggles. Creation of Reference voltage is not easy and needs careful design
- 13. Reference Voltage Generation in 1T DRAM
- 14. When EQ is raised, bit lines BLL & BLR are precharged to VDD/2,enables L & L ,and a particular Ref Voltage is generated Dividing the bit lines to two halves effectively reduces the bit line capacitance, this doubles Transfer Ratio and improves SNR
- 16. T