In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology ...VLSICS Design
This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic Design Automation tools.
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
DESIGN OF DIFFERENT DIGITAL CIRCUITS USING SINGLE ELECTRON DEVICESmsejjournal
Single Electron transistor (SET) is foreseen as an excellently growing technology. The aim of this paper is
to present in short the fundamentals of SET as well as to realize its application in the design of single
electron device based novel digital logic circuits with the help of a Monte Carlo based simulator. A Single
Electron Transistors (SET) is characterized by two most substantial determinants. One is very low power
dissipation while the other is its small stature that makes it a favorable suitor for the future generation of
very high level integration. With the utilization of SET, technology is moving past CMOS age resulting in
power efficient, high integrity, handy and high speed devices. Conducting a check on the transport of single
electrons is one of the most stirring aspects of SET technologies. Apparently, Monte Carlo technique is in
vogue in terms of simulating SED based circuits. Hence, a MC based tool called SIMON 2.0 is exercised
upon for the design and simulation of these digital logic circuits. Further, an efficient functioning of the
logic circuits such as multiplexers, decoders, adders and converters are illustrated and established by
means of circuit simulation using SIMON 2.0 simulator.
Hybrid memristor-CMOS implementation of logic gates design using LTSpice IJECEIAES
In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TEC...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology ...VLSICS Design
This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic Design Automation tools.
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
DESIGN OF DIFFERENT DIGITAL CIRCUITS USING SINGLE ELECTRON DEVICESmsejjournal
Single Electron transistor (SET) is foreseen as an excellently growing technology. The aim of this paper is
to present in short the fundamentals of SET as well as to realize its application in the design of single
electron device based novel digital logic circuits with the help of a Monte Carlo based simulator. A Single
Electron Transistors (SET) is characterized by two most substantial determinants. One is very low power
dissipation while the other is its small stature that makes it a favorable suitor for the future generation of
very high level integration. With the utilization of SET, technology is moving past CMOS age resulting in
power efficient, high integrity, handy and high speed devices. Conducting a check on the transport of single
electrons is one of the most stirring aspects of SET technologies. Apparently, Monte Carlo technique is in
vogue in terms of simulating SED based circuits. Hence, a MC based tool called SIMON 2.0 is exercised
upon for the design and simulation of these digital logic circuits. Further, an efficient functioning of the
logic circuits such as multiplexers, decoders, adders and converters are illustrated and established by
means of circuit simulation using SIMON 2.0 simulator.
Hybrid memristor-CMOS implementation of logic gates design using LTSpice IJECEIAES
In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TEC...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nanoscale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we proposed a novel 7-input minority gate in CNTFET technology that has only 9 CNTFETs. Minority function is utilized in the voting systems for decision making and also it is used in data mining. This proposed 7-input minority gate is utilized less fewer transistors than the conventional CMOS method which utilizes many transistors for implementing sum of products. By means of this proposed 7-input minority gate, a 4-input NAND gate can be implemented, which gets better the conventional design in terms of delay and energy efficiency and has much more deriving power at its output.
Performance analysis of cntfet and mosfet focusing channel length, carrier mo...IJAMSE Journal
Enhancement of switching in nanoelectronics, Carbon Nano Tube (CNT) could be utilized in nanoscaled Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In this review, we present an in depth discussion of performances Carbon Nanotube Field Effect Transistor (CNTFET) and its significance in nanoelectronic circuitry in comparison with Metal Oxide Semiconductor Field Effect Transistor(MOSFET). At first, we have discussed the structural unit of Carbon Nanotube and characteristic electrical behaviors beteween CNTFET and MOSFET. Short channel effect and effects of scattering and electric field on mobility of CNTFET and MOSFET have also been discussed. Besides, the nature of ballistic transport
and profound impact of gate capacitance along with dielectric constant on transconductance have also
have been overviewed. Electron ballistic transport would be the key in short channel regime for high speed
switching devices. Finally, a comparative study on the characteristics of contact resistance over switching
capacity between CNTFET and MOSFET has been addressed.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Carbon Nanotube Based Circuit Designing: A ReviewIJERDJOURNAL
ABSTRACT:- A new material and its associated device which have potential to replace Si and CMOS and can extend the scalability of devices below 22 nm is the carbon nanotube (CNT) and its associated transistor, the carbon nanotube field effect transistor (CNTFET). CNT possesses unique properties that make it a promising future material. Similarly, CNTFET is a promising basic building block to complement the existing silicon based MOSFET and can result in the extension of the validity of Moore's law further. This paper presents the state of the art literature related to carbon nanotubes, carbon nanotube field effect transistors and CNTFET based circuit designing. A review of CNTFET based analog and digital circuits has been presented. It has been observed that the use of CNTFET can improve the performance of both analog and digital circuits. The work will be of utmost use to the people working in the field of CNT based analog and digital circuit designing.
Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack TechniqueIJERA Editor
Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes). In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power of a system we used to reduce power consumed by flip-flops. In this paper we design an existing flip-flop “Low power clocked pass transistor flip-flop (LCPTFF)” on CNTFET using Stanford CNTFET model for reference. We propose a design of CNTFET based Forced Stack Low Power Clocked Pass Transistor Flip-Flop (CN-FS-LCPTFF) and observe 12% to 25% power reduction in various conditions like temperature change, CNTFET diameter change, and different voltage supply.
ENERGY EFFICIENT FULL ADDER CELL DESIGN WITH USING CARBON NANOTUBE FIELD EFFE...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.
Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register TannerIJMTST Journal
This paper introduced a design and implementation of shift register using pulsed latches and flip-flops. As
flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock
switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total
circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are
replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With
Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder
cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of
their unique characteristics will save energy consumption and decrease the chip area. In this paper we
presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).
Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer
technology in Different values of temperature and VDD.
Event Management System Vb Net Project Report.pdfKamal Acharya
In present era, the scopes of information technology growing with a very fast .We do not see any are untouched from this industry. The scope of information technology has become wider includes: Business and industry. Household Business, Communication, Education, Entertainment, Science, Medicine, Engineering, Distance Learning, Weather Forecasting. Carrier Searching and so on.
My project named “Event Management System” is software that store and maintained all events coordinated in college. It also helpful to print related reports. My project will help to record the events coordinated by faculties with their Name, Event subject, date & details in an efficient & effective ways.
In my system we have to make a system by which a user can record all events coordinated by a particular faculty. In our proposed system some more featured are added which differs it from the existing system such as security.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
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TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSEDuvanRamosGarzon1
AIRCRAFT GENERAL
The Single Aisle is the most advanced family aircraft in service today, with fly-by-wire flight controls.
The A318, A319, A320 and A321 are twin-engine subsonic medium range aircraft.
The family offers a choice of engines
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Final project report on grocery store management system..pdf
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELL
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
DOI : 10.5121/vlsic.2012.3302 11
CNFET BASED BASIC GATES AND A NOVEL FULL-
ADDER CELL
Fazel Sharifi1
, Amir Momeni1
and keivan Navi1
1
Department of Electrical and Computer Engineering, Shahid Beheshti University,
Tehran, Iran
F_sharifi@sbu.ac.ir
navi@sbu.ac.ir
ABSTRACT
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell
are presented. These designs are based on carbon nanotube technology. In order to compare the proposed
designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the
proposed designs have better performance in comparison with previous designs in terms of speed, power
consumption and power-delay product (PDP).
KEYWORDS
CNFET, MOSFET, Full-Adder cell, Basic gates.
1. INTRODUCTION
Serious Problems and limitations of CMOS technology scaling, have lead the designers to
investigate the replacement candidates for future designs. Several materials are introduced and
explored in ITRS reports as replacements of silicon channel and source/drain regions such as Ge,
III-V compound semiconductors, nanowires, graphene nanoribbons and carbon nanotubes [1].
Carbon nanotube is one of the most promising technologies to replace the traditional CMOS
technology [2-7]. This nano scale tube of graphine is used as channel of field effect transistors
called CNFETs.
Since CNFETs show better performance in comparison with MOSFETs, most of the designers
have designed their circuits based on this technology. One of the most important parts of each
circuit is basic gates such as OR and AND gates. Also Full Adder Cell is an important part in
microprocessors and digital signal processors. These circuits performance influences the whole
arithmetic units. Therefore if we can design these circuits with higher speed and lower power
consumption then we can increase the system performance.
In this paper we proposed new designs for basic gates and a Full Adder Cell based on CNFET
technology. The rest of paper is organized as following. Section 2 presents a review of different
types of CNFETs. Proposed circuits are analyzed in section 3. In section 4 the simulation results
of these new circuits and comparisons with previous ones are presented. And finally, section 5
concludes the paper.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
12
2. CNFETS
Carbon nanotube (CNT) has been considered as one of the most important building blocks in
nano devices. CNT is a sheet of graphite rolled into a tube with a diameter of a few nano meters.
Since the discovery of CNT in 1991 by S. Iijima[8], significant applications of it have been
demonstrated in different fields because of its specific characteristics. These excellent properties
of CNT make them the most promising candidate for creating transistors on a scale smaller than
can be achieved with silicon[9][10].
The way the graphite sheet is rolled is represented by a pair of indices (n,m) called a chiral vector.
CNT with n-m=3 are metals, otherwise they are semiconductors[11]. One of the best applicable
properties of CNT is ballistic transportation of electrons along the tube. therfore Semiconducting
CNT can be used as channel for transistors[12].
CNFETs operate like traditional silicon transistors. Different types of CNFETs have been
presented. One of them is Schottky Barrier CNTEF (SB-CNFET). These transistors are
constructed with a semiconducting nanotube and two metallic contacts acting as source and drain;
hence they have Schottky Barrier at the metal nanotube junction. In this type of CNFETs By
changing the barrier height at the metal- semiconductor interface, gate modulates the injection of
carriers in the nanotube[13]. Due to exhibit strong ambipolar characteristics, SB-CNFETs are
suitable for using in CMOS logic families. Another type of CNFETs is MOSFET-like CNFET
(MOS-CNFET) which exhibit unipolar behavior unlike SB-CNFET. In this MOSFET like device,
the ungated portion (source and drain regions) is heavily doped and the CNTFET operates on the
principle of barrier-height modulation by application of the gate potential. The conductivity of
MOS-CNFETs is modulated by the gate-source bias. Both SB-CNFETs and MOS-CNFETs are
used for high speed design because of their high ON current, however the other type of CNFET,
band-to-band tunneling CNFET (T-CNFET) is utilized for ultra-low-power design on account of
its low ON current and supper cutoff attributes [14].
CNFETs has a useful property that It will ease circuit designing and increase circuit’s
performance on the other hand, which is that the threshold voltage is proportional to the inverse
of the diameter of the nanotube[14], as:
்ܸு =
.ସଶ
ಿ()
ݒ (1)
ܦே் =
ටேభ
మାேమ
మାభమ
(2)
This feature of CNFETs indicates that by changing the CNFETs diameters one can easily acquire
different transistors with different turn on voltages.
3. PROPOSED DESIGNS
3.1. Basic Gates
Basic functions such as AND, OR and Buffer in CMOS technology are implemented by
generating related inverted functions (e.g., NAND, NOR and NOT) followed by an inverter.
Voltage threshold losing which occurred in passing high and low voltages in nMOSFET and
pMOSFET, respectively results in such implementation.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
13
Figure 1 : AND(b) and OR(a) circuits in MOSFET
CNFET technology provides more efficient way to implement these functions in terms of Delay,
Power consumption and Area. Such as explained before (see Eqn. 1), voltage threshold is
proportional to the 1/ܦே் and it could be justified by manupulating ܰଵ and ܰଶ, which (ܰଵ,ܰଶ) is
chiral vector. So increasing the diagonal of nanotube (i.e., ܦே்) results in decreasing the voltage
threshold toward zero. Consequently, pCNFET and nCNFET could be utilized in pull-down and
pull-up network, respectively. This mechanism obviates voltage threshold losing in addition to
removing inverter from critical path and less delay, area and PDP.
AND/OR circuits in CMOS technology include six transistors, whereas the number of transistors
in our proposed CNFET based circuits reduce to four (Fig. 2). As it can be seen in Fig. 2,
pCNFETs are used in pull-down network and nCNFETs are used in pull-up network. The
threshold voltages of these transistors are almost zero. Hence no voltage dropping occurs in these
circuits.
Figure 2 : Proposed Basic Gates(OR(a), AND(b)) Based on CNFET
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
14
3.2. Full-Adder Cell
In this section a new FA-cell (i.e., full adder cell) aka modified TGA are presented. The TGA Full
Adder Cell is based on XOR/XNOR and transmission gates. Eqn. 3 and 4 describe how sum and
cout signals are generated in TGA, respectively.
݉ݑݏ = (ܥ)ܤ⨂ܣ ∨ (ܥ)ܤ⨁ܣ̅ (3)
ܿݐݑ = (ܣ)ܤ⨂ܣ ∨ (ܥ)ܤ⨁ܣ (4)
Transmission gates are used in TGA to avoid the threshold voltage losing in output in cost of
using more transistors (i.e., six transistors). Such as mentioned before, CNFETs adjust voltage
threshold toward zero by increasing the diagonal of CNT. Consequently, transmission gates can
be replaced by pass transistors.
Figure 3 : First Step of Modified TGA
Such as seen in Fig. 3, the number of transistors in the modified TGA is 14 in comparison with
the standard TGA that includes 20 transistors (i.e., six transistors reduction in modified TGA). In
the next step by Substituting two pCNFETs by two nCNFETs obviates required inverter from the
circuit for transforming XOR to XNOR. Details depict in Fig. 4.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
15
Figure 4 : Final Modified TGA
Consequently, final modified TGA includes 12 transistors. Therefore, the area consumption of
proposed FA-cell (i.e., modified TGA full adder cell) is less than standard TGA full adder cell.
4. SIMULATION RESULTS
The HSPICE circuit simulator has been used to simulate both CMOS and CNFET based circuits.
The MOSFET circuits are simulated using a 32n technology. A compact model of CNFETs
presented in [14], [15] and [16] has been used for CNFET based circuits’ simulation. In this
model a MOS-CNFET device is implemented in three levels. In first level (CNFET_L1) the
intrinsic behavior of MOS-CNFET has been modeled. In level 2 (CNFET_L2) the device non-
idealities have been included and in the top level of this hierarchical modeling (CNFET_L3),
multiple CNTs for each MOS_CNFET device are allowable.
The current sources and the trans-capacitance network are two main parts of the CNFET_L1.
Semiconducting sub-bands current (ܫ௦), metallic sub-bands current (ܫ௧) and leakage
current (ܫ௧௧) are three current sources considered for CNFET model in [14] and [15]. These
current sources are given by the following equations:
ܫ௦(ܸ,ௌ, ܸ,ீௌ) ≈
ସమ
∑ ܶ. ܸ,ௌ +
்
݈݊ ൬
ଵା൫ಶ,బష∆ಅా൯ ಼⁄
ଵା
ቀಶ,బష∆ಅాశౙ,ీቁ ಼⁄
൰൨ெ
ୀଵ
(5)
ܫ௧ = (1 − ݉0)
ସమ
ܶ௧ܸ,ௌ µιλ (6)
ܫ௧௧ =
ସమ
.ܶܭ ∑ ܶ௧௧݈݊ ൬
ଵା൫ಶ,బష∆ಅా൯ ಼⁄
ଵା
ቀಶ,బష∆ಅాశౙ,ీቁ ಼⁄
൰ .
୫ୟ୶ (,ವೄିଶா,బ,)
,ವೄିଶா,బ
൨ெ
ୀଵ
(7)
In these equations ܭ is the Boltzmann constant and ܶ is the temperature in Kelvin. Vୡ୦,ୈୗ and
ܸ,ீௌ symbolize the Fermi potential differences near source side within the channel. ∆Φ is the
channel surface potential change with gate/drain bias. ܧ, denotes the carrier energy at the
(݉, ݈)sub-state above the intrinsic levelܧ, and ܧ, is the half band gap of the ݉௧
sub-band. ܶ,
ܶ௧ and ܶ௧௧ are the transmission probability in each case.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
16
Elastic scattering in the channel region, the quantum / series resistance and the parasitic
capacitance of the doped source/drain region and the Schottky barrier resistance at the interface
between the doped CNT and the source/drain metal contacts are the device non-idealities which
CNFET_L2 models[14], [16]. In this paper CNFET_L3, the top level of this device model, is
used for simulating the CNFET based circuits.
The comparison of DELAY, POWER and POWER-DELAY PRODUCT (PDP) of circuits is
discussed below. The time from fifty percent of the input voltage swing to fifty percent of the
output voltage swing is measured as delay.
4.1. Basic Gates Simulation Results
In this section, we report our analysis and compare proposed circuits with MOSFET and CNFET
AND and OR gates. We remark that the design of CNFET gates (i.e., AND and OR) are similar
to the MOSFET gates and obtained by replacing MOSFETs by CNFETs. The design of MOSFET
based gates are described in details in section III.
The circuits are simulated at room temperature and the supply voltage is 0.9V for all of the
circuits. For all circuits a 2.1 femto Farad load capacitor has been used. Table.1 shows the delay,
power and PDP of classical MOSFET and CNFET based and two novel CNFET based Basic
Function circuits.
Table 1. Basic gates simulation results
Function Delay (e-11) Power (e-8) PDP (e-19)
MOSFET-OR 5.141 20.26 104.16
CNFET-OR 1.736 7.78 13.51
Proposed-OR 1.757 3.30 5.804
MOSFET-AND 4.637 18.631 86.398
CNFET-AND 2.402 7.803 18.74
Proposed-AND 1.872 4.77 8.93
As it can be seen in the table.1 proposed OR is 322 and 1.11 times faster than OR MOSFET and
OR CNFET respectively. And it consumes less power than two other designs, which it
consumes146% and 42.4% power less than MOSFET and CNFET kinds, respectively. Therefore
its PDP is better than two others.
The obtained speed up for AND circuit is 289% and 155% in comparison with AND MOSFET
and CNFET, respectively. According to the power consumption factor, proposed AND circuit
consumes 22.7% and 87% power less than MOSFET and CNFET AND, respectively.
Consequently, the proposed AND circuit PDP is again better than the others.
In order to compare more precisely these designs are also simulated in 0.8V, 0.65V and 0.5V
supply voltages. Results show that the proposed basic gates have better performance in all
situations.
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
Figure 5 : PDP of AND gate in different
Figure 6 : PDP of OR gate in
4.2. Full-Adder Cell Simulation Results
We compare our proposed Full Adder Cell with 5 traditional Full Adder
TGA[18], CPL[19], CNTFA1[20
load capacitor is 4.9 femto Farad
MOSFET based and CNFET based circuits and the novel CNFET b
shown in this table, the smallest delay belongs to the proposed design. It is 17.5 times faster than
TGA which has the best delay among other full adders. Although proposed Full Adder design is
best in term of speed and its average power dissipation is less than others. It consumes 33.7% less
power than the CNTFA2. Its power dissipation is 22.5% and 20.5% less than CNTFA1 and TGA.
As it considered from the table.2 the proposed design has the best PDP in comparison with the
other full adders. Simulation results in different supply voltages are shown figure
this figure the proposed Full-Adder cell has the best performance in different situations.
0.8 V
6.23E-18
4.85E
1.12E-18
6.19E-19
0.8 V
7.14E-18
4.78E
9.12E-19
6.31E-19
International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
PDP of AND gate in different supply voltages
PDP of OR gate in different supply voltages
Adder Cell Simulation Results
We compare our proposed Full Adder Cell with 5 traditional Full Adder Cells(C
20] and CNTFA2[21]). For all circuits supply voltage is
femto Farad. Table.2 shows the delay, power and PDP of traditional
MOSFET based and CNFET based circuits and the novel CNFET based Full Adder circuit. As it
shown in this table, the smallest delay belongs to the proposed design. It is 17.5 times faster than
TGA which has the best delay among other full adders. Although proposed Full Adder design is
verage power dissipation is less than others. It consumes 33.7% less
power than the CNTFA2. Its power dissipation is 22.5% and 20.5% less than CNTFA1 and TGA.
As it considered from the table.2 the proposed design has the best PDP in comparison with the
Simulation results in different supply voltages are shown figure 7. as it shown in
Adder cell has the best performance in different situations.
0.65 V 0.5 V
4.85E-18
5.48E-18
1.45E-18 1.34E-18
3.98E-19 5.32E-19
MOSFET-AND
CNFET-AND
PROPOSED-AND
0.65 V 0.5 V
4.78E-18 4.94E-18
9.53E-19 1.01E-18
6.48E-19
2.88E-19
MOSFET-OR
CNFET-OR
PROPOSED-
International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
17
Cells(C-CMOS[17],
]). For all circuits supply voltage is 0.8V and
. Table.2 shows the delay, power and PDP of traditional
ased Full Adder circuit. As it
shown in this table, the smallest delay belongs to the proposed design. It is 17.5 times faster than
TGA which has the best delay among other full adders. Although proposed Full Adder design is
verage power dissipation is less than others. It consumes 33.7% less
power than the CNTFA2. Its power dissipation is 22.5% and 20.5% less than CNTFA1 and TGA.
As it considered from the table.2 the proposed design has the best PDP in comparison with the
. as it shown in
Adder cell has the best performance in different situations.
AND
AND
OR
-OR
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
Table 1.
Design Delay
C-CMOS 123.05
TGA 87.92
CPL 146.34
CNTFA1 109.37
CNTFA2 114.25
Proposed FA 5.00
Figure 7 : PDP of
5. CONCLUSIONS
Using emerging technologies such as CNFET technology have lead to design circuits with better
performance in comparison with traditional MOSFET based circuits in on hand, and have eased
the designing process on the other hand. The proposed
and simpler than the old designs. Hence they have better performance.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
Table 1. Full-Adder Cells simulation results
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
18
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