This document analyzes and compares different 1-bit digital summing circuit topologies in terms of their robustness against process, voltage, and temperature variations at the 22nm technology node. It finds that the transmission gate-based topology is the most robust, with the tightest spread in propagation delay, power dissipation, and energy-delay product. It then proposes a transmission gate-based digital summing circuit implemented using carbon nanotube field-effect transistors, which offers even greater robustness against PVT variations compared to an implementation using traditional MOSFETs.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Implementation of a High Speed and Power Efficient Reliable Multiplier Using ...iosrjce
The document describes the implementation of a high-speed and power-efficient reliable multiplier using an adaptive hold technique (AHT). It aims to address issues like negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) that degrade transistor performance over time. The proposed design uses a column-bypassing or row-bypassing multiplier integrated with an AHT circuit and Razor flip-flops. Simulation results show the AHT multipliers offer significantly reduced delay of 47.004ns and 79mW lower power compared to traditional multipliers for 32-bit versions. While area is increased, the design provides reliable operation even with aging effects and minimizes timing violations and performance degradation.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Prediction of Pcb Radiated Emissions (Emc Symposium Zurich 1998)Piero Belforte
The paper shows the experimental validation of predictive results of radiated emissions of a multilayer pcb. The radiated field is calculated from simulated results of pcb signals obtained from DWN analysis of interconnects.
This document discusses techniques to reduce leakage current and power consumption in static random-access memory (SRAM) cells implemented using independent gate fin field-effect transistors (FinFETs). It first describes the independent gate FinFET SRAM cell design and its advantages over other designs. It then examines two circuit-level leakage reduction techniques: 1) using multi-threshold voltages by connecting high-threshold transistors to reduce leakage when in standby mode, and 2) adding a gated power supply transistor to reduce leakage through stacking effects. Simulation results show that both techniques can reduce leakage current and power in the independent gate FinFET SRAM cell, with multi-threshold voltages providing better leakage control.
This document summarizes the performance enhancement and characterization of a junctionless vertical slit field effect transistor (JLVeSFET). Key findings from simulations include:
1) The JLVeSFET shows an optimized subthreshold slope of 65mV/decade and OFF current of ~10-18A/μm for a 50nm radius device with a high-k dielectric.
2) Using a high-k dielectric (Si3N4) instead of SiO2 increases the Ion/Ioff ratio to ~1011 and reduces the subthreshold slope to 63mV/decade.
3) Increasing the gate doping concentration reduces the subthreshold slope slightly while increasing the Ion/
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Implementation of a High Speed and Power Efficient Reliable Multiplier Using ...iosrjce
The document describes the implementation of a high-speed and power-efficient reliable multiplier using an adaptive hold technique (AHT). It aims to address issues like negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) that degrade transistor performance over time. The proposed design uses a column-bypassing or row-bypassing multiplier integrated with an AHT circuit and Razor flip-flops. Simulation results show the AHT multipliers offer significantly reduced delay of 47.004ns and 79mW lower power compared to traditional multipliers for 32-bit versions. While area is increased, the design provides reliable operation even with aging effects and minimizes timing violations and performance degradation.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Prediction of Pcb Radiated Emissions (Emc Symposium Zurich 1998)Piero Belforte
The paper shows the experimental validation of predictive results of radiated emissions of a multilayer pcb. The radiated field is calculated from simulated results of pcb signals obtained from DWN analysis of interconnects.
This document discusses techniques to reduce leakage current and power consumption in static random-access memory (SRAM) cells implemented using independent gate fin field-effect transistors (FinFETs). It first describes the independent gate FinFET SRAM cell design and its advantages over other designs. It then examines two circuit-level leakage reduction techniques: 1) using multi-threshold voltages by connecting high-threshold transistors to reduce leakage when in standby mode, and 2) adding a gated power supply transistor to reduce leakage through stacking effects. Simulation results show that both techniques can reduce leakage current and power in the independent gate FinFET SRAM cell, with multi-threshold voltages providing better leakage control.
This document summarizes the performance enhancement and characterization of a junctionless vertical slit field effect transistor (JLVeSFET). Key findings from simulations include:
1) The JLVeSFET shows an optimized subthreshold slope of 65mV/decade and OFF current of ~10-18A/μm for a 50nm radius device with a high-k dielectric.
2) Using a high-k dielectric (Si3N4) instead of SiO2 increases the Ion/Ioff ratio to ~1011 and reduces the subthreshold slope to 63mV/decade.
3) Increasing the gate doping concentration reduces the subthreshold slope slightly while increasing the Ion/
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
This document summarizes a study comparing the performance of CNTFET and CMOS comparator designs. CNTFET comparators were simulated using CADENCE showing faster propagation delays, lower power consumption, and improved transient response compared to CMOS comparators. Specifically, the CNTFET comparator had a rise time of 142.1ns versus 1.03ns for CMOS, and fall time of 164.18ns versus 821.476ns for CMOS. Average power was also lower at 118mW for CNTFET versus 910mW for CMOS. Due to these advantages, CNTFETs may replace silicon transistors as the performance of silicon MOSFETs reaches scaling limitations.
1) The document analyzes the effect of intercarrier interference (ICI) on single carrier orthogonal frequency division multiplexing (SC-OFDM) systems.
2) It proposes a novel magnitude-keyed modulation scheme that provides SC-OFDM immunity to ICI. This outperforms other modulation schemes like OFDM, SC-OFDM, and MC-CDMA that use phase shift keying or quadrature amplitude modulation in environments with severe ICI.
3) The analysis shows that the effect of ICI on SC-OFDM signals is simply a phase offset on each data symbol, whereas ICI introduces interference between subcarriers for OFDM. Therefore, SC-OFDM has significantly better performance
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
SIR Analysis of Overloaded CDMA System Using Orthogonal Gold CodesIDES Editor
This document summarizes a research paper that proposes a technique for overloaded CDMA systems using orthogonal gold codes.
1) The technique assigns one set of orthogonal gold codes to the first N users and another set to additional users, but overlays them with different PN sequences. Detection is done iteratively in two steps to detect signals from each user set.
2) A multistage conventional and weighted linear parallel interference cancellation approach is used to cancel interference between the two user sets. Expressions for the signal to interference ratio at the output of the second and third cancellation stages are derived.
3) Simulation results show that the proposed technique can accommodate N users without interference and additional users at the cost of a small
This document describes two techniques for designing optical XNOR and NAND logic gates. The first technique uses a 2D array of coupled optical cavities with Kerr nonlinearity. Discrete cavity solitons are numerically simulated and used to demonstrate optical XNOR and NAND gates by controlling soliton interactions with a Gaussian beam. The second technique uses multi-mode interference waveguides to convert the phase of binary-phase-shift keying input signals to amplitude at the output, implementing optical XNOR and NAND logic. Numerical simulations using the finite element method show contrast ratios of 21.5 dB for the XNOR gate and 22.3 dB for the NAND gate.
1) The document proposes a robust audio watermarking technique based on spread spectrum and empirical mode decomposition (EMD). EMD decomposes audio signals into intrinsic mode functions (IMFs) representing different frequencies.
2) The technique embeds a watermark by performing discrete cosine transform (DCT) on extrema points of the last IMF, arranging them in descending order, and adding watermark bits. Extraction retrieves the watermark from lower IMFs using the secret key.
3) Experiments show the technique is robust against attacks like noise, cropping, filtering and wiener filtering.
This document discusses various techniques for reducing peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems. It describes common PAPR reduction techniques such as partial transmit sequence (PTS), selective mapping (SLM), tone injection, peak cancellation, and peak windowing. It analyzes these techniques based on parameters like distortion, power increase, data rate loss, and bit error rate improvement. The document concludes that while SLM is better for PAPR reduction as it does not cause out-of-band radiation or degrade bit error rate performance, it has the drawback of increased complexity with larger number of subcarriers or phase sequences.
This document describes the design of a high-speed Gray to binary code converter using a novel two transistor XOR gate. It introduces a low power and area efficient Gray to binary converter implemented using a two transistor XOR gate designed with two PMOS transistors. The converter and XOR gate are designed and simulated using Mentor Graphics tools. Simulation results show the converter has very low power dissipation and area requirements compared to other code converter designs.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
This document analyzes the bit error rate (BER) of two-user power-domain non-orthogonal multiple access (NOMA) systems using successive interference cancellation receivers over Rayleigh fading channels. It derives closed-form expressions for the BER in single-input single-output and multiple-input multiple-output NOMA systems. The analysis considers two categories of multiuser superposition transmission and verifies the analytical results through Monte Carlo simulation.
VECTOR VS PIECEWISE-LINEAR FITTING FOR SIGNAL AND POWER INTEGRITY SIMULATIONPiero Belforte
The basic concepts of two fitting methods suitable for signal and power integrity simulation up to multi-gigabit/sec rates are presented. The traditional method is based on Vector Fitting (VF), a well known technique to approximate complex functions of frequency by a rational polynomial expression in terms of poles and residues. The second is a full time-domain approach mainly based on behavioral models supported by the Digital Wave Simulator.
PWLFIT/DWS advantages over VECTFIT/Spice can be summarized with the 3S acronym: SIMPLICITY, STABILITY and SPEED.
SIMPLICITY because the pwl fitting of a time-domain behavior is a very fast, explicit and intuitive process that doens't need the solution of implicit equations as required by Vector fitting. Time-domain S-parameter of actual devices in matched conditions shows simpler behaviors than the corresponding impedance in the frequency domain.
STABILITY because the use of Digital Wave processing is intrinsically very stable. Extracted pwl behaviors processed by fast convolution within DWS are unconditionally stable if the source behavior is stable. This means that NO numerical conditioning is required. As known Vector Fitting often require numerical conditioning to get stable results.
SPEED: time-domain pwl fitting is a very fast process. DWS simulations are also very fast even at very small time steps required by multigigabit system analysis. DWS/SPICE typical speedups are 100X for traditional VF derived RLC-TL circuits and up to 10000X when using pwl Behavioral Models in time domain.
The document discusses reduced order modeling for transient analysis of carbon nanotube interconnects. It proposes using a half-T ladder network model and rational functions to develop a macromodel of a CNT interconnect from its per unit length parameters. The macromodel represents the interconnect admittance matrix using poles and residues, allowing for efficient transient analysis. Numerical results show the macromodel accurately captures the behavior of a CNT interconnect under various transient signals. An experimental setup is also developed to characterize CNT interconnects.
A XOR THRESHOLD LOGIC IMPLEMENTATION THROUGH RESONANT TUNNELING DIODEVLSICS Design
Resonant tunneling diodes (RTDs) have functional versatility and high speed switching capability. The integration of resonant tunneling diodes and MOS transistor makes threshold gates and logics. The design and fabrication of linear threshold gates will be presented based on a monostable bistable transition logic element. Each of its input terminals consist out of a resonant tunnelling diode merged with a transistor device. The circuit models of RTD and MOSFET are simulated in HSPICE. Two input XOR gate is designed and tested.
OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR ...VLSICS Design
Since the current demand for high-resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable TV or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track
and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise
At this present scenario, the demand of the system capacity is very high in wireless network. MIMO
technology is used from the last decade to provide this requirement for wireless network antenna
technology. MIMO channels are mostly used for advanced antenna array technology. But it is most
important to control the error rate with enhanced system capacity in MIMO for present-day progressive
wireless communication. This paper explores the frame error rate with respect to different path gain of
MIMO channel. This work has been done in different fading scenario and produces a comparative analysis
of MIMO on the basis of those fading models in various conditions. Here, it is to be considered that
modulation technique as QPSK to observe these comparative evaluations for different Doppler frequencies.
From the comparative analysis, minimum amount of frame error rate is viewed for Rician distribution at
LOS path Doppler shift of 0 Hz. At last, this work is concluded with a comparative bit error rate study on
the basis of singular parameters at different SNR levels to produce the system performance for uncoded
QPSK modulation.
Adaptive Channel Equalization using Multilayer Perceptron Neural Networks wit...IOSRJVSP
This document presents a neural network approach to channel equalization using a multilayer perceptron with a variable learning rate parameter. Specifically, it proposes modifying the backpropagation algorithm to allow the learning rate to adapt at each iteration in order to achieve faster convergence. The equalizer structure is a decision feedback equalizer modeled as a neural network with an input, hidden and output layer. Simulation results show the proposed variable learning rate approach improves bit error rate and convergence speed compared to a standard backpropagation algorithm.
This document discusses using video compression techniques to compress multichannel neural signals. It proposes using a multiwavelet transform to decorrelate the signals, followed by vector quantization to exploit correlations between electrodes. Motion estimation and compensation are also used to reduce redundancy between successive neural frames by determining motion vectors, similar to how video compression analyzes frame-to-frame motion. The goal is to significantly reduce the large amounts of neural data for easier wireless transmission without degrading quality.
Quartz crystal microbalance based electronic nose system implemented on Field...TELKOMNIKA JOURNAL
1) The document describes a quartz crystal microbalance (QCM) based electronic nose system implemented on a field programmable gate array (FPGA).
2) The electronic nose uses an array of 8 QCM sensors coated with different chemicals and measures their frequency changes when exposed to gases.
3) A neural network with 8 input nodes, 10 hidden nodes, and 2 output nodes is used for pattern recognition on the FPGA. The sigmoid activation function is approximated using a second order equation to simplify hardware implementation.
The document proposes a novel method to characterize nonlinear channels in OFDM systems using spectral notch signals. The method involves transmitting OFDM frames with and without spectral notches and analyzing the difference signal. This allows the estimation of frequency-domain Volterra kernels to be decomposed into independent subtasks involving fewer coefficients, improving accuracy and reducing complexity compared to conventional methods. Simulations validate that the proposed method has lower computational complexity than existing approaches for estimating kernels of cubically nonlinear channels in real baseband OFDM systems.
This document describes the design of optimized reversible Vedic multipliers for high-speed low-power operations. It presents 2x2, 4x4, and 8x8 bit reversible Vedic multipliers based on the Urdhva Tiryakbhyam multiplication algorithm. The multipliers were designed using reversible logic gates like Feynman, Peres, and HNG gates. Simulation results showed the reversible Vedic multipliers have lower time delay, area, and number of logic units compared to normal Vedic multipliers. Potential applications of these high-speed low-power multipliers include fast Fourier transforms, public key cryptography, and embedded systems.
Expert systems : computer hardware problemmazlinapsas
This study introduces a method that will reduce the troubles to in diagnosing the computer hardware failures. An expert intelligent system using the rule-based technique is introduced to diagnose computer hardware failures. User or computer technician no need to check a part of computer hardware, one by one to diagnose computer hardware failure. User or computer technician just need to select category and the symptom or fact into a system, then a system will diagnose a computer hardware failure. The implementation includes types of computer hardware failure, computer condition, rules, and the solution that used in the flow chart technique and rule-based expert systems software. There are nine categories of computer hardware failure: power supply, hard drive, video, monitor, ATA drive, DVD, CD and Blu-ray playback, sound, motherboard, CPU and RAM. The results and analysis presented are computer hardware failure, conditions, rules, and solutions that used in the decision tables technique. Besides that, an analysis of the outputs and explanation about data mining by Weka engine are included to evaluate results. The testing for outputs is from black-box test and user acceptance test to evaluate the capability of study in diagnosing computer hardware failures in all conditions. Besides that, this study also showed that time is less to diagnose computer hardware failure when used expert system, than diagnose computer hardware failure manually
The document discusses error analysis in second language acquisition, noting that mistakes are a natural part of the learning process and can provide useful information about a learner's development, while errors reflect gaps in their underlying language system. It also examines different types of errors, sources of errors, approaches to identifying and categorizing errors, and considerations around providing feedback to and correcting errors of learners.
There are several types of computer errors that can occur from startup to operation. These include issues with video output, booting, loading the operating system, pop-up windows, hardware installation, safe mode not working, keyboard/mouse errors causing restarts, sound issues, and applications causing restarts. Operating system errors fall into categories like system errors caused by hardware or software issues, runtime errors from corrupted files, stop errors from RAM or hard drive issues, device manager errors from drivers or hardware, POST code errors from motherboard beeps for hardware issues, application errors, and browser status codes for website access problems.
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
This document summarizes a study comparing the performance of CNTFET and CMOS comparator designs. CNTFET comparators were simulated using CADENCE showing faster propagation delays, lower power consumption, and improved transient response compared to CMOS comparators. Specifically, the CNTFET comparator had a rise time of 142.1ns versus 1.03ns for CMOS, and fall time of 164.18ns versus 821.476ns for CMOS. Average power was also lower at 118mW for CNTFET versus 910mW for CMOS. Due to these advantages, CNTFETs may replace silicon transistors as the performance of silicon MOSFETs reaches scaling limitations.
1) The document analyzes the effect of intercarrier interference (ICI) on single carrier orthogonal frequency division multiplexing (SC-OFDM) systems.
2) It proposes a novel magnitude-keyed modulation scheme that provides SC-OFDM immunity to ICI. This outperforms other modulation schemes like OFDM, SC-OFDM, and MC-CDMA that use phase shift keying or quadrature amplitude modulation in environments with severe ICI.
3) The analysis shows that the effect of ICI on SC-OFDM signals is simply a phase offset on each data symbol, whereas ICI introduces interference between subcarriers for OFDM. Therefore, SC-OFDM has significantly better performance
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
SIR Analysis of Overloaded CDMA System Using Orthogonal Gold CodesIDES Editor
This document summarizes a research paper that proposes a technique for overloaded CDMA systems using orthogonal gold codes.
1) The technique assigns one set of orthogonal gold codes to the first N users and another set to additional users, but overlays them with different PN sequences. Detection is done iteratively in two steps to detect signals from each user set.
2) A multistage conventional and weighted linear parallel interference cancellation approach is used to cancel interference between the two user sets. Expressions for the signal to interference ratio at the output of the second and third cancellation stages are derived.
3) Simulation results show that the proposed technique can accommodate N users without interference and additional users at the cost of a small
This document describes two techniques for designing optical XNOR and NAND logic gates. The first technique uses a 2D array of coupled optical cavities with Kerr nonlinearity. Discrete cavity solitons are numerically simulated and used to demonstrate optical XNOR and NAND gates by controlling soliton interactions with a Gaussian beam. The second technique uses multi-mode interference waveguides to convert the phase of binary-phase-shift keying input signals to amplitude at the output, implementing optical XNOR and NAND logic. Numerical simulations using the finite element method show contrast ratios of 21.5 dB for the XNOR gate and 22.3 dB for the NAND gate.
1) The document proposes a robust audio watermarking technique based on spread spectrum and empirical mode decomposition (EMD). EMD decomposes audio signals into intrinsic mode functions (IMFs) representing different frequencies.
2) The technique embeds a watermark by performing discrete cosine transform (DCT) on extrema points of the last IMF, arranging them in descending order, and adding watermark bits. Extraction retrieves the watermark from lower IMFs using the secret key.
3) Experiments show the technique is robust against attacks like noise, cropping, filtering and wiener filtering.
This document discusses various techniques for reducing peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems. It describes common PAPR reduction techniques such as partial transmit sequence (PTS), selective mapping (SLM), tone injection, peak cancellation, and peak windowing. It analyzes these techniques based on parameters like distortion, power increase, data rate loss, and bit error rate improvement. The document concludes that while SLM is better for PAPR reduction as it does not cause out-of-band radiation or degrade bit error rate performance, it has the drawback of increased complexity with larger number of subcarriers or phase sequences.
This document describes the design of a high-speed Gray to binary code converter using a novel two transistor XOR gate. It introduces a low power and area efficient Gray to binary converter implemented using a two transistor XOR gate designed with two PMOS transistors. The converter and XOR gate are designed and simulated using Mentor Graphics tools. Simulation results show the converter has very low power dissipation and area requirements compared to other code converter designs.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
This document analyzes the bit error rate (BER) of two-user power-domain non-orthogonal multiple access (NOMA) systems using successive interference cancellation receivers over Rayleigh fading channels. It derives closed-form expressions for the BER in single-input single-output and multiple-input multiple-output NOMA systems. The analysis considers two categories of multiuser superposition transmission and verifies the analytical results through Monte Carlo simulation.
VECTOR VS PIECEWISE-LINEAR FITTING FOR SIGNAL AND POWER INTEGRITY SIMULATIONPiero Belforte
The basic concepts of two fitting methods suitable for signal and power integrity simulation up to multi-gigabit/sec rates are presented. The traditional method is based on Vector Fitting (VF), a well known technique to approximate complex functions of frequency by a rational polynomial expression in terms of poles and residues. The second is a full time-domain approach mainly based on behavioral models supported by the Digital Wave Simulator.
PWLFIT/DWS advantages over VECTFIT/Spice can be summarized with the 3S acronym: SIMPLICITY, STABILITY and SPEED.
SIMPLICITY because the pwl fitting of a time-domain behavior is a very fast, explicit and intuitive process that doens't need the solution of implicit equations as required by Vector fitting. Time-domain S-parameter of actual devices in matched conditions shows simpler behaviors than the corresponding impedance in the frequency domain.
STABILITY because the use of Digital Wave processing is intrinsically very stable. Extracted pwl behaviors processed by fast convolution within DWS are unconditionally stable if the source behavior is stable. This means that NO numerical conditioning is required. As known Vector Fitting often require numerical conditioning to get stable results.
SPEED: time-domain pwl fitting is a very fast process. DWS simulations are also very fast even at very small time steps required by multigigabit system analysis. DWS/SPICE typical speedups are 100X for traditional VF derived RLC-TL circuits and up to 10000X when using pwl Behavioral Models in time domain.
The document discusses reduced order modeling for transient analysis of carbon nanotube interconnects. It proposes using a half-T ladder network model and rational functions to develop a macromodel of a CNT interconnect from its per unit length parameters. The macromodel represents the interconnect admittance matrix using poles and residues, allowing for efficient transient analysis. Numerical results show the macromodel accurately captures the behavior of a CNT interconnect under various transient signals. An experimental setup is also developed to characterize CNT interconnects.
A XOR THRESHOLD LOGIC IMPLEMENTATION THROUGH RESONANT TUNNELING DIODEVLSICS Design
Resonant tunneling diodes (RTDs) have functional versatility and high speed switching capability. The integration of resonant tunneling diodes and MOS transistor makes threshold gates and logics. The design and fabrication of linear threshold gates will be presented based on a monostable bistable transition logic element. Each of its input terminals consist out of a resonant tunnelling diode merged with a transistor device. The circuit models of RTD and MOSFET are simulated in HSPICE. Two input XOR gate is designed and tested.
OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR ...VLSICS Design
Since the current demand for high-resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable TV or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track
and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise
At this present scenario, the demand of the system capacity is very high in wireless network. MIMO
technology is used from the last decade to provide this requirement for wireless network antenna
technology. MIMO channels are mostly used for advanced antenna array technology. But it is most
important to control the error rate with enhanced system capacity in MIMO for present-day progressive
wireless communication. This paper explores the frame error rate with respect to different path gain of
MIMO channel. This work has been done in different fading scenario and produces a comparative analysis
of MIMO on the basis of those fading models in various conditions. Here, it is to be considered that
modulation technique as QPSK to observe these comparative evaluations for different Doppler frequencies.
From the comparative analysis, minimum amount of frame error rate is viewed for Rician distribution at
LOS path Doppler shift of 0 Hz. At last, this work is concluded with a comparative bit error rate study on
the basis of singular parameters at different SNR levels to produce the system performance for uncoded
QPSK modulation.
Adaptive Channel Equalization using Multilayer Perceptron Neural Networks wit...IOSRJVSP
This document presents a neural network approach to channel equalization using a multilayer perceptron with a variable learning rate parameter. Specifically, it proposes modifying the backpropagation algorithm to allow the learning rate to adapt at each iteration in order to achieve faster convergence. The equalizer structure is a decision feedback equalizer modeled as a neural network with an input, hidden and output layer. Simulation results show the proposed variable learning rate approach improves bit error rate and convergence speed compared to a standard backpropagation algorithm.
This document discusses using video compression techniques to compress multichannel neural signals. It proposes using a multiwavelet transform to decorrelate the signals, followed by vector quantization to exploit correlations between electrodes. Motion estimation and compensation are also used to reduce redundancy between successive neural frames by determining motion vectors, similar to how video compression analyzes frame-to-frame motion. The goal is to significantly reduce the large amounts of neural data for easier wireless transmission without degrading quality.
Quartz crystal microbalance based electronic nose system implemented on Field...TELKOMNIKA JOURNAL
1) The document describes a quartz crystal microbalance (QCM) based electronic nose system implemented on a field programmable gate array (FPGA).
2) The electronic nose uses an array of 8 QCM sensors coated with different chemicals and measures their frequency changes when exposed to gases.
3) A neural network with 8 input nodes, 10 hidden nodes, and 2 output nodes is used for pattern recognition on the FPGA. The sigmoid activation function is approximated using a second order equation to simplify hardware implementation.
The document proposes a novel method to characterize nonlinear channels in OFDM systems using spectral notch signals. The method involves transmitting OFDM frames with and without spectral notches and analyzing the difference signal. This allows the estimation of frequency-domain Volterra kernels to be decomposed into independent subtasks involving fewer coefficients, improving accuracy and reducing complexity compared to conventional methods. Simulations validate that the proposed method has lower computational complexity than existing approaches for estimating kernels of cubically nonlinear channels in real baseband OFDM systems.
This document describes the design of optimized reversible Vedic multipliers for high-speed low-power operations. It presents 2x2, 4x4, and 8x8 bit reversible Vedic multipliers based on the Urdhva Tiryakbhyam multiplication algorithm. The multipliers were designed using reversible logic gates like Feynman, Peres, and HNG gates. Simulation results showed the reversible Vedic multipliers have lower time delay, area, and number of logic units compared to normal Vedic multipliers. Potential applications of these high-speed low-power multipliers include fast Fourier transforms, public key cryptography, and embedded systems.
Expert systems : computer hardware problemmazlinapsas
This study introduces a method that will reduce the troubles to in diagnosing the computer hardware failures. An expert intelligent system using the rule-based technique is introduced to diagnose computer hardware failures. User or computer technician no need to check a part of computer hardware, one by one to diagnose computer hardware failure. User or computer technician just need to select category and the symptom or fact into a system, then a system will diagnose a computer hardware failure. The implementation includes types of computer hardware failure, computer condition, rules, and the solution that used in the flow chart technique and rule-based expert systems software. There are nine categories of computer hardware failure: power supply, hard drive, video, monitor, ATA drive, DVD, CD and Blu-ray playback, sound, motherboard, CPU and RAM. The results and analysis presented are computer hardware failure, conditions, rules, and solutions that used in the decision tables technique. Besides that, an analysis of the outputs and explanation about data mining by Weka engine are included to evaluate results. The testing for outputs is from black-box test and user acceptance test to evaluate the capability of study in diagnosing computer hardware failures in all conditions. Besides that, this study also showed that time is less to diagnose computer hardware failure when used expert system, than diagnose computer hardware failure manually
The document discusses error analysis in second language acquisition, noting that mistakes are a natural part of the learning process and can provide useful information about a learner's development, while errors reflect gaps in their underlying language system. It also examines different types of errors, sources of errors, approaches to identifying and categorizing errors, and considerations around providing feedback to and correcting errors of learners.
There are several types of computer errors that can occur from startup to operation. These include issues with video output, booting, loading the operating system, pop-up windows, hardware installation, safe mode not working, keyboard/mouse errors causing restarts, sound issues, and applications causing restarts. Operating system errors fall into categories like system errors caused by hardware or software issues, runtime errors from corrupted files, stop errors from RAM or hard drive issues, device manager errors from drivers or hardware, POST code errors from motherboard beeps for hardware issues, application errors, and browser status codes for website access problems.
This document discusses common types of computer system errors, including:
1. No video output errors where nothing displays on the monitor or the monitor flashes or stays orange.
2. Boot errors where the computer turns on but doesn't continue past displaying the processor or motherboard brand.
3. The operating system takes a long time to load or gets stuck in an endless loading screen.
4. Various types of errors are discussed that can cause problems like random restarts, no sound, or safe mode not working properly. The causes can range from hardware or software issues to corrupted files.
There are several types of computer errors that can occur at different stages of booting up or using a computer. These include hardware errors like no video output, software errors from corrupted files, and operating system errors. To diagnose issues, one should check connections, review error messages, update drivers, scan for malware, and test in safe mode. Common solutions involve reseating or replacing hardware, updating software, and ensuring proper ventilation and power supply.
M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems.Suchitra goudar
The document proposes designs for ternary logic gates based on single power supply voltage for CMOS technology. It describes the design of a simple ternary inverter (STI), negative ternary inverter (NTI), and positive ternary inverter (PTI) using only enhancement-type MOSFETs. Transistor widths and lengths are optimized to achieve the desired voltage transfer characteristics. Basic ternary logic gates including a ternary NAND (TNAND) and ternary NOR (TNOR) are also designed using a similar single-transistor approach. The proposed gate designs aim to reduce transistor count and power consumption compared to prior ternary logic designs.
This document discusses the design and analysis of a carbon nanotube field effect transistor (CNTFET) based D flip-flop (DFF). The proposed DFF uses a single clock phase and includes a reset function. Simulation results show it consumes significantly less power and has lower delay than a comparable 32nm CMOS DFF. Circuits like a gray counter and linear feedback shift register built using the CNTFET DFF achieve over 96% improvement in power delay product compared to CMOS designs. The document evaluates the performance of the proposed CNTFET DFF and compares it to a CMOS DFF in terms of propagation delay, power consumption, and other metrics. It demonstrates that CNTFET technology has potential
This document discusses the design and analysis of a D flip-flop (DFF) based on carbon nanotube field-effect transistors (CNTFETs). It presents a negative edge triggered DFF designed using pass transistor logic with single clock phase and reset function. Simulation results show the CNTFET DFF consumes significantly lower power and has less delay compared to a 32nm CMOS DFF. Application examples of the CNTFET DFF in a gray counter and linear feedback shift register also achieve over 90% improvement in power-delay product compared to CMOS designs. The document evaluates the performance of the CNTFET DFF and applications, demonstrating its advantages over CMOS technologies for low power, high performance applications
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYcscpconf
This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this
design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using
a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to
the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The
performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm.
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document analyzes and compares the performance of CMOS and FinFET logic technologies. It discusses key parameters for both technologies including gate area, gate capacitance, channel length, delay, subthreshold leakage current, and power dissipation. CMOS has advantages of low power consumption but suffers from short channel lengths. FinFET addresses this issue with a longer channel gate but higher power. The document provides equations to calculate parameters like power dissipation, delay dependence on input rise/fall time, impact of loading capacitance on gate delay, subthreshold leakage current, and threshold voltage for both CMOS and FinFET technologies.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
Introduction gadgets have gained a lot of attention.pdfbkbk37
The document discusses the increasing need for ultra-low power electronic devices due to advances in mobile technology and the internet of things. It covers limitations in further reducing power consumption and scaling transistors according to Moore's Law. Transition metal dichalcogenides are discussed as a potential channel material for ultra-low power transistors due to their ability to achieve high ON/OFF ratios even at the monolayer level. The document also mentions using technology computer-aided design (TCAD) tools like the Quantum Transport Simulator to model and optimize new materials and device geometries.
ECE 6030 Device Electronics discusses advances in low-power electronics and internet-connected devices. As transistors continue to shrink according to Moore's law, new challenges have emerged like increased OFF current. The document discusses approaches to overcoming these challenges, including new materials like transition metal dichalcogenides and their use in ultra-low power transistors. Device and circuit simulation tools are also discussed as important for optimizing new device designs without costly fabrication.
Set and seu analysis of cntfet based designs in harsh environmentseSAT Publishing House
This document analyzes the performance and radiation robustness of designs using carbon nanotube field-effect transistors (CNTFETs) compared to designs using metal-oxide-semiconductor field-effect transistors (MOSFETs). Simulations show that CNTFET logic gate designs demonstrate on average 45% improved resilience to single event transients compared to MOSFET designs. CNTFET latches also show improved energy and delay metrics with higher robustness than MOSFET latches. In an interconnect crossbar analysis, a CNTFET implementation occupied 25% less area and consumed 4 times less energy than a MOSFET implementation while handling the same critical charge levels.
Multi-carrier Equalization by Restoration of RedundancY (MERRY) for Adaptive ...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated and less complexity also involved by the simulation of the DST-DMT system.
Conducted EMI Reduction Accomplished via IEEE 1588 PTP for Grid Connected Par...idescitation
This paper introduces a distributed approach for
interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
methodology for achieving distributed interleaving is proposed,
along with a specific software based implementation approach
using the PTPdv2. The effectiveness of such methods in terms
of EMI reduction is experimentally validated in grid connected
Paralleled Solar Power Inverters.
The document discusses using IEEE 1588 Precision Time Protocol (PTP) to achieve distributed interleaving of paralleled solar power inverters. PTP allows networked devices to synchronize clocks with microsecond accuracy over Ethernet networks. The paper proposes using PTP to introduce phase shifts between inverter switching signals, which reduces electromagnetic interference and voltage ripple. Experimental results validated the EMI reduction achieved through this software-based distributed interleaving approach using PTP.
Low power 6 transistor latch design for portable devicesAlexander Decker
The document describes a proposed new 6-transistor latch design for use in portable devices to reduce power consumption. The 6-transistor design replaces the transmission gates in a conventional 8-transistor latch with pass transistors. Simulation results show the proposed design has lower power consumption and transistor count than the 8-transistor design, making it better suited for high-speed, low-power applications in mobile devices where battery life is important. The document also provides background on latch design and reviews the conventional 8-transistor latch design for comparison.
This document describes a novel design of ternary logic gates using carbon nanotube field-effect transistors (CNTFETs). The authors propose a CNTFET-based design for ternary logic gates that eliminates the need for large off-chip resistors used in previous designs. Simulation results show the proposed ternary logic gates consume significantly lower power and delay compared to previous resistive-load CNTFET gate implementations. When used in arithmetic circuits like a full adder and multiplier, the proposed ternary gates combined with binary gates can reduce power delay product by over 90%.
Accurate leakage current models for MOSFET nanoscale devices IJECEIAES
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (I sub ) was investigated in detail. The Band-To-Band Tunneling (I BTBT ) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (I G ) were also modeled and analyzed for parasitic (I GO ), inversion channel (I GC ), and gate substrate (I GB ). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.
Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology ...VLSICS Design
This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic Design Automation tools.
Analog and digital circuit design in 65 nm CMOS end of the road.docxZHKhan15
This document summarizes challenges in analog and digital circuit design for 65nm CMOS technology. It discusses how leakage currents, process variability, and interconnect delays increase as technologies scale down, posing new problems. A panel of experts will discuss whether 65nm marks the "end of the road" for continued design benefits from technology scaling or if issues can be addressed.
Similar to Design and Analysis of Power and Variability Aware Digital Summing Circuit (20)
Power System State Estimation - A ReviewIDES Editor
This document provides a review of power system state estimation techniques. It discusses both static and dynamic state estimation algorithms. For static state estimation, it covers weighted least squares, decoupled, and robust estimation methods. Weighted least squares is commonly used but can have numerical instability issues. Decoupled state estimation approximates the gain matrix for faster computation. Robust estimation uses M-estimators and other techniques to handle outliers and bad data. Dynamic state estimation applies Kalman filtering, leapfrog algorithms, and other methods to continuously monitor system states over time.
Artificial Intelligence Technique based Reactive Power Planning Incorporating...IDES Editor
This document summarizes a research paper that proposes using artificial intelligence techniques and FACTS controllers for reactive power planning in real-time power transmission systems. The paper formulates the reactive power planning problem and incorporates flexible AC transmission system (FACTS) devices like static VAR compensators (SVC), thyristor controlled series capacitors (TCSC), and unified power flow controllers (UPFC). Evolutionary algorithms like evolutionary programming (EP) and differential evolution (DE) are applied to find the optimal locations and settings of the FACTS controllers to minimize losses and costs. Simulation results on IEEE 30-bus and 72-bus Indian test systems show that UPFC performs best in reducing losses compared to SVC and TCSC.
Design and Performance Analysis of Genetic based PID-PSS with SVC in a Multi-...IDES Editor
Damping of power system oscillations with the help
of proposed optimal Proportional Integral Derivative Power
System Stabilizer (PID-PSS) and Static Var Compensator
(SVC)-based controllers are thoroughly investigated in this
paper. This study presents robust tuning of PID-PSS and
SVC-based controllers using Genetic Algorithms (GA) in
multi machine power systems by considering detailed model
of the generators (model 1.1). The effectiveness of FACTSbased
controllers in general and SVC-based controller in
particular depends upon their proper location. Modal
controllability and observability are used to locate SVC–based
controller. The performance of the proposed controllers is
compared with conventional lead-lag power system stabilizer
(CPSS) and demonstrated on 10 machines, 39 bus New England
test system. Simulation studies show that the proposed genetic
based PID-PSS with SVC based controller provides better
performance.
Optimal Placement of DG for Loss Reduction and Voltage Sag Mitigation in Radi...IDES Editor
This paper presents the need to operate the power
system economically and with optimum levels of voltages has
further led to an increase in interest in Distributed
Generation. In order to reduce the power losses and to improve
the voltage in the distribution system, distributed generators
(DGs) are connected to load bus. To reduce the total power
losses in the system, the most important process is to identify
the proper location for fixing and sizing of DGs. It presents a
new methodology using a new population based meta heuristic
approach namely Artificial Bee Colony algorithm(ABC) for
the placement of Distributed Generators(DG) in the radial
distribution systems to reduce the real power losses and to
improve the voltage profile, voltage sag mitigation. The power
loss reduction is important factor for utility companies because
it is directly proportional to the company benefits in a
competitive electricity market, while reaching the better power
quality standards is too important as it has vital effect on
customer orientation. In this paper an ABC algorithm is
developed to gain these goals all together. In order to evaluate
sag mitigation capability of the proposed algorithm, voltage
in voltage sensitive buses is investigated. An existing 20KV
network has been chosen as test network and results are
compared with the proposed method in the radial distribution
system.
Line Losses in the 14-Bus Power System Network using UPFCIDES Editor
Controlling power flow in modern power systems
can be made more flexible by the use of recent developments
in power electronic and computing control technology. The
Unified Power Flow Controller (UPFC) is a Flexible AC
transmission system (FACTS) device that can control all the
three system variables namely line reactance, magnitude and
phase angle difference of voltage across the line. The UPFC
provides a promising means to control power flow in modern
power systems. Essentially the performance depends on proper
control setting achievable through a power flow analysis
program. This paper presents a reliable method to meet the
requirements by developing a Newton-Raphson based load
flow calculation through which control settings of UPFC can
be determined for the pre-specified power flow between the
lines. The proposed method keeps Newton-Raphson Load Flow
(NRLF) algorithm intact and needs (little modification in the
Jacobian matrix). A MATLAB program has been developed to
calculate the control settings of UPFC and the power flow
between the lines after the load flow is converged. Case studies
have been performed on IEEE 5-bus system and 14-bus system
to show that the proposed method is effective. These studies
indicate that the method maintains the basic NRLF properties
such as fast computational speed, high degree of accuracy and
good convergence rate.
Study of Structural Behaviour of Gravity Dam with Various Features of Gallery...IDES Editor
The size and shape of opening in dam causes the
stress concentration, it also causes the stress variation in the
rest of the dam cross section. The gravity method of the analysis
does not consider the size of opening and the elastic property
of dam material. Thus the objective of study is comprises of
the Finite Element Method which considers the size of
opening, elastic property of material, and stress distribution
because of geometric discontinuity in cross section of dam.
Stress concentration inside the dam increases with the opening
in dam which results in the failure of dam. Hence it is
necessary to analyses large opening inside the dam. By making
the percentage area of opening constant and varying size and
shape of opening the analysis is carried out. For this purpose
a section of Koyna Dam is considered. Dam is defined as a
plane strain element in FEM, based on geometry and loading
condition. Thus this available information specified our path
of approach to carry out 2D plane strain analysis. The results
obtained are then compared mutually to get most efficient
way of providing large opening in the gravity dam.
Assessing Uncertainty of Pushover Analysis to Geometric ModelingIDES Editor
Pushover Analysis a popular tool for seismic
performance evaluation of existing and new structures and is
nonlinear Static procedure where in monotonically increasing
loads are applied to the structure till the structure is unable
to resist the further load .During the analysis, whatever the
strength of concrete and steel is adopted for analysis of
structure may not be the same when real structure is
constructed and the pushover analysis results are very sensitive
to material model adopted, geometric model adopted, location
of plastic hinges and in general to procedure followed by the
analyzer. In this paper attempt has been made to assess
uncertainty in pushover analysis results by considering user
defined hinges and frame modeled as bare frame and frame
with slab modeled as rigid diaphragm and results compared
with experimental observations. Uncertain parameters
considered includes the strength of concrete, strength of steel
and cover to the reinforcement which are randomly generated
and incorporated into the analysis. The results are then
compared with experimental observations.
Secure Multi-Party Negotiation: An Analysis for Electronic Payments in Mobile...IDES Editor
This document summarizes and analyzes secure multi-party negotiation protocols for electronic payments in mobile computing. It presents a framework for secure multi-party decision protocols using lightweight implementations. The main focus is on synchronizing security features to avoid agreement manipulation and reduce user traffic. The paper describes negotiation between an auctioneer and bidders, showing multiparty security is better than existing systems. It analyzes the performance of encryption algorithms like ECC, XTR, and RSA for use in the multiparty negotiation protocols.
Selfish Node Isolation & Incentivation using Progressive ThresholdsIDES Editor
The problems associated with selfish nodes in
MANET are addressed by a collaborative watchdog approach
which reduces the detection time for selfish nodes thereby
improves the performance and accuracy of watchdogs[1]. In
the related works they make use of credit based systems, reputation
based mechanisms, pathrater and watchdog mechanism
to detect such selfish nodes. In this paper we follow an approach
of collaborative watchdog which reduces the detection
time for selfish nodes and also involves the removal of such
selfish nodes based on some progressively assessed thresholds.
The threshold gives the nodes a chance to stop misbehaving
before it is permanently deleted from the network.
The node passes through several isolation processes before it
is permanently removed. Another version of AODV protocol
is used here which allows the simulation of selfish nodes in
NS2 by adding or modifying log files in the protocol.
Various OSI Layer Attacks and Countermeasure to Enhance the Performance of WS...IDES Editor
Wireless sensor networks are networks having non
wired infrastructure and dynamic topology. In OSI model each
layer is prone to various attacks, which halts the performance
of a network .In this paper several attacks on four layers of
OSI model are discussed and security mechanism is described
to prevent attack in network layer i.e wormhole attack. In
Wormhole attack two or more malicious nodes makes a covert
channel which attracts the traffic towards itself by depicting a
low latency link and then start dropping and replaying packets
in the multi-path route. This paper proposes promiscuous mode
method to detect and isolate the malicious node during
wormhole attack by using Ad-hoc on demand distance vector
routing protocol (AODV) with omnidirectional antenna. The
methodology implemented notifies that the nodes which are
not participating in multi-path routing generates an alarm
message during delay and then detects and isolate the
malicious node from network. We also notice that not only
the same kind of attacks but also the same kind of
countermeasures can appear in multiple layer. For example,
misbehavior detection techniques can be applied to almost all
the layers we discussed.
Responsive Parameter based an AntiWorm Approach to Prevent Wormhole Attack in...IDES Editor
The recent advancements in the wireless technology
and their wide-spread deployment have made remarkable
enhancements in efficiency in the corporate and industrial
and Military sectors The increasing popularity and usage of
wireless technology is creating a need for more secure wireless
Ad hoc networks. This paper aims researched and developed
a new protocol that prevents wormhole attacks on a ad hoc
network. A few existing protocols detect wormhole attacks but
they require highly specialized equipment not found on most
wireless devices. This paper aims to develop a defense against
wormhole attacks as an Anti-worm protocol which is based on
responsive parameters, that does not require as a significant
amount of specialized equipment, trick clock synchronization,
no GPS dependencies.
Cloud Security and Data Integrity with Client Accountability FrameworkIDES Editor
This document summarizes a proposed cloud security and data integrity framework that provides client accountability. The framework aims to address issues like lack of user control over cloud data, need for data transparency and tracking, and ensuring data integrity. It proposes using JAR (Java Archive) files for data sharing due to benefits like portability. The framework incorporates client-side verification using MD5 hashing, digital signature-based authentication of JAR files, and use of HMAC to ensure data integrity. It also uses password-based encryption of log files to keep them tamper-proof. The framework is intended to provide both accountability and security for data sharing in cloud environments.
Genetic Algorithm based Layered Detection and Defense of HTTP BotnetIDES Editor
A System state in HTTP botnet uses HTTP protocol
for the creation of chain of Botnets thereby compromising
other systems. By using HTTP protocol and port number 80,
attacks can not only be hidden but also pass through the
firewall without being detected. The DPR based detection
leads to better analysis of botnet attacks [3]. However, it
provides only probabilistic detection of the attacker and also
time consuming and error prone. This paper proposes a Genetic
algorithm based layered approach for detecting as well as
preventing botnet attacks. The paper reviews p2p firewall
implementation which forms the basis of filtering.
Performance evaluation is done based on precision, F-value
and probability. Layered approach reduces the computation
and overall time requirement [7]. Genetic algorithm promises
a low false positive rate.
Enhancing Data Storage Security in Cloud Computing Through SteganographyIDES Editor
This document summarizes a research paper that proposes a method for enhancing data security in cloud computing through steganography. The method hides user data in digital images stored on cloud servers. When data needs to be accessed, it is extracted from the images. The document outlines the cloud architecture and security issues addressed. It then describes the proposed system architecture, security model, and data storage and retrieval process. Data is partitioned and hidden in multiple images to improve security. The goal is to prevent unauthorized access to user data stored on cloud servers.
The main tasks of a Wireless Sensor Network
(WSN) are data collection from its nodes and communication
of this data to the base station (BS). The protocols used for
communication among the WSN nodes and between the WSN
and the BS, must consider the resource constraints of nodes,
battery energy, computational capabilities and memory. The
WSN applications involve unattended operation of the network
over an extended period of time. In order to extend the lifetime
of a WSN, efficient routing protocols need to be adopted. The
proposed low power routing protocol based on tree-based
network structure reliably forwards the measured data towards
the BS using TDMA. An energy consumption analysis of the
WSN making use of this protocol is also carried out. It is
found that the network is energy efficient with an average
duty cycle of 0:7% for the WSN nodes. The OmNET++
simulation platform along with MiXiM framework is made
use of.
Permutation of Pixels within the Shares of Visual Cryptography using KBRP for...IDES Editor
The security of authentication of internet based
co-banking services should not be susceptible to high risks.
The passwords are highly vulnerable to virus attacks due to
the lack of high end embedding of security methods. In order
for the passwords to be more secure, people are generally
compelled to select jumbled up character based passwords
which are not only less memorable but are also equally prone
to insecurity. Multiple use of distributed shares has been
studied to solve the problem of authentication by algorithms
based on thresholding of pixels in image processing and visual
cryptography concepts where the subset of shares is considered
for the recovery of the original image for authentication using
correlation function[1][2].The main disadvantage in the above
study is the plain storage of shares and also one of the shares
is being supplied to the customer, which will lead to the
possibility of misuse by a third party. This paper proposes a
technique for scrambling of pixels by key based random
permutation (KBRP) within the shares before the
authentication has been attempted. Total number of shares to
be created is dependent on the multiplicity of ownership of
the account. By this method the problem of uncertainty among
the customers with regard to security, storage, retrieval of
holding of half of the shares is minimized.
This paper presents a trifocal Rotman Lens Design
approach. The effects of focal ratio and element spacing on
the performance of Rotman Lens are described. A three beam
prototype feeding 4 element antenna array working in L-band
has been simulated using RLD v1.7 software. Simulated
results show that the simulated lens has a return loss of –
12.4dB at 1.8GHz. Beam to array port phase error variation
with change in the focal ratio and element spacing has also
been investigated.
Band Clustering for the Lossless Compression of AVIRIS Hyperspectral ImagesIDES Editor
Hyperspectral images can be efficiently compressed
through a linear predictive model, as for example the one
used in the SLSQ algorithm. In this paper we exploit this
predictive model on the AVIRIS images by individuating,
through an off-line approach, a common subset of bands, which
are not spectrally related with any other bands. These bands
are not useful as prediction reference for the SLSQ 3-D
predictive model and we need to encode them via other
prediction strategies which consider only spatial correlation.
We have obtained this subset by clustering the AVIRIS bands
via the clustering by compression approach. The main result
of this paper is the list of the bands, not related with the
others, for AVIRIS images. The clustering trees obtained for
AVIRIS and the relationship among bands they depict is also
an interesting starting point for future research.
Microelectronic Circuit Analogous to Hydrogen Bonding Network in Active Site ...IDES Editor
A microelectronic circuit of block-elements
functionally analogous to two hydrogen bonding networks is
investigated. The hydrogen bonding networks are extracted
from â-lactamase protein and are formed in its active site.
Each hydrogen bond of the network is described in equivalent
electrical circuit by three or four-terminal block-element.
Each block-element is coded in Matlab. Static and dynamic
analyses are performed. The resultant microelectronic circuit
analogous to the hydrogen bonding network operates as
current mirror, sine pulse source, triangular pulse source as
well as signal modulator.
Texture Unit based Monocular Real-world Scene Classification using SOM and KN...IDES Editor
In this paper a method is proposed to discriminate
real world scenes in to natural and manmade scenes of similar
depth. Global-roughness of a scene image varies as a function
of image-depth. Increase in image depth leads to increase in
roughness in manmade scenes; on the contrary natural scenes
exhibit smooth behavior at higher image depth. This particular
arrangement of pixels in scene structure can be well explained
by local texture information in a pixel and its neighborhood.
Our proposed method analyses local texture information of a
scene image using texture unit matrix. For final classification
we have used both supervised and unsupervised learning using
K-Nearest Neighbor classifier (KNN) and Self Organizing
Map (SOM) respectively. This technique is useful for online
classification due to very less computational complexity.
Project Management Semester Long Project - Acuityjpupo2018
Acuity is an innovative learning app designed to transform the way you engage with knowledge. Powered by AI technology, Acuity takes complex topics and distills them into concise, interactive summaries that are easy to read & understand. Whether you're exploring the depths of quantum mechanics or seeking insight into historical events, Acuity provides the key information you need without the burden of lengthy texts.
Skybuffer SAM4U tool for SAP license adoptionTatiana Kojar
Manage and optimize your license adoption and consumption with SAM4U, an SAP free customer software asset management tool.
SAM4U, an SAP complimentary software asset management tool for customers, delivers a detailed and well-structured overview of license inventory and usage with a user-friendly interface. We offer a hosted, cost-effective, and performance-optimized SAM4U setup in the Skybuffer Cloud environment. You retain ownership of the system and data, while we manage the ABAP 7.58 infrastructure, ensuring fixed Total Cost of Ownership (TCO) and exceptional services through the SAP Fiori interface.
Let's Integrate MuleSoft RPA, COMPOSER, APM with AWS IDP along with Slackshyamraj55
Discover the seamless integration of RPA (Robotic Process Automation), COMPOSER, and APM with AWS IDP enhanced with Slack notifications. Explore how these technologies converge to streamline workflows, optimize performance, and ensure secure access, all while leveraging the power of AWS IDP and real-time communication via Slack notifications.
Unlock the Future of Search with MongoDB Atlas_ Vector Search Unleashed.pdfMalak Abu Hammad
Discover how MongoDB Atlas and vector search technology can revolutionize your application's search capabilities. This comprehensive presentation covers:
* What is Vector Search?
* Importance and benefits of vector search
* Practical use cases across various industries
* Step-by-step implementation guide
* Live demos with code snippets
* Enhancing LLM capabilities with vector search
* Best practices and optimization strategies
Perfect for developers, AI enthusiasts, and tech leaders. Learn how to leverage MongoDB Atlas to deliver highly relevant, context-aware search results, transforming your data retrieval process. Stay ahead in tech innovation and maximize the potential of your applications.
#MongoDB #VectorSearch #AI #SemanticSearch #TechInnovation #DataScience #LLM #MachineLearning #SearchTechnology
Ivanti’s Patch Tuesday breakdown goes beyond patching your applications and brings you the intelligence and guidance needed to prioritize where to focus your attention first. Catch early analysis on our Ivanti blog, then join industry expert Chris Goettl for the Patch Tuesday Webinar Event. There we’ll do a deep dive into each of the bulletins and give guidance on the risks associated with the newly-identified vulnerabilities.
Digital Marketing Trends in 2024 | Guide for Staying AheadWask
https://www.wask.co/ebooks/digital-marketing-trends-in-2024
Feeling lost in the digital marketing whirlwind of 2024? Technology is changing, consumer habits are evolving, and staying ahead of the curve feels like a never-ending pursuit. This e-book is your compass. Dive into actionable insights to handle the complexities of modern marketing. From hyper-personalization to the power of user-generated content, learn how to build long-term relationships with your audience and unlock the secrets to success in the ever-shifting digital landscape.
Programming Foundation Models with DSPy - Meetup SlidesZilliz
Prompting language models is hard, while programming language models is easy. In this talk, I will discuss the state-of-the-art framework DSPy for programming foundation models with its powerful optimizers and runtime constraint system.
Fueling AI with Great Data with Airbyte WebinarZilliz
This talk will focus on how to collect data from a variety of sources, leveraging this data for RAG and other GenAI use cases, and finally charting your course to productionalization.
Generating privacy-protected synthetic data using Secludy and MilvusZilliz
During this demo, the founders of Secludy will demonstrate how their system utilizes Milvus to store and manipulate embeddings for generating privacy-protected synthetic data. Their approach not only maintains the confidentiality of the original data but also enhances the utility and scalability of LLMs under privacy constraints. Attendees, including machine learning engineers, data scientists, and data managers, will witness first-hand how Secludy's integration with Milvus empowers organizations to harness the power of LLMs securely and efficiently.
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
available on those devices, but many of the features provide convenience and capability but sacrifice security. This best practices guide outlines steps the users can take to better protect personal devices and information.
Building Production Ready Search Pipelines with Spark and MilvusZilliz
Spark is the widely used ETL tool for processing, indexing and ingesting data to serving stack for search. Milvus is the production-ready open-source vector database. In this talk we will show how to use Spark to process unstructured data to extract vector representations, and push the vectors to Milvus vector database for search serving.
Have you ever been confused by the myriad of choices offered by AWS for hosting a website or an API?
Lambda, Elastic Beanstalk, Lightsail, Amplify, S3 (and more!) can each host websites + APIs. But which one should we choose?
Which one is cheapest? Which one is fastest? Which one will scale to meet our needs?
Join me in this session as we dive into each AWS hosting service to determine which one is best for your scenario and explain why!
HCL Notes and Domino License Cost Reduction in the World of DLAUpanagenda
Webinar Recording: https://www.panagenda.com/webinars/hcl-notes-and-domino-license-cost-reduction-in-the-world-of-dlau/
The introduction of DLAU and the CCB & CCX licensing model caused quite a stir in the HCL community. As a Notes and Domino customer, you may have faced challenges with unexpected user counts and license costs. You probably have questions on how this new licensing approach works and how to benefit from it. Most importantly, you likely have budget constraints and want to save money where possible. Don’t worry, we can help with all of this!
We’ll show you how to fix common misconfigurations that cause higher-than-expected user counts, and how to identify accounts which you can deactivate to save money. There are also frequent patterns that can cause unnecessary cost, like using a person document instead of a mail-in for shared mailboxes. We’ll provide examples and solutions for those as well. And naturally we’ll explain the new licensing model.
Join HCL Ambassador Marc Thomas in this webinar with a special guest appearance from Franz Walder. It will give you the tools and know-how to stay on top of what is going on with Domino licensing. You will be able lower your cost through an optimized configuration and keep it low going forward.
These topics will be covered
- Reducing license cost by finding and fixing misconfigurations and superfluous accounts
- How do CCB and CCX licenses really work?
- Understanding the DLAU tool and how to best utilize it
- Tips for common problem areas, like team mailboxes, functional/test users, etc
- Practical examples and best practices to implement right away
Webinar: Designing a schema for a Data WarehouseFederico Razzoli
Are you new to data warehouses (DWH)? Do you need to check whether your data warehouse follows the best practices for a good design? In both cases, this webinar is for you.
A data warehouse is a central relational database that contains all measurements about a business or an organisation. This data comes from a variety of heterogeneous data sources, which includes databases of any type that back the applications used by the company, data files exported by some applications, or APIs provided by internal or external services.
But designing a data warehouse correctly is a hard task, which requires gathering information about the business processes that need to be analysed in the first place. These processes must be translated into so-called star schemas, which means, denormalised databases where each table represents a dimension or facts.
We will discuss these topics:
- How to gather information about a business;
- Understanding dictionaries and how to identify business entities;
- Dimensions and facts;
- Setting a table granularity;
- Types of facts;
- Types of dimensions;
- Snowflakes and how to avoid them;
- Expanding existing dimensions and facts.
Your One-Stop Shop for Python Success: Top 10 US Python Development Providersakankshawande
Simplify your search for a reliable Python development partner! This list presents the top 10 trusted US providers offering comprehensive Python development services, ensuring your project's success from conception to completion.