Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
At this present scenario, the demand of the system capacity is very high in wireless network. MIMO
technology is used from the last decade to provide this requirement for wireless network antenna
technology. MIMO channels are mostly used for advanced antenna array technology. But it is most
important to control the error rate with enhanced system capacity in MIMO for present-day progressive
wireless communication. This paper explores the frame error rate with respect to different path gain of
MIMO channel. This work has been done in different fading scenario and produces a comparative analysis
of MIMO on the basis of those fading models in various conditions. Here, it is to be considered that
modulation technique as QPSK to observe these comparative evaluations for different Doppler frequencies.
From the comparative analysis, minimum amount of frame error rate is viewed for Rician distribution at
LOS path Doppler shift of 0 Hz. At last, this work is concluded with a comparative bit error rate study on
the basis of singular parameters at different SNR levels to produce the system performance for uncoded
QPSK modulation.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
At this present scenario, the demand of the system capacity is very high in wireless network. MIMO
technology is used from the last decade to provide this requirement for wireless network antenna
technology. MIMO channels are mostly used for advanced antenna array technology. But it is most
important to control the error rate with enhanced system capacity in MIMO for present-day progressive
wireless communication. This paper explores the frame error rate with respect to different path gain of
MIMO channel. This work has been done in different fading scenario and produces a comparative analysis
of MIMO on the basis of those fading models in various conditions. Here, it is to be considered that
modulation technique as QPSK to observe these comparative evaluations for different Doppler frequencies.
From the comparative analysis, minimum amount of frame error rate is viewed for Rician distribution at
LOS path Doppler shift of 0 Hz. At last, this work is concluded with a comparative bit error rate study on
the basis of singular parameters at different SNR levels to produce the system performance for uncoded
QPSK modulation.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Multi carrier equalization by restoration of redundanc y (merry) for adaptive...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The
performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed
DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated
and less complexity also involved by the simulation of the DST-DMT system.
Study on transmission over Nakagami-m fading channel for multiple access sche...TELKOMNIKA JOURNAL
In this paper, a downlink performance in non-orthogonal multiple access (NOMA) system is considered. With regard to different priority for two NOMA users, we exploit the closed-form expressions of outage probability over wireless fading channel following Nakagami-m fading. The fixed power allocation factor scheme is examined to reduce the complexity in computation regarding performance analysis. In our analysis, perfect successive interference cancellation (SIC) is applied in order to achieve perfect signal decoding operation. Simulation results show that the considered NOMA downlink scheme is affected by transmit SNR, power allocation factors, fading parameters.
Combining SFBC_OFDM Systems with SVD Assisted Multiuser Transmitter and Multi...IOSR Journals
Abstract: In this work, we exploit the SVD assisted multiuser transmitter (MUT) and multiuser detector (MUD) technique, using downlink (DL) preprocessing transmitter and DL postprocessing receiver matrice .In combination with space frequency block coding (SFBC). And also propose the precoded DL transmission scheme, were the both proposed schemes take advantage of the channel state information (CSI) of all users at the base station (BS), but only of the mobile station (MS)’s own CSI, to decompose the MU MIMO channels into parallel single input single output (SISO), these two proposed schemes are compared to the vertical layered space time (V_BLAST) combined with SFBC (SFBC_VBLAST). Our Simulation results show that the performance of the proposed scheme with DL Zero Forcing (ZF) transmitter for interference canceller outperforms the SFBC_VBLAST and the precoded DL schemes with ZF receiver in frequency selective fading channels. Keywords – Post processing, Preprocessing,, SFBC, SVD, ZF.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance evaluation on the basis of bit error rate for different order of ...ijmnct
Today, we have required to accommodate a large number of users under a single base station. This can be
possible only if we have some flexibility over the spectrum. Previously we have lots of multiplexing methods
to accommodate large number of signals in time and frequency domain. But now we have required to
accommodate a large number of users in the same bandwidth, without any fading over the received signal.
So, orthogonality can be maintained over the frequency response. This technology is now more popular in
the mobile communication domain, called Orthogonal Frequency Division Multiplexing (OFDM). Actually
user data can be converted into the parallel form and then they are modulated using digital modulation
techniques. Finally, they have followed by OFDM Modulator and cyclic prefix can be inserted into the
OFDM symbols. Here, I have worked on the measurement of Bit error rate for different modulation
techniques in OFDM technology. It has been considered that subchannel size is not constant. According to
that I have concluded the overall idea regarding the performance under OFDM technology.
To design most reliable wireless communication system we need an efficient method which can be proposed in this paper is V-BLAST technique which is most powerful tool in MIMO system. To improve the channel capacity and data rate efficiently we need manifold antennas together with the transmitter and receiver. In this paper we have analysed different equalizers performance using V-BLAST algorithm. We have proposed two methods i.e low complexity QR algorithm and another is consecutive iterations reduction method. This methods compare with traditional finding methods such as ZF, MMSE, SIC and ML. The proposed algorithm shows that it not only reduce the computational complexity but we can achieve significant bit error rate (BER) and probability error compared to traditional VBLAST techniques.
BER Performance of MPSK and MQAM in 2x2 Almouti MIMO Systemsijistjournal
Almouti published the error performance of the 2x2 space-time transmit diversity scheme using BPSK. One of the key techniques employed for correcting such errors is the Quadrature amplitude modulation (QAM) because of its efficiency in power and bandwidth.. In this paper we explore the error performance of the 2x2 MIMO system using the Almouti space-time codes for higher order PSK and M-ary QAM. MATLAB was used to simulate the system; assuming slow fading Rayleigh channel and additive white Gaussian noise. The simulated performance curves were compared and evaluated with theoretical curves obtained using BER tool on the MATLAB by setting parameters for random generators. The results shows that the technique used do find a place in correcting error rates of QAM system of higher modulation schemes. The model can equally be used not only for the criteria of adaptive modulation but for a platform to design other modulation systems as well.
Performance Analysis of MIMO-OFDM System Using QOSTBC Code Structure for M-PSKCSCJournals
MIMO-OFDM system has been currently recognized as one of the most competitive technology for 4G mobile wireless systems. MIMO-OFDM system can compensate for the lacks of MIMO systems and give play to the advantages of OFDM system. In this paper, a general Quasi orthogonal space time block code (QOSTBC) structure is proposed for multiple-input multiple-output–orthogonal frequency-division multiplexing (MIMO-OFDM) systems for 4X4 antenna configuration. The signal detection technology used in this paper for MIMO-OFDM system is Zero-Forcing Equalization (linear detection technique). In this paper the analysis of high level of modulations (i.e. M-PSK for different values of M) on MIMO-OFDM system is presented. Here AWGN and Rayleigh channels have been used for analysis purpose and their effect on BER for high data rates have been presented. The proposed MIMO-OFDM system with QOSTBC using 4X4 antenna configuration has better performance in terms of BER vs SNR than the other systems.
A Potent MIMO–OFDM System Designed for Optimum BER and its Performance Anal...inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR ...VLSICS Design
Since the current demand for high-resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable TV or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track
and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
SECURED TEXT MESSAGE TRANSMISSION IN PRE -CHANNEL EQUALIZATION BASED MIMO- OF...IJNSA Journal
In this paper, we made a comprehensive performance evaluative study of a secured MIMO Orthogonal Frequency-Division Multiplexing wireless communication system with implementation of two pre channel equalization techniques such as Pre-Minimum Mean Square Error (Pre-MMSE) and Pre-Zero
Forcing(Pre-ZF) under QPSK and QAM digital modulations. The simulated system deploys three channel coding techniques(1/2-rated Convolutional, CRC and BCH). In the present simulated system, text message transmission has been secured with concatenated implementation of Electronic Codebook (ECB)
and Cipher Feedback(CFB) cryptographic algorithm. It is remarked from simulation results that the MIMO OFDM system outperforms with pre-ZF channel equalization,QAM digital modulation and BCH channel coding schemes under fading channels(AWGN and Raleigh).In Pre-MMSE/pre-ZF channel
equalization scheme, the system shows comparatively worst performance in convolutional channel coding scheme with QAM/QPSK digital modulation. With increase in noise power as compared to signal power, the system is found to have shown performance deterioration
Performance analysis of negative group delay network using MIMO techniqueTELKOMNIKA JOURNAL
This study introduces comparative consequences that determine the bit error rate enhancements, resultant from adopting a proposed MIMO wireless model in this study. The antenna configurations for this model uses new small microstrip slotted patch antenna with multiple frequency bands at strategic operating frequencies of 2.4, 4.4, and 5.55 respectively. The S11 response of the proposed antenna for IEEE802.11 MIMO wireless network has been highly appropriate to be adopted with MIMO antenna system. The negative group delay (NGD) response is the most significant feature for projected MIMO antenna. The NGD stands for a counterintuitive singularity that interacts time advancement with wave propagation. These improvements are employed for increasing a reliability of instantly conveyed data streams, enhance the capacity of the wireless configuration and decrease the bit error rate (BER) of adopted wireless system. In addition to antenna scattering response, the enhancements have been analysed in term of BER for different MIMO topologies.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
New Adaptive Cooperative-MIMO for LTE Technologyijtsrd
Multiple Input Multiple Output (MIMO) systems have been widely used in an area of wireless cellular communication system, providing the both increased capacity and reliability. However, the use of multiple antennas in mobile terminals may not be very practical due to limited space and other implementation issues. In this paper, cooperative MIMO has been used in a way to optimise the implementation and working of conventional MIMO systems in terms of BER and Spectral Efficiency while maintaining a minimal number of antennas on each handset. Cooperative MIMO with V-BLAST transmission over Rayleigh flat fading channels and amplify and forward protocol with one relay node for modulation techniques like BPSK, QPSK, QAM using various decoding techniques has been analysed. Decoding algorithms like ZF, MMSE and ML have been analysed with respect to their BER performances. Since, there is throughput loss in cooperative MIMO due to extra resources required for relaying, adaptive modulation has been used with C-MIMO to meet the demands for high data rates in Long Term Evolution Network. Sukhreet Kaur | Dr. Amita Soni"New Adaptive Cooperative-MIMO for LTE Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd12919.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/12919/new-adaptive-cooperative-mimo-for-lte-technology/sukhreet-kaur
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TEC...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
Multi carrier equalization by restoration of redundanc y (merry) for adaptive...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The
performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed
DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated
and less complexity also involved by the simulation of the DST-DMT system.
Study on transmission over Nakagami-m fading channel for multiple access sche...TELKOMNIKA JOURNAL
In this paper, a downlink performance in non-orthogonal multiple access (NOMA) system is considered. With regard to different priority for two NOMA users, we exploit the closed-form expressions of outage probability over wireless fading channel following Nakagami-m fading. The fixed power allocation factor scheme is examined to reduce the complexity in computation regarding performance analysis. In our analysis, perfect successive interference cancellation (SIC) is applied in order to achieve perfect signal decoding operation. Simulation results show that the considered NOMA downlink scheme is affected by transmit SNR, power allocation factors, fading parameters.
Combining SFBC_OFDM Systems with SVD Assisted Multiuser Transmitter and Multi...IOSR Journals
Abstract: In this work, we exploit the SVD assisted multiuser transmitter (MUT) and multiuser detector (MUD) technique, using downlink (DL) preprocessing transmitter and DL postprocessing receiver matrice .In combination with space frequency block coding (SFBC). And also propose the precoded DL transmission scheme, were the both proposed schemes take advantage of the channel state information (CSI) of all users at the base station (BS), but only of the mobile station (MS)’s own CSI, to decompose the MU MIMO channels into parallel single input single output (SISO), these two proposed schemes are compared to the vertical layered space time (V_BLAST) combined with SFBC (SFBC_VBLAST). Our Simulation results show that the performance of the proposed scheme with DL Zero Forcing (ZF) transmitter for interference canceller outperforms the SFBC_VBLAST and the precoded DL schemes with ZF receiver in frequency selective fading channels. Keywords – Post processing, Preprocessing,, SFBC, SVD, ZF.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance evaluation on the basis of bit error rate for different order of ...ijmnct
Today, we have required to accommodate a large number of users under a single base station. This can be
possible only if we have some flexibility over the spectrum. Previously we have lots of multiplexing methods
to accommodate large number of signals in time and frequency domain. But now we have required to
accommodate a large number of users in the same bandwidth, without any fading over the received signal.
So, orthogonality can be maintained over the frequency response. This technology is now more popular in
the mobile communication domain, called Orthogonal Frequency Division Multiplexing (OFDM). Actually
user data can be converted into the parallel form and then they are modulated using digital modulation
techniques. Finally, they have followed by OFDM Modulator and cyclic prefix can be inserted into the
OFDM symbols. Here, I have worked on the measurement of Bit error rate for different modulation
techniques in OFDM technology. It has been considered that subchannel size is not constant. According to
that I have concluded the overall idea regarding the performance under OFDM technology.
To design most reliable wireless communication system we need an efficient method which can be proposed in this paper is V-BLAST technique which is most powerful tool in MIMO system. To improve the channel capacity and data rate efficiently we need manifold antennas together with the transmitter and receiver. In this paper we have analysed different equalizers performance using V-BLAST algorithm. We have proposed two methods i.e low complexity QR algorithm and another is consecutive iterations reduction method. This methods compare with traditional finding methods such as ZF, MMSE, SIC and ML. The proposed algorithm shows that it not only reduce the computational complexity but we can achieve significant bit error rate (BER) and probability error compared to traditional VBLAST techniques.
BER Performance of MPSK and MQAM in 2x2 Almouti MIMO Systemsijistjournal
Almouti published the error performance of the 2x2 space-time transmit diversity scheme using BPSK. One of the key techniques employed for correcting such errors is the Quadrature amplitude modulation (QAM) because of its efficiency in power and bandwidth.. In this paper we explore the error performance of the 2x2 MIMO system using the Almouti space-time codes for higher order PSK and M-ary QAM. MATLAB was used to simulate the system; assuming slow fading Rayleigh channel and additive white Gaussian noise. The simulated performance curves were compared and evaluated with theoretical curves obtained using BER tool on the MATLAB by setting parameters for random generators. The results shows that the technique used do find a place in correcting error rates of QAM system of higher modulation schemes. The model can equally be used not only for the criteria of adaptive modulation but for a platform to design other modulation systems as well.
Performance Analysis of MIMO-OFDM System Using QOSTBC Code Structure for M-PSKCSCJournals
MIMO-OFDM system has been currently recognized as one of the most competitive technology for 4G mobile wireless systems. MIMO-OFDM system can compensate for the lacks of MIMO systems and give play to the advantages of OFDM system. In this paper, a general Quasi orthogonal space time block code (QOSTBC) structure is proposed for multiple-input multiple-output–orthogonal frequency-division multiplexing (MIMO-OFDM) systems for 4X4 antenna configuration. The signal detection technology used in this paper for MIMO-OFDM system is Zero-Forcing Equalization (linear detection technique). In this paper the analysis of high level of modulations (i.e. M-PSK for different values of M) on MIMO-OFDM system is presented. Here AWGN and Rayleigh channels have been used for analysis purpose and their effect on BER for high data rates have been presented. The proposed MIMO-OFDM system with QOSTBC using 4X4 antenna configuration has better performance in terms of BER vs SNR than the other systems.
A Potent MIMO–OFDM System Designed for Optimum BER and its Performance Anal...inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR ...VLSICS Design
Since the current demand for high-resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable TV or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track
and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
SECURED TEXT MESSAGE TRANSMISSION IN PRE -CHANNEL EQUALIZATION BASED MIMO- OF...IJNSA Journal
In this paper, we made a comprehensive performance evaluative study of a secured MIMO Orthogonal Frequency-Division Multiplexing wireless communication system with implementation of two pre channel equalization techniques such as Pre-Minimum Mean Square Error (Pre-MMSE) and Pre-Zero
Forcing(Pre-ZF) under QPSK and QAM digital modulations. The simulated system deploys three channel coding techniques(1/2-rated Convolutional, CRC and BCH). In the present simulated system, text message transmission has been secured with concatenated implementation of Electronic Codebook (ECB)
and Cipher Feedback(CFB) cryptographic algorithm. It is remarked from simulation results that the MIMO OFDM system outperforms with pre-ZF channel equalization,QAM digital modulation and BCH channel coding schemes under fading channels(AWGN and Raleigh).In Pre-MMSE/pre-ZF channel
equalization scheme, the system shows comparatively worst performance in convolutional channel coding scheme with QAM/QPSK digital modulation. With increase in noise power as compared to signal power, the system is found to have shown performance deterioration
Performance analysis of negative group delay network using MIMO techniqueTELKOMNIKA JOURNAL
This study introduces comparative consequences that determine the bit error rate enhancements, resultant from adopting a proposed MIMO wireless model in this study. The antenna configurations for this model uses new small microstrip slotted patch antenna with multiple frequency bands at strategic operating frequencies of 2.4, 4.4, and 5.55 respectively. The S11 response of the proposed antenna for IEEE802.11 MIMO wireless network has been highly appropriate to be adopted with MIMO antenna system. The negative group delay (NGD) response is the most significant feature for projected MIMO antenna. The NGD stands for a counterintuitive singularity that interacts time advancement with wave propagation. These improvements are employed for increasing a reliability of instantly conveyed data streams, enhance the capacity of the wireless configuration and decrease the bit error rate (BER) of adopted wireless system. In addition to antenna scattering response, the enhancements have been analysed in term of BER for different MIMO topologies.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
New Adaptive Cooperative-MIMO for LTE Technologyijtsrd
Multiple Input Multiple Output (MIMO) systems have been widely used in an area of wireless cellular communication system, providing the both increased capacity and reliability. However, the use of multiple antennas in mobile terminals may not be very practical due to limited space and other implementation issues. In this paper, cooperative MIMO has been used in a way to optimise the implementation and working of conventional MIMO systems in terms of BER and Spectral Efficiency while maintaining a minimal number of antennas on each handset. Cooperative MIMO with V-BLAST transmission over Rayleigh flat fading channels and amplify and forward protocol with one relay node for modulation techniques like BPSK, QPSK, QAM using various decoding techniques has been analysed. Decoding algorithms like ZF, MMSE and ML have been analysed with respect to their BER performances. Since, there is throughput loss in cooperative MIMO due to extra resources required for relaying, adaptive modulation has been used with C-MIMO to meet the demands for high data rates in Long Term Evolution Network. Sukhreet Kaur | Dr. Amita Soni"New Adaptive Cooperative-MIMO for LTE Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd12919.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/12919/new-adaptive-cooperative-mimo-for-lte-technology/sukhreet-kaur
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TEC...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Design of carbon nanotube field effect transistor (CNTFET) small signal model IJECEIAES
The progress of Carbon Nanotube Field Effect Transistor (CNTFET) devices has facilitated the trimness of mobile phones, computers and all other electronic devices. CNTFET devices contribute to model these electronics instruments that require designing the devices. This research consists of the design and verification of the CNTFET device's small signal model. Scattering parameters (S-parameters) is extracted from the CNTFET model to construct equivalent small model circuit. Current sources, capacitors and resistors are involved to evaluate this equivalent circuit. S-parameters and small signal models are elaborated to analyze using a technique to form the small signal equivalent circuit model. In this design modeling process, at first intrinsic device's Y-parameters are determined. After that series of impedances are calculated. At last, Y-parameters model are transformed to add parasitic capacitances. The analysis result shows the acquiring high frequency performances are obtained from this equivalent circuit.
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
Conducted EMI Reduction Accomplished via IEEE 1588 PTP for Grid Connected Par...idescitation
This paper introduces a distributed approach for
interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
methodology for achieving distributed interleaving is proposed,
along with a specific software based implementation approach
using the PTPdv2. The effectiveness of such methods in terms
of EMI reduction is experimentally validated in grid connected
Paralleled Solar Power Inverters.
AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nanoscale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we proposed a novel 7-input minority gate in CNTFET technology that has only 9 CNTFETs. Minority function is utilized in the voting systems for decision making and also it is used in data mining. This proposed 7-input minority gate is utilized less fewer transistors than the conventional CMOS method which utilizes many transistors for implementing sum of products. By means of this proposed 7-input minority gate, a 4-input NAND gate can be implemented, which gets better the conventional design in terms of delay and energy efficiency and has much more deriving power at its output.
PARALLEL BIJECTIVE PROCESSING OF REGULAR NANO SYSTOLIC GRIDS VIA CARBON FIELD...ijcsit
New implementations for parallel processing applications using reversible systolic networks and the
corresponding nano and field-emission controlled-switching components is introduced. The extensions of
implementations to many-valued field-emission systolic networks using the introduced reversible systolic
architectures are also presented. The developed implementations are performed in the reversible domain to
perform the required parallel computing. The introduced systolic systems utilize recent findings in field
emission and nano applications to implement the function of the basic reversible systolic network using
nano controlled-switching. This includes many-valued systolic computing via carbon nanotubes and carbon
field-emission techniques. The presented realization of reversible circuits can be important for several
reasons including the reduction of power consumption, which is an important specification for the system
design in several future and emerging technologies, and also achieving high performance realizations. The
introduced implementations for non-classical systolic computation are new and interesting for the design
within modern technologies that require optimal design specifications of high speed, minimum power and
minimum size, which includes applications in adiabatic low-power signal processing.
Design and Fabrication of the Novel Miniaturized Microstrip Coupler 3dB Using...TELKOMNIKA JOURNAL
In this work, a novel miniaturized compact coupler using the shunt-stubs artificial transimission
lines with high and low impedances is presented. Design of the proposed coupler is accomplished by
modifying the length and impedance of the branch lines in the conventional structure with the planar
resonators in order to achieve branch line coupler with compact size and improvement of the
performances. First part of this work is focusing on the theorical study of the proposed resonators where
the equations are obtained. Secondly, the proposed coupler is designed on FR4 susbtrate, and simulated
by using the EM Solver (ADS from Agilent technologies and CST microwave studio) in order to operate in
the ISM band. The obtained results show good agreement with the simulations and the coupler shows a
good perfo6rmance in the hole bandwidth. The size of the proposed coupler is reduced around 50%
compared to the conventional design. The last part conerns the fabrication and test of the proposed
coupler. The measurement and simulation results are in good agreements.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
28 GHz balanced pHEMT VCO with low phase noise and high output power performa...IJECEIAES
This paper presents the study and design of a balanced voltage controlled oscillator VCO for 5G wireless communication systems. This circuit is designed in monolithic microwave integrated circuit (MMIC) technology using PH15 process from UMS foundry. The VCO ensures an adequate tuning range by a single-ended pHEMT varactors configuration. The simulation results show that this circuit delivers a sinusoidal signal of output power around 9 dBm with a second harmonic rejection between 25.87 and 33.83 dB, the oscillation frequency varies between 26.46 and 28.90 GHz, the phase noise is -113.155 and -133.167 dBc/Hz respectively at 1 MHz and 10 MHz offset and the Figure of Merit is -181.06 dBc/Hz. The power consumed by the VCO is 122 mW. The oscillator layout with bias and RF output pads occupies an area of 0.515 mm 2 .
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder
cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of
their unique characteristics will save energy consumption and decrease the chip area. In this paper we
presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).
Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer
technology in Different values of temperature and VDD.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
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Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
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Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
CW RADAR, FMCW RADAR, FMCW ALTIMETER, AND THEIR PARAMETERSveerababupersonal22
It consists of cw radar and fmcw radar ,range measurement,if amplifier and fmcw altimeterThe CW radar operates using continuous wave transmission, while the FMCW radar employs frequency-modulated continuous wave technology. Range measurement is a crucial aspect of radar systems, providing information about the distance to a target. The IF amplifier plays a key role in signal processing, amplifying intermediate frequency signals for further analysis. The FMCW altimeter utilizes frequency-modulated continuous wave technology to accurately measure altitude above a reference point.
CW RADAR, FMCW RADAR, FMCW ALTIMETER, AND THEIR PARAMETERS
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
DOI : 10.5121/vlsic.2012.3207 73
A LOW POWER HIGH BANDWIDTH FOUR
QUADRANT ANALOG MULTIPLIER IN 32 NM
CNFET TECHNOLOGY
Ishit Makwana1
and Vitrag Sheth2
1
Dept. of Electrical & Electronics Engg, Birla Institute of Technology & Science (BITS)
Pilani, Pilani, India
ishitmakwana@gmail.com
2
Hewlett Packard Global Soft India Pvt. Ltd., Bangalore, India
vitragksheth@gmail.com
ABSTRACT
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several
limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for
analog circuit applications has been explored. This paper proposes a novel four quadrant analog
multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the
proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large
bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
KEYWORDS
Carbon Nanotube FET, Nanoelectronics, Analog Integrated Circuits, Analog Multipliers, Low Power.
1. INTRODUCTION
As predicted by Moore’s law, CMOS manufacturing technology has continued to scale to ever-
smaller dimensions now reaching 32nm [1]. At these dimensions several issues arise, such as
source to drain tunneling, device mismatch, random dopant fluctuations, mobility degradation,
etc. that impact its cost, reliability and performance making further scaling almost impossible. To
maintain the trend of Moore’s Law and technology’s advances in nano-scale regime, novel
nanoelectronic solutions are needed to surmount the physical and economic barriers of current
technologies.
As one of the promising new transistors, carbon nanotube field-effect transistor (CNFET)
overcomes most of the fundamental limitations of traditional silicon MOSFET. The excellent
device performance of carbon nanotube (CNT) is attributed to its near-ballistic transport
capability under low voltage bias [2]. Intense research on carbon nanotube (CNT) technology has
been performed on digital circuit applications such as logic or memory, as well as radio-
frequency (RF) devices for analog applications. The potential for high intrinsic device speed [3]
and demonstration of CNFETs with a cut-off frequency fT as high as 80 GHz [4] have indicated
that CNT-based devices are well suited as building blocks of future analog and RF circuits.
CNFET structure is similar to a conventional MOSFET except that its semiconducting channel is
made up of carbon nanotubes (CNT) as shown in Figure 1. Since the electrons are only confined
to the narrow nanotube, the mobility goes up substantially on account of near-ballistic transport as
compared to the bulk MOSFET. The near-ballistic transport is due to a limited carrier-phonon
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
74
interaction because of larger mean free paths of acoustic phonons [5]. Additionally, CNFET
shows higher current density, and higher electron mobility of the order of 104
–105
cm2
/Vs [6]
compared with 103
cm2
/Vs for bulk silicon. The sizing of a CNFET is equivalent to adjusting the
number of tubes. Since the mobility of n-type and the mobility of p-type carriers inside CNTs are
identical, the minimum size is 1 for both P-CNFET and N-CNFET [7]. The device is turned on or
off by the applied gate voltage. Thus, CNFET is a high quality semiconducting material.
Figure 1. CNFET device structure with multiple nanotubes (CNFET_L3) and with a single tube
(CNFET_L2) as illustrated in [2].
The potential of CNFETs for analog circuit design is explored in recent works [7,8]. CNFET also
exhibits properties of higher current densities, higher transconductance, lower intrinsic
capacitances, as compared to CMOS, which makes CNFET attractive for linear analog circuit
applications. It has been demonstrated that CNFETs have the potential to provide higher linearity
as compared to silicon or III-V semiconductors [9]. Therefore, low power and high bandwidth
analog circuits can be designed based on CNFET.
The four quadrant analog multiplier circuit is a versatile building block used for numerous
communication signal processing applications. In contemporary VLSI chips, the analog CMOS
multipliers are widely applied in phase-lock loops, automatic variable gain amplifiers, mixers,
modulators, demodulators and many other non-linear operations - including division, square
rooting, frequency conversion, etc. In most of applications, the desired multiplier’s features are
good isolation between input-output ports (especially for RF systems), wide input dynamic range,
wide bandwidth, symmetric input/output delay, low power dissipation and low voltage supply
[10].
Following the early work of Gilbert [11], a variety of multipliers has been designed with different
optimization objectives [12-15]. Multipliers have been built around various topologies using
Bipolar, CMOS [12,13] and Bi-CMOS [14,15] based circuits. The general idea behind these
designs is to utilize electronic devices like BJT or MOS transistors to process the two input
signals, followed by a cancellation of errors caused by non-linearity of the devices. MOS
transistors are widely used for multiplication process, while differential circuit structure is
generally used for nonlinearity cancellation [10].
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
75
In this paper, we present a new analog multiplier based on 32nm CNFET technology with
emphasis on high linearity, low power consumption, and high bandwidth. We analyze the
performance of the multiplier and compare it with recent works.
2. ANALOG MULTIPLIER DESIGN
The design of the proposed multiplier is based on the quarter square algebraic identity [16], which
is a widely used method for multiplier implementation. In this technique, in the first step the sum
and difference of two input signals is performed. Next, the square of both the sum and difference
is performed. Finally, the difference between the two square signals is taken as the output. The
output signal can be expressed as,
2 2
1 2 1 2 1 2[( ) ( ) ] 4. .outV V V V V V V= + − − = (1)
The proposed multiplier circuit is shown in Figure 3. The multiplier consists of two stages, the
first stage is the adder-subtractor circuit and the second stage is the core multiplier circuit, the
output of which is taken differentially across two output terminals. The complete multiplier
circuit requires the input signal voltages V1 and V2 in both true form and inverted form, i.e. V1,
V2 and -V1,-V2.
2.1. Capacitive Divider based Adder-Subtractor Circuit
The input stage of the multiplier circuit consists of the adder circuit, which is realized by a
capacitive divider based voltage adder/scaling circuit, as shown in Figure 2. A capacitive divider
based circuit is chosen for addition of the two input signals, which reduces Total Harmonic
Distortion (THD) at the output, reduces power consumption, improves linearity and increases
input dynamic range of the multiplier [17]. According to the superposition theorem, the output
voltage Vo is the scaled sum of the input voltages V1 and V2. In the complete multiplier circuit
shown in Figure 3, the Vo of the adder circuit is connected directly to the gate of one of the
NCNFET devices. For example, the Vy voltage at the gate of M3 is equal to (V1+V2)/6. Similarly,
Vx voltage at the gate of M1 is equal to (V1-V2)/6.
Figure 2. Capacitive adder-subtractor circuit.
At 32nm node, the gate effective capacitance (Ceff) of CNFET is found to be approximately
200aF/FET [18]. Therefore, to minimize the loading effect of input stage on the gate of CNFET,
the value of C in capacitive adder is chosen to be 5fF, which is very large compared to Ceff of
CNFET. Here the matching of capacitance values is essential for obtaining distortion-free output.
The capacitive adders/dividers are preferred to resistive adder/dividers, as getting precise
capacitive ratios is easier in CMOS manufacturing process as compared to resistance ratios.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
76
Hence, the use of capacitive adder/divider circuit reduces mismatch effects and reduces harmonic
distortion.
2.2. The Multiplier Core
In this paper, the high performance Stanford standard model of CNFET have been used for
simulation and analyses of analog multiplier circuit [19] which accounts for the practical non-
idealities in CNFET. The model also predicts the dynamic and transient performance of CNFET
with more than 90% accuracy [20]. The initial design parameters of CNFET topology was set to
their most practical values and then optimized for the multiplier circuit.
Figure 3. Proposed multiplier circuit.
The relatively larger value of gm in CNFET as compared to CMOS, makes it useful for analog
applications such as amplification and modulation.
0'
( )g g
m g
abs V V
g C
L
µ−
= (2)
The limiting value of gm for a ballistic nanotube transistor has been shown to be 150µA/V [2]. It
is also found that there is a direct relationship between CNFET diameter, band-gap energy Eg and
threshold voltage Vth of intrinsic CNT channel. It is given by the following equations [2][20]:
0.84
g
CNT
eV
E
D
= (3)
0.577
2
g
th
CNT
E aV
V
e D
π
= = (4)
2 2
CNT
n nm m
D a
π
+ +
= (5)
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
77
The parameters, ‘a’ (~2.49 Å) is the carbon to carbon atomic distance, Vπ (~3.033 eV) is the
carbon p-p bond energy in the tight bonding model, ‘e’ is the unit electron charge and (n,m) is the
chirality. The diameter of tube DCNT is the main parameter that directly affects the
transconductance in a CNFET. The barrier height at the S/D contact (Ef0), chirality (n,m) and
oxide thickness affect the gain and noise performance of CNFET. The power consumption of the
amplifier increases due to smaller (Ef0) as CNT become more conducting, increasing the on-
current. Moreover, the bandwidth also improves with increase in diameter of CNT, which is due
to enhanced screening between adjacent channels [7].
The inputs to multiplier are Vx=(V1-V2)/6 and Vy=(V1+V2)/6. Here, the scaling factor of 1/6
ensures that Vgs at gate of CNFETs is always greater than the threshold voltage Vth of NCNFET
when input voltages are in the range ±400mV. The transistors M5 and M6 have twice the number
of CNT as compared to M1-M4 transistors since the current through M5 and M6 is twice that of
M1-M4. Moreover, the transistors M5 and M6 are biased in saturation region such that the DC
node voltage at output terminals Vo1 and Vo2 is 0V. Thus all transistors in the multiplier operate in
saturation region. The non-linearity effect in the output is cancelled by matching pairs M3-M4
and M1-M2 and taking differential output across the drain terminal of the two pairs. Thus, the
above configuration of the circuit helps achieve high linearity multiplication across wide input
voltage range.
3. SIMULATION RESULTS
The proposed multiplier circuit has been simulated with Synopsys HSPICE simulator using the
32nm CNFET SPICE model from Stanford University at a supply voltage of ±0.9V [19]. The
following CNFET technology parameters are used for each CNFET in the simulation of
multiplier:
Table 1. Technology Parameters of CNFET used in the proposed circuit
Parameter Value
Physical length of channel 32.0 nm
Length of doped CNT source/drain extensions 32.0 nm
Fermi level of doped source/drain CNT regions 0.6 eV
Work function of source/drain metal contact 4.6 eV
CNT Work function 4.5 eV
Mean free path in Intrinsic CNT 200.0 nm
Mean free path in p+/n+ doped CNT 15.0 nm
Chirality of the tube (25,0)
Sub-lithographic Pitch 6.4 nm
Pitch (distance between two nanotubes) 20.0 nm
Dielectric constant of high-K gate oxide 16.0
Thickness of high-K gate oxide 4.0nm
The sizing of transistors is performed according to the magnitude of DC currents as mentioned
above. The number of tubes for M1-M4 is 1 and number of tubes for M5-M6 is 2. The major
parameter which affects the performance of multiplier is diameter of CNT (DCNT). It is observed
that with increase in DCNT the bandwidth, linearity range and power consumption of the multiplier
increases. The optimum diameter is found to be 1.98 nm, corresponding to a chirality of (25,0),
for achieving high linearity and wide input range, while the power consumption of the multiplier
is kept low by keeping minimum number of tubes per device.
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The performance of the multiplier is evaluated on the parameters of linearity, input range, power
consumption, frequency range and noise. Depending upon applications, some of them can be
more important than others. There is a trade-off between certain parameters. For instance, as the
power consumption of multiplier is decreased, the linearity range and bandwidth also decreases.
Hence, a reasonable trade-off is required to achieve low power consumption and good linearity.
3.1. DC Transfer Characteristics
The DC transfer characteristics of the circuit with V1 and V2 as the two inputs are shown in
Figure 4. The Vout = Vo2-Vo1 swings between -4.5mV to +4.5mV for the input range of +0.4V. In
the simulation, ‘in1’ is the variable for input V1 depicted on X-axis, and V2 is varied from -0.4V
to 0.4V with 50mV step size. The circuit is symmetric with respect to both input, therefore the
DC characteristics remain same. At the operating point, the DC node voltage at Vo1 and Vo2 is
nearly 0V (~0.677mV). The quiescent power consumption of the overall circuit is only 246.9µW.
Figure 4. DC Transfer Characteristics of multiplier
3.2. Harmonic Distortion Analysis
The harmonic distortion analysis is performed in frequency doubler configuration of the
multiplier. In this configuration, a 0.4V amplitude sinusoidal signal of 1MHz frequency is given
as input to both V1 and V2. Figure 5 depicts the transient response of the multiplier. The output
signal is sinusoid with fundamental frequency 2MHz. Figure 6 shows the simulated output
spectrum of the output signal obtained by Fourier analysis of the transient response in frequency
doubler configuration. The output component at 2MHz is having the highest magnitude as
expected. It is observed that the harmonic frequency components are at least 3 orders of
magnitude less than the fundamental. Figure 7 shows the variation of Total Harmonic Distortion
(THD) in percentage of the output waveform with different V1 and V2 values. Here both V1 and
V2 have same input frequency of 1MHz. It is found that the multiplier exhibits very low THD
(<0.45%) for a wide input range of ±400mV.
3.2. Frequency Response
Figure 8 shows the frequency response of the proposed multiplier in frequency doubler
configuration. The simulation is done with a sine wave of 0.2V peak value given as input to both
V1 and V2. The -3dB bandwidth is approximately 49.88GHz. The large bandwidth of the
multiplier is mainly due to the fact that the intrinsic capacitance of CNFET is much less as
compared to MOSFET [18]. Moreover, the gain of the circuit is much lesser than unity, while the
structure of the multiplier is similar to a common source amplifier. The bandwidth of the
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proposed multiplier is close to the cut-off frequency fT (~80GHz) of the single-walled carbon
nanotube common source amplifier as reported in [9].
Figure 5. Transient response of the multiplier in frequency doubler configuration with 400mV
1MHz AC input.
Figure 6. Simulated output spectrum of the multiplier in frequency doubler configuration for
0.4V 1MHz AC input signal.
Figure 7. Variation of output THD (%) with different V1 and V2 input voltages.
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.
Figure 8. Frequency Response: output magnitude plot for 0.2V AC signal input.
3.4. Noise Analysis
The equivalent input noise and the equivalent output noise are plotted in Figure 9 and Figure 10
with input frequency varying from 100 KHz to 1 THz. The simulation is done with the input sine
wave value of 0.4V peak in the frequency doubler configuration of the multiplier. The Y-axis
is in Volts/√Hz. It is apparent that significant noise suppression is achieved, which can be
attributed to the less count of devices used in the circuit.
Figure 9. Equivalent Input Noise Plot (in V/√Hz) for input 0.4V AC signal.
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Figure 10. Equivalent Output Noise Plot (in V/√Hz) for input 0.4V AC signal.
3.5. Amplitude Modulation
An application of analog multiplier is amplitude modulation. Figure 11 shows the modulation
performance of proposed circuit with sinusoidal inputs, V1 is 200mV at 10MHz and V2 is 50mV
at 100 MHz. The modulation performance is also simulated at a high frequency of 10 GHz as
shown in Figure 12.
Figure 11. Amplitude Modulation output for inputs 200mV 10MHz carrier and 50mV 1MHz
modulating signal.
Figure 12. Amplitude Modulation output for inputs 200mV 10GHz carrier and 50mV 1GHz
modulating signal.
3.6. Comparison with earlier works
The Table 2 summarizes a comparison of the proposed CNFET based multiplier circuit with
similar prior work on four quadrant multipliers in CMOS technology. It is observed that the
proposed multiplier is better than other CMOS based structures in terms of power consumption,
input range, linearity, bandwidth and transistor count.
4. CONCLUSIONS
A novel fully differential four quadrant analog multiplier using carbon nanotube FETs is
proposed. The proposed multiplier is a two stage structure based on quarter square technique of
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multiplication. The circuit is designed for low power and high bandwidth operation. A detailed
analysis of the circuit behaviour has been performed. High linearity and good noise performance
has been achieved by well designed structure of multiplier and fine-tuned parameters of CNFET.
The performance of the proposed multiplier is also compared with similar works on four-quadrant
multipliers in CMOS technology.
Table 2. Comparison of the proposed multiplier with previous works
Factor This work Ref [21] Ref [22] Ref [23] Ref [24] Ref [25]
Technology Node CNFET
32nm
CMOS
0.18µm
CMOS
0.5µm
CMOS
0.8µm
CMOS
0.35µm
CMOS
0.35µm
Supply Voltage ±0.9V ±1V ±2.5V +1.2V +1.8V +1.5V
Input Range ±400mV ±100mV ±1V ±250mV ±400mV ±400mV
THD % at 1MHz <0.45 <1.0 <0.85 <1.1 <1.0 at
25KHz
<1.0
Power 246.9 µW 588µW 3.6mW 2.76mW 200µW 46.4 µW
-3dB Bandwidth 49.88GHz 3.96GHz 120MHz 2.2MHz 10MHz 95MHz
Transistor Count 6 36 27 12 10 10
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Authors
Ishit Makwana received the B.Tech. Degree in Electronics & Communication
from Institute of Technology, Nirma University, Ahmedabad. He is currently
working toward the Master of Engineering Degree in Microelectronics, at
Birla Institute of Technology & Science (BITS) Pilani, Rajasthan. His research
interests include design and analysis of nanoscale devices and circuits.
Vitrag Sheth received the B.Tech. Degree in Electronics & Communication
from Institute of Technology, Nirma University, Ahmedabad. He is currently
with Hewlett Packard Global Soft Pvt. Ltd., Bangalore. His research interests
include analog and digital VLSI design.