In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of vco using current mode logic with low supply sensitivityeSAT Journals
Abstract The function of an oscillator is to convert dc energy into RF. Voltage Controlled Oscillator (VCO) is a type of oscillator whose output frequency can be varied by a control voltage. Here the VCO is designed using 0.18μm CMOS-RF technology using current mode logic. The Current mode logic is the fastest logic and is mainly used in Clock and Data Recovery applications. Current mode logic (CML) is a differential logic and provides noise immunity. Using the proposed design the current mode logic VCO operates with a supply voltage of 1.8 V and frequency varies from 2 MHz to 2.5 MHz. Its normalized supply sensitivity is 0.976 and optimum sensitivity is 0.966. Keywords: VCO, Supply sensitivity, CML, Ring oscillator.
A low power wideband varactorless VCO using tunable active inductorTELKOMNIKA JOURNAL
This paper presents a wideband varactorless voltage controlled oscillator (VCO) based on tunable active inductor in 90 nm CMOS process which yields a tuning range of 1.22 GHz to 3.7 GHz having a tuning scope of 100.5%. The designed VCO can be used for wideband wireless applications. The proposed VCO consumes a very low power (1.05~2.5) mW with the change of tuning voltages (0.3~0.9) V and provides a differential output power of (1.17~-5.13) dBm. The VCO exhibits phase noise of -80.50 dBc/Hz @ 2.74 GHz and the Figure of merit (FOM) is -147.73 dBc/Hz @ 2.74 GHz at 1MHz offset frequency. Achievement of high tuning range by altering the inductance of inductor which paves the way for eliminating the MOS varactor that recedes the overall silicon area consumption, is the noteworthy outcome of the proposed VCO. Furthermore, considering the dc power consumption, Figure of merit (FOM) and consistency of performance parameters over tuning range, the proposed VCO outstrips the other referred VCOs.
42 30 nA Comparative Study of Power Semiconductor Devices for Industrial PWM ...IAES-IJPEDS
The growing demand of energy translates into efficiency requirements of
energy conversion systems and electric drives. Both these systems are based
on Pulse Width Modulation (PWM) Inverter. In this paper we firstly present
the state of art of the main types of semiconductors devices for Industrial
PWM Inverter. In particular we examine the last generations of Silicon
Carbide (SiC) MOSFETs and Insulated Gate Bipolar Transistors (IGBTs)
and we present a comparison between these devices, obtained by SPICE
simulations, both for static characteristics at different temperatures and for
dynamic ones at different gate resistance, in order to identify the one which
makes the PWM inverter more efficient.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of vco using current mode logic with low supply sensitivityeSAT Journals
Abstract The function of an oscillator is to convert dc energy into RF. Voltage Controlled Oscillator (VCO) is a type of oscillator whose output frequency can be varied by a control voltage. Here the VCO is designed using 0.18μm CMOS-RF technology using current mode logic. The Current mode logic is the fastest logic and is mainly used in Clock and Data Recovery applications. Current mode logic (CML) is a differential logic and provides noise immunity. Using the proposed design the current mode logic VCO operates with a supply voltage of 1.8 V and frequency varies from 2 MHz to 2.5 MHz. Its normalized supply sensitivity is 0.976 and optimum sensitivity is 0.966. Keywords: VCO, Supply sensitivity, CML, Ring oscillator.
A low power wideband varactorless VCO using tunable active inductorTELKOMNIKA JOURNAL
This paper presents a wideband varactorless voltage controlled oscillator (VCO) based on tunable active inductor in 90 nm CMOS process which yields a tuning range of 1.22 GHz to 3.7 GHz having a tuning scope of 100.5%. The designed VCO can be used for wideband wireless applications. The proposed VCO consumes a very low power (1.05~2.5) mW with the change of tuning voltages (0.3~0.9) V and provides a differential output power of (1.17~-5.13) dBm. The VCO exhibits phase noise of -80.50 dBc/Hz @ 2.74 GHz and the Figure of merit (FOM) is -147.73 dBc/Hz @ 2.74 GHz at 1MHz offset frequency. Achievement of high tuning range by altering the inductance of inductor which paves the way for eliminating the MOS varactor that recedes the overall silicon area consumption, is the noteworthy outcome of the proposed VCO. Furthermore, considering the dc power consumption, Figure of merit (FOM) and consistency of performance parameters over tuning range, the proposed VCO outstrips the other referred VCOs.
42 30 nA Comparative Study of Power Semiconductor Devices for Industrial PWM ...IAES-IJPEDS
The growing demand of energy translates into efficiency requirements of
energy conversion systems and electric drives. Both these systems are based
on Pulse Width Modulation (PWM) Inverter. In this paper we firstly present
the state of art of the main types of semiconductors devices for Industrial
PWM Inverter. In particular we examine the last generations of Silicon
Carbide (SiC) MOSFETs and Insulated Gate Bipolar Transistors (IGBTs)
and we present a comparison between these devices, obtained by SPICE
simulations, both for static characteristics at different temperatures and for
dynamic ones at different gate resistance, in order to identify the one which
makes the PWM inverter more efficient.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low
temperature coefficient (TC) is presented in this paper. Large 1μF off-chip load capacitor is used to
achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower
frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode
amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in
bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC.
The characteristic is achieved by implementing MOSFET transistors operate in weak and strong
inversions. The LDO is designed using 0.18 μm CMOS technology and achieves a constant 1.8 V output
voltage for input voltages from 3.2 V to 5 V and load current up to a 128mA at temperature between -40 °C
to 125 °C. The proposed LDO is targeted for RF application which has stringent requirement on noise
rejection over a broad range of frequency.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Power quality improvement using impedance network based invertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
Abstract The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2 in 0.13μm CMOS ,which gives the best figure of merit and performance. Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A Study on Protection of Cables by Solkor Differential Protection Relay with ...IJERA Editor
This paper intends to briefly compare the protection of buried three phase high voltage cable with Solkordifferential protection relay using metallic pilot wires orfibre optic pilot wires. Dielectric property of the fiber optic provides complete electrical isolation as well as interference free signaling. This provides total immunity from GPR (ground potential rise), longitudinal induction, and differential mode noise coupling andhigh-voltage hazards to personnel safety. So Fibre optic provides great advantage for Solkor differential protection relaying.
Performance Analysis of Constant-K Low-Pass and Band-Pass Filters in a Uni-Po...paperpublications3
Abstract: Power system is designed to operate at a frequency of 50 or 60 Hz. However, certain types of non-linear loads produce current and voltages with frequency that are integer multiple of fundamental frequency. These frequency components known as harmonic pollution and is having adverse effect on the power system network. Harmonics generates serious problem to the quality of power supply of transmission and distribution network.. In today’s scenario, power system has not only to become reliable one, but also has to ensure about the quality of power. Due to few of the load side equipment only, the quality of power supply worsens. It affects not only the whole power system as well as many consumer side appliances and some sensitive equipment which cannot be afforded to be malfunctioned leading to even loss of life.
The output voltage waveform of ideal inverter should be sinusoidal. However, the waveforms of practical inverters are non sinusoidal and contain certain harmonics. For low and medium power applications, square-wave or quasi-square wave voltages may be acceptable; and for high-power applications, low distorted sinusoidal waveforms are required. With the availability of high-speed power semiconductor devices, the harmonic content of output voltage can be minimised or reduced significantly by switching techniques.
Keywords: SPWM inverter. low-pass, band-pass, carrier frequency, cut-off frequency, characteristic impedance, THD.
Title: Performance Analysis of Constant-K Low-Pass and Band-Pass Filters in a Uni-Polar SPWM Single Phase Inverter for Resistive Load
Author: Rashmi Vaishya, Ashish Choubey
ISSN 2349-7815
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
Paper Publications
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor ...journalBEEI
This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
A Low Phase Noise CMOS Quadrature Voltage Control Oscillator Using Clock Gate...IJERA Editor
This project presents the low phase noise cmos quadrature voltage control oscillator using clock gating technique. Here the colpitts vco is used to split the capacitance in the Qvco circuit producing quadrature output. The startup condition in the oscillator is improved by using 𝐺𝑚enhancement [12].This QVCO performs the operation anti phase injection locking fordevice reuse [8]. The new clock gating technique is used to reduce the power with thepower supply 1.5v. The QVCO uses a 0.5m𝐴with phase error of 0.4𝑜and exhibits a phase noise of -118dBc/HZ at 1MHZ offset at the centre frequency of 500MHZ.
A Low Phase Noise CMOS Quadrature Voltage Control Oscillator Using Clock Gate...IJERA Editor
This project presents the low phase noise cmos quadrature voltage control oscillator using clock gating technique. Here the colpitts vco is used to split the capacitance in the Qvco circuit producing quadrature output. The startup condition in the oscillator is improved by using 퐺푚enhancement [12].This QVCO performs the operation anti phase injection locking fordevice reuse [8]. The new clock gating technique is used to reduce the power with thepower supply 1.5v. The QVCO uses a 0.5m퐴with phase error of 0.4표and exhibits a phase noise of -118dBc/HZ at 1MHZ offset at the centre frequency of 500MHZ.
Index terms: current switching, clock gating, phase noise, Qvco
A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low
temperature coefficient (TC) is presented in this paper. Large 1μF off-chip load capacitor is used to
achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower
frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode
amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in
bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC.
The characteristic is achieved by implementing MOSFET transistors operate in weak and strong
inversions. The LDO is designed using 0.18 μm CMOS technology and achieves a constant 1.8 V output
voltage for input voltages from 3.2 V to 5 V and load current up to a 128mA at temperature between -40 °C
to 125 °C. The proposed LDO is targeted for RF application which has stringent requirement on noise
rejection over a broad range of frequency.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Power quality improvement using impedance network based invertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
Abstract The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2 in 0.13μm CMOS ,which gives the best figure of merit and performance. Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A Study on Protection of Cables by Solkor Differential Protection Relay with ...IJERA Editor
This paper intends to briefly compare the protection of buried three phase high voltage cable with Solkordifferential protection relay using metallic pilot wires orfibre optic pilot wires. Dielectric property of the fiber optic provides complete electrical isolation as well as interference free signaling. This provides total immunity from GPR (ground potential rise), longitudinal induction, and differential mode noise coupling andhigh-voltage hazards to personnel safety. So Fibre optic provides great advantage for Solkor differential protection relaying.
Performance Analysis of Constant-K Low-Pass and Band-Pass Filters in a Uni-Po...paperpublications3
Abstract: Power system is designed to operate at a frequency of 50 or 60 Hz. However, certain types of non-linear loads produce current and voltages with frequency that are integer multiple of fundamental frequency. These frequency components known as harmonic pollution and is having adverse effect on the power system network. Harmonics generates serious problem to the quality of power supply of transmission and distribution network.. In today’s scenario, power system has not only to become reliable one, but also has to ensure about the quality of power. Due to few of the load side equipment only, the quality of power supply worsens. It affects not only the whole power system as well as many consumer side appliances and some sensitive equipment which cannot be afforded to be malfunctioned leading to even loss of life.
The output voltage waveform of ideal inverter should be sinusoidal. However, the waveforms of practical inverters are non sinusoidal and contain certain harmonics. For low and medium power applications, square-wave or quasi-square wave voltages may be acceptable; and for high-power applications, low distorted sinusoidal waveforms are required. With the availability of high-speed power semiconductor devices, the harmonic content of output voltage can be minimised or reduced significantly by switching techniques.
Keywords: SPWM inverter. low-pass, band-pass, carrier frequency, cut-off frequency, characteristic impedance, THD.
Title: Performance Analysis of Constant-K Low-Pass and Band-Pass Filters in a Uni-Polar SPWM Single Phase Inverter for Resistive Load
Author: Rashmi Vaishya, Ashish Choubey
ISSN 2349-7815
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
Paper Publications
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor ...journalBEEI
This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
A Low Phase Noise CMOS Quadrature Voltage Control Oscillator Using Clock Gate...IJERA Editor
This project presents the low phase noise cmos quadrature voltage control oscillator using clock gating technique. Here the colpitts vco is used to split the capacitance in the Qvco circuit producing quadrature output. The startup condition in the oscillator is improved by using 𝐺𝑚enhancement [12].This QVCO performs the operation anti phase injection locking fordevice reuse [8]. The new clock gating technique is used to reduce the power with thepower supply 1.5v. The QVCO uses a 0.5m𝐴with phase error of 0.4𝑜and exhibits a phase noise of -118dBc/HZ at 1MHZ offset at the centre frequency of 500MHZ.
A Low Phase Noise CMOS Quadrature Voltage Control Oscillator Using Clock Gate...IJERA Editor
This project presents the low phase noise cmos quadrature voltage control oscillator using clock gating technique. Here the colpitts vco is used to split the capacitance in the Qvco circuit producing quadrature output. The startup condition in the oscillator is improved by using 퐺푚enhancement [12].This QVCO performs the operation anti phase injection locking fordevice reuse [8]. The new clock gating technique is used to reduce the power with thepower supply 1.5v. The QVCO uses a 0.5m퐴with phase error of 0.4표and exhibits a phase noise of -118dBc/HZ at 1MHZ offset at the centre frequency of 500MHZ.
Index terms: current switching, clock gating, phase noise, Qvco
Design and performance analysis of low phase noise LC-voltage controlled osci...TELKOMNIKA JOURNAL
Voltage controlled oscillator (VCO) offers the radio frequency (RF) system designer a freedom to select the required frequency. Today’s wireless communication system imposes a very stringent requirement in terms of phase noise generated in VCO. This study presents an inductive source degeneration technique to improve the phase noise performance of the inductance-capacitance (LC)-VCO. Double cross-coupled topology has been chosen for the proposed VCO. The post layout simulations with the parasitic resistance, inductance, capacitance (RLC) extracted view is carried out with united microelectronics corporations (UMC) 0.18 µm process by spectre simulator of cadence tools. The proposed VCO provides a phase noise
of -124.3 dBc/Hz @ 1 MHz. The tuning range obtained is 19.87% with a centre frequency of 2.46 GHz which makes it suitable for industrial, scientific, and medical (ISM) band applications. It consumes a power of 2.10 mW. Also, a good figure of merit of -189 is achieved. The total layout area occupied is 477×545 µm2.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
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In this paper, a low voltage differential CMOS trans-conductance amplifier using 180nm on cadence is presented. This design operates in sub threshold region of ±0.5V-1.5V and biasing stabilization has been checked by observing relationship between differential voltage and biasing variations on Nano-scale. Simulation results shows maximum differential output is obtained when biasing current reaches 500nA with CMRR 88db and static power consumption on normal input conditions is 241nW. In this paper, layout of OTA has been presented after verifying DRC and LVS by using assura tool of cadence suite.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
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interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
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using the PTPdv2. The effectiveness of such methods in terms
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The output voltage of a three level inverter is stepped voltage in which the output voltage have three possible values. Such systems can be used to interface renewable energy sources with the grid. Temperature has significant effect on performance of power MOSFETs. Typically, the MOSFETs used as power switches in such applications are a significant source of heat, and the heat energy dissipated by these components must be carefully controlled if operating temperatures are to be maintained. So for the system to work efficiently cooling of MOSFETs is required. This paper proposed an automated air cooled 3 level H-bridge inverter. The system consists of MOSFETs, LM 35 temperature sensor, Optocouplers for isolation. Arduino is used to control the on-off operation of fan. When temperature rises above certain level fan turns on to cool the MOSFETs.
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An Approach to Speech and Iris based Multimodal Biometric SystemIJEEE
Biometrics is the science and technology of human identification and verification through the use of feature set extracted from the biological data of the individual to be recognized. Unimodal and Multimodal systems are the two modal systems which have been developed so far. Unimodal biometric systems use a single biometric trait but they face limitations in the system performance due to the presence of noise in data, interclass variations and spoof attacks. These problems can be resolved by using multimodal biometrics which rely on more than one biometric information to produce better recognition results. This paper presents an overview of the multimodal biometrics, various fusion levels used in them and suggests the use of iris and speech using score level fusion for a multimodal biometric system.
An Overview of EDFA Gain Flattening by Using Hybrid AmplifierIJEEE
Data communication systems are increasingly engrossing optical fiber communication system as the transmission paths for the information, the information is in the form of light pulses sending from one place to another through the optical fiber. Several types of optical amplifiers have been developed in optical fiber communication system to amplify the optical signals. The erbium doped fiber amplifier is one of the optical fiber amplifiers which are used for long distance communication. The most significant points in any optical amplifier design are gain and noise figure. They are connected to one another. The other optical amplifier, Raman amplifier has wide gain bandwidth. The EDFA gain spectrum has variations over 1536 to 1552 nm, therefore the gain flattening is a research issue in recent years with the development of high capacity DWDM. The gain variation becomes a problem as the number of channels increases. The gain of EDFA depends on large number of device parameters such as, Erbium ion concentration, amplifier length, core radius, pump power. Raman amplifiers can be combined with EDFAs to expand the optical gain flattened bandwidth. This paper focuses on different methods used for the gain flattening.
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...IJEEE
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Design of Image Segmentation Algorithm for Autonomous Vehicle Navigationusing...IJEEE
In the past few years Autonomous vehicles have gained importance due to its widespread applications in the field of civilian and military applications. On-board camera on autonomous vehicles captures the images which need to be processed in real time using the image segmentation algorithm. On board processing of video(frames)in real time is a big challenging task as it involves extracting the information and performing the required operations for navigation.This paper proposes an approach for vision based autonomous vehicle navigation in indoor environment using the designed image segmentation algorithm. The vision based navigation is applied to autonomous vehicle and it is implemented using the Raspberry Pi camera module on Raspberry Pi Model-B+ with the designed image segmentation algorithm. The image segmentation algorithm has been built using smoothing,thresholding, morpho- logical operations, and edge detection. The reference images of directions in the path are detected by the vehicle and accordingly it moves in right or left directions or stops at destination. The vehicle finds the path from source to destination using reference directions. It first captures the video,segments the video(frame by frame), finds the edges in the segmented frame and moves accordingly. The Raspberry Pi also transmits the capture video and segmented results using the Wi-Fi to the remote system for monitoring. The autonomous vehicle is also capable of finding obstacle in its path and the detection is done using the ultrasonic sensors.
Performance Analysis of GSM Network for Different Types of Antennas IJEEE
Today, in metro cities BTSs are increasing day by day and interference is also increasing. This paper shows the received power of the cell depends on a number of factors. Antenna gain and antenna type are one of the important parameters for this. This paper reveals the effect of signal received power by changing the antenna gain and antenna type.The antenna used is omnidirectional and switched beam and gain varies from 5 to 15 dB.The GSM network is simulated for 6 users in Qualnet software.
On the Performance Analysis of Composite Multipath/Shadowing (Weibull-Log Nor...IJEEE
Composite multipath/shadowing fading environments are frequently encountered in different mobile realistic scenarios. These channels are generally modeled differentComposite multipath/shadowing fading. In this paper wepresent the performance analysis of composite (Weibull-Lognormal shadowed) fading. We adopt efficient toolproposed by Holtzman to approximate composite (Weibull-Lognormal shadowed) fading. The performance measures offading communication systems such as Probability densityfunction (PDF) of Signal to Noise ratio (SNR), Amount offading (AF), Outage probability (Pout) and ChannelCapacity(C/B) will be calculated. Graphical results will bepresented for different signals and fading parameters. Thedifferent expressions that will be provided are of greatimportance in assessing the performance of communicationsystems in composite channels.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
Carbon Nanotubes Based Sensor for Detection of Traces of Gas Molecules- A ReviewIJEEE
In this review paper, we discuss various gas sensors based on technique and sensing materials used in there fabrication. Various sensors are designed making use of salient features of carbon nanotubes and its electrical, mechanical, and electromechanical properties. Effect of using nano-composites on sensitivity and selectivity of gas sensor have been studied.
Routing Protocols in Zigbee Based networks: A SurveyIJEEE
ZigBee is the new standard developed wireless personal area network (WPAN) based on IEEE 802.15.4 for low cost, low data rate and low power consumption wireless network. In present times, zigbee has become a hot topic for research and development all over the world. This paper briefly describes various ZigBee network topologies including star, cluster tree and mesh topology and further introduces different ZigBee routing protocols such as AODV, AODVjr, Hierarchical, Integrated and Enhanced hierarchical routing protocol (EHRP).
A Survey of Routing Protocols for Structural Health MonitoringIJEEE
Wireless sensor networks have emerged in recent years as a promising technology that can impact the field of structural monitoring and infrastructure asset management. Various routing protocols are used to define communication among sensor nodes of the wireless sensor network for purpose of disseminating information. These routing protocols can be designed to improve the network performance in terms of energy consumption, delay and security issues. This paper discusses the requirements of routing protocol for Structural health monitoring and presents summary of various routing protocols used for WSNs for Structural health monitoring.
Layout Design Analysis of SR Flip Flop using CMOS TechnologyIJEEE
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Codec Scheme for Power Optimization in VLSI InterconnectsIJEEE
This paper presents a codec scheme for optimizing power in VLSI Interconnects. It is based on the traditional bus encoding method which is considered to be one of the most effective ways of power and delay reduction. The work done aims at optimizing power by designing the scheme using Full-Custom design approach. The model has been designed and implemented using Cadence Virtuoso Analog Design Suite in 0.18µm CMOS technology. Power has been computed for different possible combinations of input data. Delay has been reckoned for the maximum power consuming input combination. Layout editor has been used to generate the physical description of the circuit. The 4 bit input data combination consuming maximum dynamic power of 6.44µW and propagation delay of 722.7ps is “1000” with previously transmitted 4 bit data being “0111”. A significant power reduction of 38.89% has been observed by designing the scheme using Full-Custom approach as compared to the conventional Semi-Custom approach of design.
Design of Planar Inverted F-Antenna for Multiband Applications IJEEE
Planar Inverted F- Antenna (PIFA) is widely used in handheld devices because of its various advantages like compact size, good bandwidth and moderate radiation patterns. In this paper, a design of Planar Inverted F- Antenna(PIFA) is proposed that resonates at the frequency of 2.5 GHz with a bandwidth of 300MHz. The relative permittivity of the substrate used is 2.2. The antenna is fed by coaxial feed. Also, gain, VSWR and radiation pattern of the antenna are studied.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
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1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 18
A LOW POWER, LOW PHASE NOISE CMOS
LC OSCILLATOR
1
Pankaj Aseri, 2
R.C Gurjar
1,2
Microelectronics and VLSI Design, E&I Department, Shri G. S. Institute of Technology and Science, Indore,
M.P, India
1
pankajaseri17@gmail.com,2
rgurjar@sgsits.ac.in
Abstract:- In this paper a Double Cross Coupled Inductor
capacitor based Voltage Control Oscillator (LC-VCO) is
designed. In the proposed circuit the phase noise, tuning
range with respect to control voltage, output power and the
power dissipation of the circuit is analysed. Phase noise of
approximate -96 dBc/Hz at frequency of 1MHz, frequency
tuning range of 4.8 to 8.3 GHz (corresponding to 53.0%
tuning range) obtained by varying the control voltage from 0
to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm
resistance terminal and the power consumption of Circuit is
3.8 mW. This VCO are designed for 5.5 GHz. The circuit is
designed on the UMC 180nm CMOS technology and all the
simulation results are obtained using cadence SPECTRE
Simulator.
Keywords:- Phase Noise, LC-Tank, CMOS, Voltage controlled
Oscillator (VCO), Low power.
I. INDTRODCTION
The typical performance parameters of a VCO are phase
noise, tuning range, output power and DC power
consumption [1]. The VCO is the most important building
block of RF IC design. It play a vital role in many
applications such as GSM, Bluetooth, WLAN, Wireless
Personal Area Network (WPAN) and Wireless Sensor
Network etc. [2]. The most difficult task is to design the
Voltage Control Oscillator in the Front end block of RF-IC
design. In the today’s world of perfection in technology
there is a need to design and develop the circuit with Low
power and Low noise at the Higher Frequency. Out of the
total power consumption of a system the oscillator power
consumption can be a significant portion. So over- all
power consumption can be reduced by minimizing the
power consumption of the VCO [2]. Some basic oscillator
circuits such as local oscillator are limited to the Mixer
circuits at receiver end. But, at the high frequency the
different topology of oscillators are used that are capable to
provide low phase noise and most important term smaller
power at high frequency range i.e. Radio frequency range.
For higher quality receivers, an L C oscillator topology is
chosen over a relaxation oscillator because the band pass
nature of the resonant tank in the L C oscillator provides
the lowest phase noise [3]. In this paper, LC Voltage
Controlled Oscillator is designed, the proposed circuit
shows frequency tuning range in Giga Hertz due to
variation in control voltage variation.
In the SECTION II and SECTION III of this paper
provides information about the LC-VCO circuit
description and theoretical analyses of proposed circuit.
SECTION IV and SECTION V shows the simulation
results and conclusion.
II. LC-VCO CIRCUIT DESCRIPTION
The schematic circuit of the double cross coupled
differential LC-VCO including the differential buffer at the
output side is shown in Fig.1. The proposed LC-VCO form
by the PMOS and NMOS, inductor, and capacitor. This
LC-VCO is having of Cross Coupled PMOS transistors
(M4, M5) and Cross Coupled NMOS transistors (M0, M3).
Here PMOS and NMOS pairs are in parallel and due to this
negative resistance is generated. M14 and M12 transistors
are used as an output buffer. For biasing proposed circuit a
current mirror technique is used. (M1, M2) transistors are
being used as a current mirror. The Oscillation frequency
can be obtain from M14 and M12 NMOS transistors. This
proposed circuit provides better Phase Noise performance
measure because of double switch Cross Coupled
structure.
Fig: 1. Cross Coupled double switch LC-VCO.
III.THEORITICAL ANALYSES OF PROPOSED
CIRCUIT
The proposed circuit shown in the fig.1 consists of
inductor and voltage controlled capacitor (capacitor design
through MOS transistor) these two passive element forms
or resonant tank circuit. In the proposed circuit MOS
transistors (M1, M2) and (M3, M4) are cross coupled
transistors, which forms negative resistance and this
negative resistance basically compensated the resonator
losses. Voltage across the tank circuit is given by:-
- ≈ A sin( ) (1)
Where = ωt, ω being the angular frequency of oscillation.
Equations for bias current ( ) in NMOS and PMOS pair is
as follows:-
2. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
19 NITTTR, Chandigarh EDIT-2015
+ = (2)
And also for PMOS pair
+ = (3)
If transconductance PMOS and NMOS are gmp and gmn
respectively, from the small signal behaviour and analyse
we can relate negative resistance Rnegative with the
transcondutances of NMOS and PMOS shown below:-
= − (4)
If gmp = gmn = gm. Then we have
> (5)
The transistors (M5, M6) are current mirror which provide
or maintain the tail current of VCO and provide current
mirror action. Transistor (M7, M8) act as common drain
output buffer and having large input impedance.
IV.SIMULATION RESULTS
In this section, we have shown all simulation results of
double cross coupled LC-VCO. This VCO is designed
using UMC 180nm CMOS technology and is simulated
with Cadence Spectre simulator. This work has used
estimated value of inductance as L= 2nH and a variable
MOS based capacitor. For all measurements, we have
chosen following parameters as Vdd (power supply) = 1.8V
and biasing current Ibias, M1 = 1mA. The DC power
consumption of about <= 3.8 mW is obtained. Fig. 2 shows
the Oscillation waveform of LC-VCO. This Oscillation is
produced by the tank circuit, i.e. inductor (L) and
Capacitor (Ceq) in parallel connection forms the parallel
RLC circuit.
Fig: 2 Oscillation Waveform of LC VCO
Fig: 3 Oscillation of frequency at two output nodes Vout+
and Vout- of LC-VCO.
Fig. 4 The Phase Noise performance of circuit.
Fig: 5 The Tuning range response of circuit.
Fig: 4 The Phase Noise performance of circuit.
Fig: 5 The Tuning range response of circuit i.e. graph
between Frequency v/s Vcn (Control Voltage).
By varying of Control Voltage from 0 Volts to 2 Volts, the
Oscillation frequency varies from 4.8 GHz to 8.3 GHz.
The percentage tuning is measured to be 53%.
3. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 20
TABLE.1 COMPARISON AND PERFORMANCE
SUMMARY OF LC-OSCILLATOR WITH EARLIER
WORKS
Parameters This
Work
[1] [4] [5]
Process (nm) 180 250 180 180
Oscillation
Frequency
(GHz)
5.5 5.5 4.2 4.25
Core Current
(mA)
1 0.83 6 4
Supply voltage
(V)
1.8 2.5 1 2
Power
Dissipation(m
W)
3.8 2.075 6.0 8.0
Tuning range
(%)
53 16.9 42 30
Phase Noise
(dBc/Hz)
-95.6
@1MH
z
-89.77
@1MH
z
-116
@1MH
z
-114
@1MH
z
V.CONCLUSION
This design shows improved performance of Double cross
coupled LC-VCO. The integrated CMOS LC-VCO uses
double cross coupled transistor, an inductor and a capacitor
(using MOS varactors). This CMOS LC-VCO is
implemented using UMC 180nm CMOS technology and is
simulated using Cadence SPECTRE simulator. This design
has measured phase noise performance of -95.6 dBc/Hz at
1MHz and -116.3 dBc/Hz at 3MHz. It consume 3.8mW
power at 1.8V DC voltage supply. The tuning range of this
circuit is from 4.3 GHz to 8.3 GHz for 0V to 2V control
Voltage respectively i.e. about 53% tuning range. This
design finds its application in RF field because of its low
power, low area and high speed. Comparison and
performance summary of this work and earlier Oscillator
work is shown in Table.1
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