This seminar presentation introduces a design for a ternary logic family that operates using a single supply voltage. It will cover the design and simulation of ternary logic gates like inverters, NAND gates, and NOR gates. Simulation results will be shown for the output waveforms, power dissipation, rise time and fall time. The objectives are to minimize power consumption and propagation delay by reducing the number of transistors used. In conclusion, implementing ternary logic with a single power supply can significantly reduce power dissipation and improve transition times compared to traditional designs.

1. WELCOME TO THE SEMINAR
ON:
“Design of CMOS Ternary Logic
Family Based On Single Supply
Voltage”
Presented by:
Shivaleela.G

2. Contents :
• INTRODUCTION
• DESIGN AND SIMULATION OF TERNARY LOGIC GATES.
• DESIGN OF TERNARY INVERTER.
 STI(Simple Ternary Inverter)
 NTI(Negative Ternary Inverter)
 PTI(Positive Ternary Inverter)
• DESIGN OF TERNARY NAND GATE.
• DESIGN OF TERNARY NOR GATE.
• DESIGN OF TAND & TOR GATES.
• RESULTS & DISCUSSIONS.
 simulation & verification of outputs.
 Power dissipation .
 Rise time & Fall time.
• CONCLUSION.
• REFERENCES.

3. 1.INTRODUCTION:
• CMOS logic is considered for implemention of
only binary logic. As the circuit complexity is
increasing, the interconnection in binary occupies
large area on VLSI chip & thus, degrading the
performance.
• MVL(Multi valued logic) is considerd as solution
to this issue.
• A Ternary logic or three-valued logic is considered
as best radix of several MVL systems.
• The proposed GATES are designed & simulated
with the help of Microwind EDA tool and layout
design using VLSI CMOS technology.

4. 2.DESIGN AND SIMULATION OF
TERNARY LOGIC GATES.
• In design of digital systems,the inverter, NOR
gate,& NAND gates are considered to be building
blocks.
• The main objective is to minimize the power
consumption & propagation delay time thereby
reducing the number of transistor.
• In the proposed designs,the smaller single supply
voltage & MOSFETs with smaller threshold
voltage are used.
• Three logic levels are represented by states 0,1,2
with potential(0v),(0.5v), & +Vcc(+1v)respectively.

5. 3.DESIGN OF
TERNARY INVERTER:
The ternary inverter is a
compliment function, which in
the binary notation is known as
an inverter or MVL-NOT function.
 depending on inversion logic,
ternary inverters are of 3 types.
a) STI(Simple Ternary Inverter),
b) NTI(Negative Ternary
Inverter) and
c) PTI(Positive Ternary Inverter).
 The set of ternary inverters and
logic gates like TNAND(Ternary
NAND) & TNOR(Ternary NOR) can
be used to realize the complix
ternary function.

6. DESIGN LAYOUT OF STANDARD TERNARY INVERTER
USING PMOS & NMOS TRANSISTOR
Fig 3: Layout of standard Ternary Inverter
(STI)

7. 4.DESIGN OF
TERNARY NAND
GATE :
 A TNAND function
gives the inversion of
minimum value of inputs
signal where input signal
belongs to 0,1&2 or -1, 0,
+1
 The NAND output can
be defined as,

8. 5.DESIGN OF TERNARY
NOR GATE:
 A TNOR output
function gives the
inversion of the
maximum value of the
input signal. Thus the
NOR output can be
defined as,
Fig.5. proposed NOR with standard
Ternary logic

9. 6.DESIGN OF TAND & TOR GATES :
 The basic elements of
ternary logic family are STI,
TNAND & TNOR. By using
these gates we can further
implement TNAND, TOR.
 AND is basically a MIN
function, and OR is a MAX
fuction, which are specified
in below equations.

10. 7.RESULTS & DISCUSSIONS :
A. Simulation & verification of outputs:

11. Continue:

12. Continue:

13. B. POWER DISSIPATION :
• The power dissipation ‘p’
depends on three main factors.
 capacitance ‘C’
 supply votage ‘VDD’
 Clock frequency ‘f’
where
C- o/p load capacitance(Farad)
VDD- Supply voltage(V)
F – clock frequency (HZ)
• power dissipation is given by,

14. C. RISE TIME & FALL TIME :
• The rise time & fall
time is mainly
contributing to the
propagation delay of
the logic gate.
• proposed designs are
simulated to obtain rise
time & fall time for
various switching
transistions.

15. 8.CONCLUSION :
 In the proposed designs, these output transmission
gates/pull up transistors are eliminated from inverters,
thereby reducing the component count.
 Use of single power supply to implement ternary logic
gates has lead to significant reduction in overall power
dissipation & improving the transition time
 considering the various advantages of the MVL, the
appropriate design of MVL logic gates is important so
that it will lead to the further development and its
application in this area.

16. REFERENCES :