The document discusses the CMOS inverter, including its basic structure and operation, transient response characteristics, voltage transfer curve, propagation delay, and design considerations for improving performance such as minimizing delay. It provides analysis of how varying factors like transistor widths, supply voltage, and load capacitance affect the inverter's switching threshold, rise/fall times, and propagation delay. The goal of the analysis is to determine the optimal transistor width ratios and device parameters needed to design a high-performance symmetric CMOS inverter with minimum total propagation delay.

1. Low Power VLSI Design The Inverter Dr Anu Mehra

2. The CMOS Inverter: A First Glance V in V out C L V DD

3. CMOS Inverter Polysilicon In Out GND PMOS 2  Metal 1 NMOS Contacts N Well V DD

4. Two Inverters Connect in Metal Share power and ground Abut cells

5. CMOS Inverter First-Order DC Analysis V OL = 0 V OH = V DD V M = f(R n , R p ) V DD V DD V in 5 V DD V in 5 0 V out V out R n R p

6. CMOS Inverter: Transient Response V out V out R n R p V DD V DD V in 5 V DD V in 5 0 (a) Low-to-high (b) High-to-low C L C L t pHL = f(R on .C L ) = 0.69 R on C L

7. Voltage Transfer Characteristic

8. PMOS Load Lines V DSp I Dp V GSp =-2.5 V GSp =-1 V DSp I Dn V in =0 V in =1.5 V out I Dn V in =0 V in =1.5 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp V out I Dn V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp

9. CMOS Inverter Load Characteristics

10. CMOS Inverter VTC

11. Switching Threshold as a function of Transistor Ratio 10 0 10 1 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) W p /W n

12. Determining V IH and V IL A simplified approach V OH V OL V in V out V M V IL V IH

13. Inverter Gain

14. Simulated VTC

15. Propagation Delay

16. CMOS Inverter Propagation Delay Approach 1 ∆ t=C L ∆V/I DS Iav is average charging current and ∆V is V DD /2 V DD V out V in = V DD C L I av t pHL = C L V swing /2 I av

17. CMOS Inverter Propagation Delay Approach 2

18. Transient Response t p = 0.69 C L (R eqn +R eqp )/2 t pLH t pHL

19. Delay as a function of V DD

20. The Transistor as a Switch

21. Design for Performance (minimum delay) Keep capacitances small –keep drain diffusion area small so less overlap Increase transistor sizes watch out for self-loading! Increase V DD – however increasing voltage beyond a level leads to reliability concern

22. To MAKE A SYMMETRIC INVERTER tpHL=tpLH Reqn= 13k Ω and Reqp= 31k Ω (for 0.25 µ m technology) R N = Reqn(L/W)n R P= Reqp(L/W)p tpLH=ln(2)R P C L tnHL=ln(2)R N C L

23. In order to make tpHL=tpLH

24. To minimize total delay Total delay =tpHL+tpLH Approximate load Capacitance C L = (Cdp1+Cdn1)+(Cgp2+Cgn2)+CW Let β =(W/L)p/(W/L)n Then Cdp1= βCdn1 and Cgp2= β Cgn2 Total delay=tp

25. tp=0.69((1+β)(Cdn1+Cgn2)+C W (Reqn+Reqp/β) tp=0.69((1+β)(Cdn1+Cgn2)+C W Reqn(1+r/β) To minimize delay

26. For 0.25 technology

27. NMOS/PMOS ratio tpLH tpHL tp  = W p /W n