This document describes the design of a CMOS inverter for low power and high speed using Mentor Graphics. It summarizes the following: 1) An inverter was designed using a 25nm technology in Mentor Graphics. Simulations were performed to analyze power dissipation, delay, rise/fall times at different voltages and temperatures. 2) Power dissipation decreased and rise/fall times improved as the supply voltage was reduced from 3V to 1.1V. Delay remained similar across voltage levels. 3) The layout of the inverter was also designed using layout design rules and layout versus schematic checks in Mentor Graphics.