Pass-transistor logic uses transistors as switches to pass logic levels between circuit nodes, rather than connecting directly to power supplies, reducing the number of active devices. It has advantages over standard NMOS gate logic like being minimum geometry and dissipating no standby power. However, voltage differences decrease between logic levels at each stage. General functional blocks can implement all 16 logic functions of two inputs using NMOS or CMOS pass transistors controlled by four input signals. NMOS blocks pull down to ground but only up to a threshold below power, while CMOS transmission gates can output strong ones and zeros. Precharge logic can reduce the size of CMOS blocks.

1. PASS-TRANSISTOR LOGIC
-Yalagoud Patil
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2. Outline
1. What and Why Pass transistors?
2. Designing Pass transistor logic
3. General Function Blocks
I. NMOS Function Blocks
II. CMOS Function Blocks
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3. What and Why Pass transistors?
• In electronics, pass transistor logic (PTL) describes several logic families used in
the design of IC’s. It reduces the count of transistors used to make different logic
gates, by eliminating redundant transistors.
• Transistors are used as switches to pass logic levels between nodes of a circuit,
instead of as switches connected directly to supply voltages (Under the control of
the FETs gate voltage). This reduces the number of active devices.
• Applications: Designing regular arrays, such as ROMs , PLAs and multiplexers.
• Contemplate: Depletion mode PT created by an ion implant step can be used to
remove control from a given FET by shorting its drain and source!.
• Disadvantage: that the difference of the voltage between high and low logic levels
decreases at each stage.
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4. • Two major advantages of PT over standard NMOS gate logic are:
1. They are not “ratiod” devices and can be minimum geometry.
2. They do not have a path from plus supply to ground, and do not
dissipate standby power.
• If the gate and drain of a pass transistor are both high, the source will rise
to the lower of the potentials VDD and VGS – VTH.
• If the gate and drain are both at VDD , the source can only rise to one
threshold voltage below the gate, as shown in Fig 1.
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5. • Consider the Fig 2.
• Three pass transistor driving an inverter.
• With gate and drain of the first pass transistor at 5V its source rises to 3.5V
and the device is at the onset of pinching off.
• With the gate bias of the second FET at 5V and its drain at 3.5V, its source
rises to the drain potential 3.5V, and the device passes the input voltage to
its output (Depletion mode devices are short circuited).
• Each additional input requires only a minimum-geometry FET and adds no
DC power dissipation to the circuit.
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6. • Disadvantages: Chare steering, For Fig 2. inputs A,B,C and D all at 5V.
The voltage presented to inverter input is only 3.5V. This must be sufficient
to drive the inverter output low.
• If a PT is driven by a voltage less than 5V, the source of that FET will be at
one threshold voltage less than corresponding gate voltage.
• Fig 3. shows a situation when input C is 3.5V, Which would be the case if it
were driven by a pass transistor. Even though input D is 5V, the voltage to
the inverter is only 2V. This is below inverter threshold voltage and is most
likely treated as logic 0.
• A sufficiently high inverter ratio will solve this problem, but at the expense
of a long pull-up.
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7. • Thumb Rule: In designing NMOS PT logic, one must never drive a PT
with the output of another PT!
• Another one: In designing PT logic, care must be taken to ensure the
existence of both charging and discharging paths to the inputs of all
inverters!
• Charge sharing is a serious problem which occurs when two or more
capacitors at different potentials are tied together. One must be aware of
sneak paths.
• Sneak path is created when two PT are both on at the same time and one is
connected to VDD while the other is connected to GND, as shown in Fig 4.
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8. • There is also a timing problem!
• One more rule : One must always provide both a charging and a
discharging path for all input variables!
• A PT chain driving a capacitive load is shown in Fig 5.
• PT can be approximated as a lumped RC equivalent circuit. Where C is
gate to channel capacitance plus any parasitic capacitance of the gate node.
R is the series resistance of the channel with the FET operating in the linear
region, plus any parasitic resistance between nodes .
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9. • The rise time is proportional to the total resistance Rt and the total
capacitance Ct, of the line, both of which double when the number of PT
doubles. Hence propagation time is proportional to the square of the
number of PT in the chain.
• A string (finite transmission) of N elements, a string of identical pass
transistor driving a matched load CL=Cg, exhibits a delay of approximately
tp = 0.7N(N+1) RCL/2
• More accurate estimate for the propagation delay times low to high tpLH,
and high to low tpHL are
tpLH = 0.63 N(N+1)RCL/2
and
tpHL = 0.79 N(N+1)RCL/2
• Periodic restoration of the full signal voltage swing will improve the speed
of the circuit.
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10. Designing PTL
• Good PT design can design often faster logic than conventional MOS
design, with very low power loss and much less chip area.
• A weak one can be defined as an output voltage that is above ViH but lower
than a strong one, and a weak zero as an output that is below ViL but higher
than a strong zero. Typical values are as given below for 5V logic.
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Signal Rannge,V
Strong one 4.5-5.0
Weak one 3.5-4.5
Weak zero 0.5-1.5
Strong zero 0.0-0.5

11. • An NMOS PT can pull down to the negative rail, but it can only pull up to a
threshold voltage below the positive rail, as shown in Fig 6.
• In contrast PMOS PT can pull up to the positive rail, but can only pull down to
a threshold voltage above the negative rail. It can output a strong ne, but only a
weak zero, as shown in Fig 7.
• CMOS Transmission Gates (TG) can be used whenever PMOS devices are
available. CMOS TGs are superior to NMOS PT in two significant ways:
i. Output both strong ones and zeros
ii. TG consists of two transistors in parallel and except near the positive and negative
rails, it has about half the resistance of a single pass transistor.
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12. • Two disadvantages to CMOS TG are:
i. They require more are than NMOS pass circuitry.
ii. Require complemented control signals.
• The circuit diagram ,stick diagram of a CMOS TG are as shown in Fig 8.
Note: With four or less pass gates, the transistor network dissipates negligible
switching power.
• Pass transistor implementation of 2-input NAND and NOR gates.
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13. General Functional Blocks
• The function block can be either NMOS or CMOS and if implemented the
details if its operation can be left unbounded until later.
• The general two variable function block that implement all 16 logic
function of two input variables A and B is controlled by inputs C0 through
C3,is as shown in Fig 9.
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14. NMOS Functional block
• Examination of two input NAND,NOR,AND,OR,XOR,XNOR pass
networks shows that they all are of the same topological structure, with
only the inputs, controls and outputs changing.
• These six function are special cases of the sixteen possible logic functions
realizable with a 2-input function block,or logic block as shown in Fig 10.
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15. • There are two possible realizations of a two input function block, one with
enhancement mode transistor and other with depletion mode transistor, as
shown in Fig 11.
• Problem: Timing (When variables are used as inputs PT chains as well as
control signals).
• Solution: By using only VDD and GND as inputs to the PT chains,but
this doubles the size of the gate.
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16. • Example: Design of an XOR gate with 0 and 1 inputs requires 4 controls
A,A’,B & B’.This requires a 4-to-1 MUX in either NAND or NOR form.
• Two realization of an XOR gate with fixed inputs are shown in Fig 12. and
are seen to require a 4X4 matrix of transistors.
NOR structure NAND structure
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17. CMOS Functional Blocks
• A complementary CMOS design would consist of 8 TG replacing the 8 PT
of the NMOS design. When the CMOS function block is laid out the TG
would be split. It has twice the size of NMOS function block.
• The CMOS function block can be reduced in size by using precharge logic.
It can be precharged either high or low.
• A precharged high mostly NMOS function block and a precharged low
mostly PMOS function block are shown in Fig 13.
Mostly NMOS Mostly PMOS
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