Download to read offline
VLSI_MOS.pptx
- 1. VLSI Design Dr. VijayRao Kumbhare Assistant Professor (ECE) K L University, Hyderabad Session Outcome: 1 Remember the IC era and Understand the MOS transistor analysis Session No. 03 22-12-2022 1 24-04-2023
- 2. Integrated Circuit • IC •Integrated circuit 2 24-04-2023 • ICs have three key advantages over digital circuits built from discrete components Small size ICs are much smaller. High speed Communication within a chip is faster. Low power consumption Logic operations within a chip take much less power
- 3. Device Physics Device Electronics Two-Transistor Circuits (Inverters) Combinational andSequential Circuits Regular Structures ROMs, RAMs, PLAs VLSI Sub-Systems, Adders, Multipliers System-Related Issues, Reliability, Manufacturability, Testability Increasing Complexity 3 24-04-2023
- 4. Introduction to VLSIDesign VLSI Design Analog MOS Mirror and Steering MOS Cascade and Cascode OPAMP Amplifier Feedback Digital Static Design Conventional Static CMOS Logic Ratioed Logic Transmission Gate Logic Pass Transistor Dynamic Design Domino logic np-CMOS 4 24-04-2023
- 5. 5 Design Abstraction Levels SystemRequirements Architecture Definition and Logic Design VLSI Design and Layout Design Verification Pass Mask Generation Silicon Processing To: Wafer Testing Packaging and Reliability Qualification Design Rule Checking and Circuit Simulation (SPICE) Technology, Design Rules, Device Models Fail 24-04-2023
- 6. Levels of Design •Specifications • IO, Goals and Objectives, Function, Costs • Architectural Description • VHDL, Verilog, Behavioral, Large Blocks • Logic Design • Gates plus Registers • Circuit Design • Transistors sized for power and speed • Discrete Logic, Technology Mapping • Layout • Size, Interconnect, Parasitic 6 24-04-2023
- 7.
- 8.
- 9.
- 10.
- 11. Fabrication • nMOS -Early process with which only nMOS transistors could be fabricated 11 24-04-2023 • pMOS - Similar to nMOS process, but only pMOS transistors could be fabricated • CMOS - Complementary Metal Oxide Semiconductor process with which both pMOS and nMOS could be fabricated on the same substrate
- 12. CMOS FABRICATION PROCESS •The CMOS fabrication process involves both pMOS and nMOS transistors 12 24-04-2023 • An inverter is taken as an example to explain the CMOS process • An inverter contains both pMOS and nMOS transistors
- 13. BASIC MOS TRANSISTORS (a)nMOS Enhancement mode transistor (b) nMOS depletion mode transistor FIGURE 1 MOS transistors (V0 = 0 V. Source gate and substrate to 0 V). 13 24-04-2023
- 14.
- 15. MOS Capacitor Vg <0 When a negative voltage is applied to the gate Accumulation
- 16. MOS Capacitor Vg >0 Depletion When a small positive voltage is applied to the gate Depletion
- 17. MOS Capacitor 0 >Vg > Vth Inversion When a positive voltage above threshold voltage is applied to the gate Channel
- 18. NMOS Transistor Vgs =0 NO Channel, Ids = 0 CUT-OFF
- 19.
- 20. NMOS Transistor • Theformation of channel does not guarantee a drain to source current Ids • Following the Ohm’s law, there has to be a potential difference between drain and source so that current flows • Therefore for Ids to flow, Vds > 0 Vgs >Vth
- 21. Shape of thechannel • If Vgs > Vth then channel is formed and symmetric • In this case there is no current flow because Vds = 0
- 22. Shape of thechannel Vgs > Vth CHANNEL SYMMETRIC
- 23. Shape of thechannel • If Vgs > Vth, then channel is formed and has a trapezoidal shape • In this case, Ids > 0 because Vds > 0 • Under these conditions NMOS is said to be in ohmic/linear region
- 24. Shape of thechannel Vgs > Vth, then channel is formed and has a Trapezoidal shape Transistor in Ohmic/Linear Region
- 25. Shape of thechannel • If Vgs > Vth, then channel is formed but it is pinched off at the drain • Under these conditions NMOS is said to be at the edge of saturation region
- 26. Shape of thechannel • If Vgs > Vth then channel is formed but it does not exist till the drain region • Under these conditions NMOS is said to be in the saturation region • Even without channel formed completely till the drain, the current flows from drain to source due to drift • In saturation region, Ids is independent of Vds
- 27. Shape of thechannel Vgs > Vth CHANNEL PINCHED OFF TRANSISTOR IN SATURATION REGION Vgs > Vth is usually written as Vds > Vgs - Vth
- 28. IV Characteristics The IVCharacteristics we derive now are from IDEAL Model Too many secondary effects are neglected in this model In Cut-off region Ids = 0 In Linear Region, Ids depends on How much charge is in the channel? How fast is the charge moving?
- 29. Channel Charge MOSstructure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel
- 30. Carrier Velocity • Chargeis carried by electron in NMOS • Carrier velocity v is proportional to lateral E-field between source and drain • • • Time for the carriers to cross the channel
- 31. NMOS Linear IV •NOW, we know • How much charge is in the channel (QChannel) • How much time each carrier takes to cross the channel
- 32. NMOS Saturation IV •When Vgd < Vth channel pinches off at the drain region • This condition is written as Vds > Vdsat = Vgs – Vth • Now the drain source voltage no longer causes increase in current
- 33. NMOS IV Characterisitcs 0 1 2 3 4 5 6 00.5 1 1.5 2 2.5 Ids = 0 Vgs < Vth Cutoff region Linear/ Resistive region Vgs > Vth Vds < Vdsat Saturation region Vgs > Vth Vds > Vdsat
- 34. Problems • For thecircuit shown, use the the NMOS equations to find Id and Vds • For the NMOS, VTH = 1.5V and β = 1 mA/V2
- 35. Problems • For thecircuit shown, use the the NMOS equations to find Id and Vds • For the NMOS, VTH = 1.5V and β = 1 mA/V2
- 36. Problems For the circuitshown, use the the NMOS equations to find Id and Vds For the NMOS, VTH = 1.5V and β = 0.5 mA/V2
- 37. Problems • For thecircuit shown, use the the NMOS equations to find Id and Vds • For the NMOS, VTH = 1V and β = 1 mA/V2
- 38. Problems For the circuitshown, use the the NMOS equations to find Id and Vds For the NMOS, VTH = 1.5V and β = 0.5 mA/V2
- 39. Problems • Design thecircuit at right (by choosing β for the NMOS and the value of RD) so that ID = 10 mA and VDS = 0.2 V. The NMOS has VT = 1 V. How much power is being dissipated in the resistor and the NMOS?
- 40. nMOS Inverter withresistive pull up • The sharpness of the transfer characteristic increases with increasing load • Logic 0 level for a high input decreases with increasing load NOTE: Look at the Ltspice simulation for more clarity
- 41. nMOS inverter withdiode load • The sharpness of the transfer characteristic increases with increasing W/L ratio of the load transistor • Logic 0 level for a high input decreases with increasing W/L ration NOTE: Look at the Ltspice simulation for more clarity
- 42. CMOS Inverter properties •Full rail to rail swing • Low output impedance • Extremely high input impedance • Large Fanout • No direct path from VDD to GND which leads to LOW POWER
- 43. CMOS inverter StaticBehaviour 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 VIn Vout NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off VM
- 44. Transient Behaviour Vin =0 Low to High Transition Propagation Delay α Rp Cout Vin = 1 HIGH to Low Transition Propagation Delay α Rn Cout
- 45. Transient Behaviour • Howcan we build a faster inverter? Keeping the Output capacitance small Decreasing ON resistance of the transistor ON resistance decreases with increasing W/L ratio of the transistor
- 46. Transient Behaviour • WhenBoth PMOS and NMOS are symmetric, VM = VDD/2 • Symmetrical when W/L of PMOS is roughly twice that of NMOS • This is because the mobility of electrons is roughly twice that of holes • The inverter can be skewed to be either high or low • Note: Look into the CMOS inverter characteristics file for better understanding
- 47. Delay Definitions t Vin input waveform Vout output waveform t Vin Vout 50% tpHL 50% tf tpLH 90% 10% tr tp= (tpHL + tpLH)/2 Propagation delay
- 48.
- 49.
- 50. CMOS Inverter StickDiagram
- 51. Scaling • Technology shrinksby 0.7 times every generation • With every generation we can integrate 2x more functionality • Cost of a function decreases by 2x • There is a need for better design
- 52. Supply Voltage Scaling •Continuing technology scaling forces the supply voltages to reduce at rates similar to device dimensions • For example 180 nm 1.8 V and for 90 nm 1.1 V • How does it affect CMOS inverter ? • Reducing VDD improves transition region gain • But gain degrades for very low supply voltages 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2
- 53. Lambda based designrules • Layouts allow translation of circuits into actual geometry on silicon • Layout act as interface between circuit designer and fabrication engineer • Design rules define ranges for features • Minimum space between two metals to avoid short circuit • Minimum overlap to ensure complete overlap
- 54. Design Rules • Designrules have two major approaches • Micron rules • Absolute dimensions are discussed • Lambda rules • Depend on a single parameter λ • λ is usually 0.5 times minimum drawn transistor length • Advantage of Lambda rules is design rules can be scaled based on λ • Widely accepted
- 55. Rules for metallayer • Metal layers should have a minimum width and spacing of 4λ
- 56. Rule for diffusionlayers • Diffusion layers should have a minimum width and spacing of 4λ
- 57. Rules for polysiliconlayer • Polysilicon to have a minimum width of 2λ • Minimum spacing between two polys must be 3λ
- 58. Rules for contacts •Contacts must be 2λ by 2λ and should be surrounded by 1λ on the layers above and below
- 59. Rule for spacingbetween contacts • Contacts must have a spacing of 3λ from each other
- 60. CKV 0 0.5 1 1.5 2 2.5 0 0.5 11.5 2 2.5 Vout (V) X 10-4 Vin = 1.0V Vin = 1.5V Vin = 2.0V Vin = 2.5V Vin = 0V Vin = 0.5V Vin = 1.0V Vin = 1.5V Vin = 0.5V Vin = 2.0V Vin = 2.5V Vin = 2V Vin = 1.5V Vin = 1V Vin = 0.5V Vin = 0V PMOS NMOS 0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V CMOS Inverter VTC
- 61. Noise Margin Noise Margindictates the amount of noise a gate can withstand before it does not recognise the input
- 62.
- 63. Latch Up inCMOS • Latchup refers to short circuit formed between power and ground rails in an IC leading to high current and damage to the IC • This is due to interaction between parasitic pnp and npn transistors. • These form a +ve feedback loop, short circuit the power rail and ground rail, which eventually causes excessive current, and can even permanently damage the device
- 64. Latch Up inCMOS • Q1 is double emitter pnp transistor whose base is formed by n well substrate of PMOS, two emitters are formed by source and drain terminal of PMOS and collector is formed by substrate(p type) of NMOS.
- 65. Latch Up inCMOS Q2 is double emitter npn transistor whose base is formed by p- substrate, two emitters are formed by source and drain terminal of NMOS and collector is formed by substrate(N Well) of PMOS
- 66. Latch Up inCMOS • Collector current of one transistor Q1 is fed as input base current to another transistor Q2 • Collector current of Q2, Ic2 = β2 * Ib2 • This collector current Ic2 is fed as input base current Ib1 to transistor Q1 • In this way both transistors feedback each other and the collector current of each goes on multiplying.
- 67. Latch Up inCMOS • If β1 *β2 >=1, both transistors will conduct a high saturation current • This current eventually becomes so large that it may damage the device.
Editor's Notes
- #21 or equivalently Vgs > Vgd
- #22 and Vgs = Vgd, In a MOS transistor, the channel shape is a function of two voltages: Vgs and Vgd
- #23 and Vgs = Vgd
- #24 Vgd In a MOS transistor, the channel shape is a function of two voltages: Vgs and Vgd
- #25 Vgd >
- #26 and Vgd = Vth In a MOS transistor, the channel shape is a function of two voltages: Vgs and Vgd
- #27 and Vgd < Vth,
- #28 and Vgd < Vth and Vgd < Vth