International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Boundary Scan Basics - x1149 de KeysightInterlatin
Descubre los principios básicos sobre qué es Boundary Scan en la prueba electrónica, por qué es necesaria y cómo puedes tenerla como parte de tus sistemas de prueba gracias al x1149 de Keysight Technologies.
Boundary scan has become an indispensable technology as engineers like you face increasing test challenges. Agilent is proud to introduce the new x1149 Boundary Scan Analyzer - bringing the best of our technology and vast test experience - to your workbench!
Introduction to Phased Array Using the OmniScan MX2 - Part FourOlympus IMS
Free webinar available: http://bit.ly/1ndAuAc
OmniScan MX2 product details: http://bit.ly/1e6mjY8
Part four of the series will cover inspection and analysis with an emphasis on flaw sizing and characterizations using the sector scan data view. The user will learn and see examples of how the tools in the OmniScan MX2 are used to measure and record data for a manual inspection. This will include pros and cons of sector scan and linear scan groups, focus and coverage strategies, and application examples while learning to navigate the OmniScan MX2 software. There will be a brief review of the previous Webinar that leads into the current topics. All basic concepts of parts 1-3 in preparing the OmniScan MX2 for a single group manual weld inspection will be covered.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
Solution: Stainless Steel Weld InspectionZetec Inc.
Various industries want to use phased array ultrasonic technology for the inspection of stainless steel and other austenitic welds but many challenges exist including sound propogation.
This presentation provides a recommended solution that addresses the challenges and delivers results.
Boundary Scan Basics - x1149 de KeysightInterlatin
Descubre los principios básicos sobre qué es Boundary Scan en la prueba electrónica, por qué es necesaria y cómo puedes tenerla como parte de tus sistemas de prueba gracias al x1149 de Keysight Technologies.
Boundary scan has become an indispensable technology as engineers like you face increasing test challenges. Agilent is proud to introduce the new x1149 Boundary Scan Analyzer - bringing the best of our technology and vast test experience - to your workbench!
Introduction to Phased Array Using the OmniScan MX2 - Part FourOlympus IMS
Free webinar available: http://bit.ly/1ndAuAc
OmniScan MX2 product details: http://bit.ly/1e6mjY8
Part four of the series will cover inspection and analysis with an emphasis on flaw sizing and characterizations using the sector scan data view. The user will learn and see examples of how the tools in the OmniScan MX2 are used to measure and record data for a manual inspection. This will include pros and cons of sector scan and linear scan groups, focus and coverage strategies, and application examples while learning to navigate the OmniScan MX2 software. There will be a brief review of the previous Webinar that leads into the current topics. All basic concepts of parts 1-3 in preparing the OmniScan MX2 for a single group manual weld inspection will be covered.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
Solution: Stainless Steel Weld InspectionZetec Inc.
Various industries want to use phased array ultrasonic technology for the inspection of stainless steel and other austenitic welds but many challenges exist including sound propogation.
This presentation provides a recommended solution that addresses the challenges and delivers results.
Muchos ingenieros de prueba electrónica están muy acostumbrados a trabajar con la interfaz de UNIX y se niegan a cambiar a Windows, basados en rumores y/o falta de información. En este entrenamiento, encontrarán lo fácil que es hacer la migración entre Unix y Windows y todas las ventajas que tiene utilizar Windows en los equipos ICT de Keysight Technologies
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
Scalable NDT Instruments for the Inspection of Variable Geometry ComponentsOlympus IMS
For the past several years, the aviation industry has seen above normal growth due, in part, to lower oil prices, saving major aircraft operators millions of dollars. As a result of this outstanding growth, production rates for new airplanes have increased and new aircraft programs are being launched. Consequently, aviation component manufacturers are facing new challenges including a rise in production rates, a high probability of detection (POD) due to the critical nature of the parts being manufactured, lack of skilled operators, and parts with increasingly complex geometry.
Ultrasonic phased array (PA) instruments have evolved, enabling an increase in inspection speeds and the implementation of advanced acquisition strategies. The introduction of scalable instruments and advanced acquisition strategies helps manufacturers address the inspection challenges they are facing. Scalability can now be used for nondestructive testing (NDT), enabling system integrators and manufacturers to improve the performance of their solutions by using multiple instruments in parallel. The evolution of electronic components enables advanced acquisition strategies, such as adaptive ultrasound, to be implemented. Adaptive ultrasound simplifies the inspection of complex components and improves the POD by using innovative signal-processing algorithms.
This paper presents an overview of scalable NDT instruments with the goal of helping NDT integrators and manufacturers to address the challenges they are facing in terms of system performance, production output, and quality control.
Básicos de Functional Test Systems - Testing Days TijuanaInterlatin
Conoce las características principales de los sistemas TS-5400 de Keysight Technologies y aprende a seleccionar la configuración de sistema adecuado a tu producto.
To determine the limitations of TOFD and assuming the outcome was to the client’s satisfaction: I would lead a team to carry out subsequent inspections in the field.
The following is a brief overview of another success story.
Presentation on Prospect of Non Destructive Testing and Condition Monitoring...Ferdous Kabir
Predictive Maintenance (PdM) , PdM techniques are designed to help to determine the condition of in-service equipment in order to predict when maintenance should be performed.
Executive our PDM program, we consider following Non Destructive Testing and Condition Monitoring technique:
Ultrasonic Thickness Gauging (w/wo coating)
Conventional Ultrasonic Testing
Phased Array Ultrasonic Testing
Time and Flight Diffraction(TOFD)
Radiography Testing
Video-Borescopic Inspection/Endoscopic Inspection
Eddy Current Testing
Magnetic Particle Testing
Dye Penetrate Testing
Hardness Testing
Pre and Post Weld Heat Treatment
Vacuum Test
Vibration Analysis (vibration/field balancing)
Thermography
Lube Oil Analysis (Viscosity ,Oxidation, Nitration, Sulfating, Incorrect lubricant, Wear additives, Soot, Glycol, Water, FAME)
PV (Pressure Vessel) 200 Series DescriptionOlympus IMS
For more on the PV200 Series: http://bit.ly/1vD0zTw
The PV Series is a solution package with different configurations to meet customer’s applications.
The PV Series solutions include:
Acquisition unit
Scanner
Applicable Accessories
Setup and Analysis Tools
View our presentation to learn how this package is easy to use and can be a great inspection tool for those in manufacturing and welding.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
Boiler tube welds require a rapid volumetric inspection method. Traditionally, radiography (RT) is used, but this technology has several drawbacks. RT is insensitive to mis-oriented planar defects, it does not provide immediate feedback to the welders, and is disruptive to other activities. Mostly, safety regulations are getting more and more severe worldwide drastically restricting the use of radiography.
Low Pressure Turbine Rotor Weld InspectionZetec Inc.
Low pressure Turbine Rotor is an important part of steam turbine, Fatigue cracking tends to occur on the surface of the weld. In order to ensure the safe operation of power equipment aLow pressure Turbine Rotor is an important part of steam turbine, Fatigue cracking tends to occur on the surface of the weld. In order to ensure the safe operation of power equipment and personnel safety, the importance of safety evaluation on in service high-speed rotating turbine rotors is increasingly prominent. nd personnel safety, the importance of safety evaluation on in service high-speed rotating turbine rotors is increasingly prominent.
Advanced Probes for Austenitic and CRA Weld Inspection WebinarOlympus IMS
Free webinar available: http://bit.ly/1qXeQYj
OmniScan MX2 product details: http://bit.ly/1e6mjY8
The OmniScan has established a track record for reliable and cost effective phased array inspections as an alternative to radiography for carbon steel piping and pressure vessel welds. That success is now driving the market for viable inspection solutions for austenitic welds such duplex, stainless steel 304\316\321, and inconel cladded dissimilar metal welds. Advanced probe strategies and more effective probe designs are pushing the limits of what service companies and manufacturers can qualify with regard to full volumetric weld inspection and in-service crack detection and sizing. This presentation will provide a general overview of probe technology used in austenitic weld inspection and how it is deployed in portable phased array systems including live demonstration of austenitic flaw sizing and detection.
Contact us: http://bit.ly/1rDmq94
Sign up for our Newsletter: http://bit.ly/1j5FOTy
Friction Stir Weld Inspection Application SolutionZetec Inc.
Friction Stir Weld (FSW) inspections can be challenging and time consuming. It typically requires 3 beam angles for flaws parallel to the weld center line (WCL). Standard solutions use multiple probes, and require each probe to be aligned and calibrated, which can be a long process. Some flaw types (transverse, skewed) are not reliably detected with standard probe design. Additionally, the surface condition and flashing can prevent adequate coverage of the weld area with a contact solution.
Zetec offers the optimal solution for this type of inspection challenge, delivering a reliable and efficient inspection solution
that includes rapid setup, quick calibration and fast inspection speed.
Introduction to Phased Array Using the OmniScan MX2 - Part OneOlympus IMS
Free webinar available: http://bit.ly/1b5imIS
OmniScan MX2 product details: http://bit.ly/1e6mjY8
This series of webinars is designed to take participants through the basics of preparing a single group Phased Array inspection using the OmniScan MX2. Part one of the series will cover the essential ingredients of phased array and basic theory. It is geared toward understanding the equipment basics used to generate phased array inspections and includes the introduction to the OmniScan MX2 software user interface. Instrument module configurations, probe and wedge information, and basic beam forming concepts for a single sector scan group typical of manual inspection are explained while learning how those parameters are entered and controlled in the OmniScan MX2 software.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
Many challenges exist with turbine blade inspections -- Cracks and crack initiation in the blade attachment serrations need to be reliably detected. Complex geometry of the component is a very challenging factor for inspection design. In-situ inspection without blade removal is required, thus limiting blade access. This application presentation highlights a recommended solution with techniques to overcome the challenges.
For more on the PV100 Series: http://bit.ly/1vD0zTw
The PV Series is a solution package with different configurations to meet customer’s applications
The PV Series solutions include:
Acquisition unit
Scanner
Applicable Accessories
Setup and Analysis Tools
View our presentation to learn how this package is easy to use and can be a great inspection tool for those in manufacturing and welding.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
The increasing needs in term of energy production lead to new rotor shafts designs with larger dimensions. A new generation of nuclear power plants is already being deployed worldwide with such heavy components. Their implementation requires new inspection tools in order to guarantee the public safety and to ensure the quality of these critical parts.
This presentation addresses the implementation and validation of new solutions for large mono-block rotor shaft forgings.
T04201162168Optimal Allocation of FACTS Device with Multiple Objectives Using...IJMER
In this paper Multi objective functions are simultaneously considered as the indexes of the system performance minimize total generation fuel cost and maximize system load-ability within system security margin. To find the optimal location and optimal value for Thyristor Controlled Series Compensator (TCSC) using optimization technique Genetic Algorithm (GA) to maximize system load-ability and minimize the system losses considering multi objectives optimization approach. A GA based Optimal Power Flow (OPF) is proposed to determine the type of FACTS (Flexible AC Transmission system) controllers, its optimal location and rating of the devices in power systems. The value of TCSC and line losses is applied as measure of power system performance. The type of FACTS controllers are used and modeled for steady-state studies: TCSC, minimize total generation fuel cost and maximize system load-ability within system security margin. Simulations will be carrying on IEEE30 bus power system for type of FACTS devices.
Muchos ingenieros de prueba electrónica están muy acostumbrados a trabajar con la interfaz de UNIX y se niegan a cambiar a Windows, basados en rumores y/o falta de información. En este entrenamiento, encontrarán lo fácil que es hacer la migración entre Unix y Windows y todas las ventajas que tiene utilizar Windows en los equipos ICT de Keysight Technologies
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
Scalable NDT Instruments for the Inspection of Variable Geometry ComponentsOlympus IMS
For the past several years, the aviation industry has seen above normal growth due, in part, to lower oil prices, saving major aircraft operators millions of dollars. As a result of this outstanding growth, production rates for new airplanes have increased and new aircraft programs are being launched. Consequently, aviation component manufacturers are facing new challenges including a rise in production rates, a high probability of detection (POD) due to the critical nature of the parts being manufactured, lack of skilled operators, and parts with increasingly complex geometry.
Ultrasonic phased array (PA) instruments have evolved, enabling an increase in inspection speeds and the implementation of advanced acquisition strategies. The introduction of scalable instruments and advanced acquisition strategies helps manufacturers address the inspection challenges they are facing. Scalability can now be used for nondestructive testing (NDT), enabling system integrators and manufacturers to improve the performance of their solutions by using multiple instruments in parallel. The evolution of electronic components enables advanced acquisition strategies, such as adaptive ultrasound, to be implemented. Adaptive ultrasound simplifies the inspection of complex components and improves the POD by using innovative signal-processing algorithms.
This paper presents an overview of scalable NDT instruments with the goal of helping NDT integrators and manufacturers to address the challenges they are facing in terms of system performance, production output, and quality control.
Básicos de Functional Test Systems - Testing Days TijuanaInterlatin
Conoce las características principales de los sistemas TS-5400 de Keysight Technologies y aprende a seleccionar la configuración de sistema adecuado a tu producto.
To determine the limitations of TOFD and assuming the outcome was to the client’s satisfaction: I would lead a team to carry out subsequent inspections in the field.
The following is a brief overview of another success story.
Presentation on Prospect of Non Destructive Testing and Condition Monitoring...Ferdous Kabir
Predictive Maintenance (PdM) , PdM techniques are designed to help to determine the condition of in-service equipment in order to predict when maintenance should be performed.
Executive our PDM program, we consider following Non Destructive Testing and Condition Monitoring technique:
Ultrasonic Thickness Gauging (w/wo coating)
Conventional Ultrasonic Testing
Phased Array Ultrasonic Testing
Time and Flight Diffraction(TOFD)
Radiography Testing
Video-Borescopic Inspection/Endoscopic Inspection
Eddy Current Testing
Magnetic Particle Testing
Dye Penetrate Testing
Hardness Testing
Pre and Post Weld Heat Treatment
Vacuum Test
Vibration Analysis (vibration/field balancing)
Thermography
Lube Oil Analysis (Viscosity ,Oxidation, Nitration, Sulfating, Incorrect lubricant, Wear additives, Soot, Glycol, Water, FAME)
PV (Pressure Vessel) 200 Series DescriptionOlympus IMS
For more on the PV200 Series: http://bit.ly/1vD0zTw
The PV Series is a solution package with different configurations to meet customer’s applications.
The PV Series solutions include:
Acquisition unit
Scanner
Applicable Accessories
Setup and Analysis Tools
View our presentation to learn how this package is easy to use and can be a great inspection tool for those in manufacturing and welding.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
Boiler tube welds require a rapid volumetric inspection method. Traditionally, radiography (RT) is used, but this technology has several drawbacks. RT is insensitive to mis-oriented planar defects, it does not provide immediate feedback to the welders, and is disruptive to other activities. Mostly, safety regulations are getting more and more severe worldwide drastically restricting the use of radiography.
Low Pressure Turbine Rotor Weld InspectionZetec Inc.
Low pressure Turbine Rotor is an important part of steam turbine, Fatigue cracking tends to occur on the surface of the weld. In order to ensure the safe operation of power equipment aLow pressure Turbine Rotor is an important part of steam turbine, Fatigue cracking tends to occur on the surface of the weld. In order to ensure the safe operation of power equipment and personnel safety, the importance of safety evaluation on in service high-speed rotating turbine rotors is increasingly prominent. nd personnel safety, the importance of safety evaluation on in service high-speed rotating turbine rotors is increasingly prominent.
Advanced Probes for Austenitic and CRA Weld Inspection WebinarOlympus IMS
Free webinar available: http://bit.ly/1qXeQYj
OmniScan MX2 product details: http://bit.ly/1e6mjY8
The OmniScan has established a track record for reliable and cost effective phased array inspections as an alternative to radiography for carbon steel piping and pressure vessel welds. That success is now driving the market for viable inspection solutions for austenitic welds such duplex, stainless steel 304\316\321, and inconel cladded dissimilar metal welds. Advanced probe strategies and more effective probe designs are pushing the limits of what service companies and manufacturers can qualify with regard to full volumetric weld inspection and in-service crack detection and sizing. This presentation will provide a general overview of probe technology used in austenitic weld inspection and how it is deployed in portable phased array systems including live demonstration of austenitic flaw sizing and detection.
Contact us: http://bit.ly/1rDmq94
Sign up for our Newsletter: http://bit.ly/1j5FOTy
Friction Stir Weld Inspection Application SolutionZetec Inc.
Friction Stir Weld (FSW) inspections can be challenging and time consuming. It typically requires 3 beam angles for flaws parallel to the weld center line (WCL). Standard solutions use multiple probes, and require each probe to be aligned and calibrated, which can be a long process. Some flaw types (transverse, skewed) are not reliably detected with standard probe design. Additionally, the surface condition and flashing can prevent adequate coverage of the weld area with a contact solution.
Zetec offers the optimal solution for this type of inspection challenge, delivering a reliable and efficient inspection solution
that includes rapid setup, quick calibration and fast inspection speed.
Introduction to Phased Array Using the OmniScan MX2 - Part OneOlympus IMS
Free webinar available: http://bit.ly/1b5imIS
OmniScan MX2 product details: http://bit.ly/1e6mjY8
This series of webinars is designed to take participants through the basics of preparing a single group Phased Array inspection using the OmniScan MX2. Part one of the series will cover the essential ingredients of phased array and basic theory. It is geared toward understanding the equipment basics used to generate phased array inspections and includes the introduction to the OmniScan MX2 software user interface. Instrument module configurations, probe and wedge information, and basic beam forming concepts for a single sector scan group typical of manual inspection are explained while learning how those parameters are entered and controlled in the OmniScan MX2 software.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
Many challenges exist with turbine blade inspections -- Cracks and crack initiation in the blade attachment serrations need to be reliably detected. Complex geometry of the component is a very challenging factor for inspection design. In-situ inspection without blade removal is required, thus limiting blade access. This application presentation highlights a recommended solution with techniques to overcome the challenges.
For more on the PV100 Series: http://bit.ly/1vD0zTw
The PV Series is a solution package with different configurations to meet customer’s applications
The PV Series solutions include:
Acquisition unit
Scanner
Applicable Accessories
Setup and Analysis Tools
View our presentation to learn how this package is easy to use and can be a great inspection tool for those in manufacturing and welding.
Contact us: http://bit.ly/1rDmq94
Sign up for our newsletter: http://bit.ly/1j5FOTy
The increasing needs in term of energy production lead to new rotor shafts designs with larger dimensions. A new generation of nuclear power plants is already being deployed worldwide with such heavy components. Their implementation requires new inspection tools in order to guarantee the public safety and to ensure the quality of these critical parts.
This presentation addresses the implementation and validation of new solutions for large mono-block rotor shaft forgings.
T04201162168Optimal Allocation of FACTS Device with Multiple Objectives Using...IJMER
In this paper Multi objective functions are simultaneously considered as the indexes of the system performance minimize total generation fuel cost and maximize system load-ability within system security margin. To find the optimal location and optimal value for Thyristor Controlled Series Compensator (TCSC) using optimization technique Genetic Algorithm (GA) to maximize system load-ability and minimize the system losses considering multi objectives optimization approach. A GA based Optimal Power Flow (OPF) is proposed to determine the type of FACTS (Flexible AC Transmission system) controllers, its optimal location and rating of the devices in power systems. The value of TCSC and line losses is applied as measure of power system performance. The type of FACTS controllers are used and modeled for steady-state studies: TCSC, minimize total generation fuel cost and maximize system load-ability within system security margin. Simulations will be carrying on IEEE30 bus power system for type of FACTS devices.
Conservation of Energy: a Case Study on Energy Conservation in Campus Lightin...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Effect Of Water On Slope Stability And Investigation Of ΝΝw Drainage Techniqu...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Greedy – based Heuristic for OSC problems in Wireless Sensor NetworksIJMER
This paper contains optimize set coverage problem in wireless sensor networks with adaptable sensing range. Communication and sensing consume energy, so efficient power management can extended the network lifetime. In this paper we consider a enormous number of sensors with adaptable sensing range that are randomly positioned to monitor a number of targets. Every single target may be redundantly covered by various sensors. For preserving energy resources we organize sensors in sets stimulated successively. In this paper we introduce the Optimize Set Coverage (OSC) problem that has in unbiased finding with an extreme number of set covers in which every sensor node to be activated is connected to the base station. A sensor can be participated in various sensor sets, but the overall energy consumed in all groups is forced by the primary energy reserves. We show that the OSC problem is NP-complete and we propose the solutions: an integer programming for OSC problem, a linear programming for OSC problem with greedy approach, and a distributed and localized heuristic. Simulation results are presented and validated to our approaches.
High Performance Germanium Double Gate N-MOSFETIJMER
The current MOSFET technology supports scaling down to nanometer. To achieve
enhanced transistor switching, it is difficult to keep the equivalent driver current at the same level
since it changes by the certain restrictions like effective masses, density of states, uniaxial- and
biaxial- strain; band structure, channel orientation, channel mobility, off-state leakage, switching
delay in nano-scale and parasitic latch up. Current strained-Si is the ruling technology for
intensifying the performance of MOSFET and development of strain can provide a better solution to
the scaling. The future of nano-scale MOSFETs relies on exploration of novel higher mobility channel
materials such as stained-Ge and strained III-V groups that might perform even better than very
highly strained-Si. In addition, parameters such as injection velocity, short channel length effect and
Band-to-Band Tunneling (BTBT) result in reduction of inversion charge, increase in leakage current,
resulting in decrease in the drive current. While developing accurate model of MOSFETs all these
complex effects should be captured. It is proposed to
1. Design high performance double gate n-MOSFET with channel material Ge.
2. Benchmarked & stimulate high performance double gate n-MOSFET by using the simulation
techniques.
Hybrid Photovoltaic and thermoelectric systems more effectively converts solar energy into electrical energy. Two sources of energy are used one of the energy is solar,that converts radiant light into electrical energy and heat energy which will convert heat into electricity.Photovoltaic cells and thermoelectric modules are used to capture and convert the energy into electricity.Furthermore solar-thermoelectric hybrid system is environmental friendly and has no harmful emissions.Solar-thermoelectric hybrid system increases the overall reliability without sacrificing the quality of power generated.In this paper an overview of the previous research and development of technological advancement in the solar-thermoelectric hybrid systems is presented.
Security of Data in Cloud Environment Using DPaaSIJMER
The rapid development of cloud computing is giving way to more cloud services, due to
which security of services of cloud especially data confidentiality protection, becomes more critical.
Cloud computing is an emerging computing style which provides dynamic services, scalable and payper-use.
Although cloud computing provides numerous advantages, a key challenge is how to ensure
and build confidence that the cloud can handle user data securely. This paper highlights some major
security issues that exist in current cloud computing environments. The status of the development of
cloud computing security, the data privacy analysis, security audit, information check and another
challenges that the cloud computing security faces have been explored. The recent researches on data
protection regarding security and privacy issues in cloud computing have partially addressed some
issues. The best option is to build data-protection solutions at the platform layer. The growing appeal
of data protection as a service is that it enables to access just the resources you need at minimal
upfront expense while providing the benefits of enterprise-class data protection capabilities. The
paper proposes a solution to make existing developed applications for simple cloud Systems
compatible with DPaaS. The various security challenges have been highlighted and the various
necessary metrics required for designing DPaaS have been investigated.
Enhancement in viscosity of diesel by adding vegetable oilIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
In the present paper , we introduce and study the concept of gr- Ti- space (for i =0,1,2) and
obtain the characterization of gr –regular space , gr- normal space by using the notion of gr-open
sets. Further, some of their properties and results are discussed.
Thermodynamic properties and modeling of sorption isotherms for longer storag...IJMER
Moisture equilibrium data of Urtica urens leaves by desorption and adsorption were
determined at 30, 40, and 50°C. The isotherms were determined by a static gravimetric method for
various temperature and humidity conditions. Five mathematical models were used to fit
the experimental data. A nonlinear least-squares regression program was used to evaluate the constants
of the five desorption and adsorption isotherm models GAB and Modified Halsey models were adequate
to describe the sorption characteristics of the samples. Isosteric heats of desorption and adsorption were
calculated by applying the Clausius-Clapeyron equation to the sorption isotherms at different
temperatures. It decreased with increasing moisture content. We recognized the linear relation exists
between the enthalpy and entropy of the sorption reaction
Delay measurement technique using signature register for small delay defect d...eSAT Journals
Abstract This paper proposes an method for testing a circuit in order to improve defect coverage of delays due to resistive open and close. The proposed method uses a signature analysis and a scan design to detect small delay defects. This measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design measures the small delay in short measurement time by delay measurement technique and extra latches for storing the test vectors. By evaluating with Rohm 0.18-μm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design and the area overhead is larger than that of the delay measurement architecture using standard scan design. Index Terms: Very Large Scale Integration (VLSI), Large Scale Integration (LSI), Design for Testability (DFT)
Implementation of delay measurement technique using signature register for sm...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOPVLSICS Design
The power consumption of IC during test mode is higher than its normal mode. This brings the power as one of the major design constraints for today’s low power design technologies. In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too. The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode. The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Mixed Scanning and DFT Techniques for Arithmetic CoreIJERA Editor
Elliptic curve Cryptosystem used in cryptography chips undergoes side channel threats, where the attackers deciphered the secret key from the scan path. The usage of extra electronic components in scan path architecture will protect the secret key from threats. This work presents a new scan based flip flop for secure cryptographic application. By adding more sensitive internal nets along with the scan enable the testing team can find out the bugs in chip after post-silicon and even after chip fabrication. Also present a new mixed technique by adding DFT(design for testing or Dfx unit) unit and scan unit in same chip unit without affecting the normal critical path ,i.e. without affecting speed of operation of chip, latency in normal mode. Both Scan unit and DFT unit are used for testing the sequential and combinational circuits present in 32 Bit Arithmetic core. Here a proposed PN code generation unit as scan in port to increase the code coverage and scan out port efficiency. The proposed system will written in verilog code and simulated using Xilinx Tool. The hardware module core is synthesized using Xilinx Vertex 5 Field Programmable Gated Array (FPGA) kit. The performance utilization is reported with the help of generated synthesis result
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware...奈良先端大 情報科学研究科
Outsourcing of IC fabrication components has initiated the
potential threat of design tempering using hardware Trojans and also has drawn the attention of government agencies and the semiconductor industry. The added functionality, known as hardware Trojan, poses major detection and isolation challenges. This paper presents a hardware Trojan detection technique that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified LOC test pattern application method is proposed so as to maximize dynamic power consumption of any target segment. The proposed architecture allows activating any target segment of scan chain and keeping others freeze which reduces total circuit switching activity. This helps magnify the Trojan’s contribution to selected segment by increasing dynamic power
consumption. Experimental results for ISCAS89 benchmark circuit demonstrate its effectiveness in side-channel analysis.
Data Volume Compression Using BIST to get Low-Power Pseudorandom Test Pattern...IJMTST Journal
This project describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)- based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to pattern-count ratios. Furthermore, this proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO based logic BIST (LBIST) infrastructure. The proposed architecture is extended in such that the patterns generated from PRPG is gone through CUT and then to TRA to perform ATE.
Design and implementation of modified clock generationeSAT Journals
Abstract
Performing delay test needs the automatic test equipment (ATE) which is used to provide the high-speed clocks, which is then used to generate at-speed test. ATE has some limitations such as it has limited number of clock pins, and is limited in supplying maximum clock frequencies. Expensive ATE has number of pins that works in high frequencies but that will be very expensive to go with to avoid that in this project at speed pulses is generated by a logic that is given to STUMP based LBIST
Keywords — ATE, LBIST
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Journals
Abstract Faults, caused by timing-related defects in very large scale integrated circuits, are important to detect to optimize coverage and test time. Delay faults are only due to timing malfunction. At-speed test is only method to detect these delay faults. This paper describes and compares different at-speed testing techniques on vivid point of views along with them practical implementation. This paper also shows results generated by automatic test pattern generation tool for these techniques. Next, generated test patterns are simulated by using simulator and correctness of these methods are verified. Keywords: LOC (Launch on capture), LOS (Launch on shift), LOES (Launch on extra shift), At-speed testing.
Design for Testability in Timely Testing of Vlsi CircuitsIJERA Editor
Even though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system.Two main issues related to test and security domain are scan-based attacks and misuse of JTAG interface. Design for testability presents effective and timely testing of VLSI circuits. The project is to test the circuits after design and then reduce the area, power, delay and security of misuse. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in self-test (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both. BIST is usually performed using pseudorandom pattern generators (PRPGs). Among the advantages of pseudorandom BIST are: (1) the low cost compared to testing from automatic test equipment (ATE). (2) The speed of the test, which is much faster than when it is applied from ATE. (3) The applicability of the test while the circuit is in the field, and (4) the potential for high quality of test.
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
Design and simulation of radio frequencyeSAT Journals
Abstract
Present day guided weapon systems, especially tactical class missiles use RF seeker, for target tracking towards terminal engagement. The seeker system including its antenna assembly will be onboard the missile. Due to the missile trajectory corrections, the seeker antenna pointing to the target may get disturbed resulting in track loss. To avoid this track loss, it becomes necessary to stabilize the antenna system in two planes. The fundamental role of stabilization loop in seeker application is to precisely follow the angular rate of the target. In order to achieve this requirement, it is essential to highly isolate the gimbaled antenna from the missile body motion due to the maneuvering of target or low frequency vibration during flight. However, the isolation ratio and stability margin of stabilization loop adopting the gimbaled platform with both low stiffness and heavy inertia are limited by mechanical characteristic such as low resonance frequency and its high magnitude. The selection of proper feedback sensors, modeling of the total system are key features of this project. In the end, the performance and the stability of designed stabilization loop are demonstrated using simulation in both frequency and time domain. The Hardware for the system is under realization by the Industry. The whole scheme is simulated in MATLAB off-line for this project.
Keywords: Missile, RF seeker, Track loss, Stabilization loop, Angular Rate Command, Bore-Sight Error, Maneuvering and Gimbaled Platform.
A Study on Translucent Concrete Product and Its Properties by Using Optical F...IJMER
- Translucent concrete is a concrete based material with light-transferring properties,
obtained due to embedded light optical elements like Optical fibers used in concrete. Light is conducted
through the concrete from one end to the other. This results into a certain light pattern on the other
surface, depending on the fiber structure. Optical fibers transmit light so effectively that there is
virtually no loss of light conducted through the fibers. This paper deals with the modeling of such
translucent or transparent concrete blocks and panel and their usage and also the advantages it brings
in the field. The main purpose is to use sunlight as a light source to reduce the power consumption of
illumination and to use the optical fiber to sense the stress of structures and also use this concrete as an
architectural purpose of the building
Developing Cost Effective Automation for Cotton Seed DelintingIJMER
A low cost automation system for removal of lint from cottonseed is to be designed and
developed. The setup consists of stainless steel drum with stirrer in which cottonseeds having lint is mixed
with concentrated sulphuric acid. So lint will get burn. This lint free cottonseed treated with lime water to
neutralize acidic nature. After water washing this cottonseeds are used for agriculter purpose
Study & Testing Of Bio-Composite Material Based On Munja FibreIJMER
The incorporation of natural fibres such as munja fiber composites has gained
increasing applications both in many areas of Engineering and Technology. The aim of this study is to
evaluate mechanical properties such as flexural and tensile properties of reinforced epoxy composites.
This is mainly due to their applicable benefits as they are light weight and offer low cost compared to
synthetic fibre composites. Munja fibres recently have been a substitute material in many weight-critical
applications in areas such as aerospace, automotive and other high demanding industrial sectors. In
this study, natural munja fibre composites and munja/fibreglass hybrid composites were fabricated by a
combination of hand lay-up and cold-press methods. A new variety in munja fibre is the present work
the main aim of the work is to extract the neat fibre and is characterized for its flexural characteristics.
The composites are fabricated by reinforcing untreated and treated fibre and are tested for their
mechanical, properties strictly as per ASTM procedures.
Hybrid Engine (Stirling Engine + IC Engine + Electric Motor)IJMER
Hybrid engine is a combination of Stirling engine, IC engine and Electric motor. All these 3 are
connected together to a single shaft. The power source of the Stirling engine will be a Solar Panel. The aim of
this is to run the automobile using a Hybrid engine
Fabrication & Characterization of Bio Composite Materials Based On Sunnhemp F...IJMER
The present day technology demands eco-friendly developments. In this era the
composite material are playing a vital roal in different field of Engineering .The composite materials
are using as a principle materials. Nowaday the composite materials are utilizing as a important
component of engineering field .Where as the importance of the applications of composites is well
known, but thrust on the use of natural fibres in it for reinforcement has been given priority for some
times. But changing from synthetic fibres to natural fibres provides only half green-composites. A
partial green composite will be achieved if the matrix component is also eco-friendly. Keeping this in
view, a detailed literature surveyed has been carried out through various issues of the Journals
related to this field. The material systems used are sunnhemp fibres. Some epoxy and hardener has
been also added for stability and drying of the bio-composites. Various graphs and bar-charts are
super-imposed on each other for comparison among themselves and Graphs is plotted on MAT LAB
and ORIGIN 6.0 software. To determining tensile strengths, Various properties for different biocomposites
have been compared among themselves. Comparison of the behaviour of bio-composites of
this work has been also compare with other works. The bio-composites developed in this work are
likely to get applications in fall ceilings, partitions, bio-degradable packagings, automotive interiors,
sports things (e.g. rackets, nets, etc.), toys etc.
Geochemistry and Genesis of Kammatturu Iron Ores of Devagiri Formation, Sandu...IJMER
The Greenstone belts of Karnataka are enriched in BIFs in Dharwar craton, where Iron
formations are confined to the basin shelf, clearly separated from the deeper-water iron formation that
accumulated at the basin margin and flanking the marine basin. Geochemical data procured in terms of
major, trace and REE are plotted in various diagrams to interpret the genesis of BIFs. Al2O3, Fe2O3 (T),
TiO2, CaO, and SiO2 abundances and ratios show a wide variation. Ni, Co, Zr, Sc, V, Rb, Sr, U, Th,
ΣREE, La, Ce and Eu anomalies and their binary relationships indicate that wherever the terrigenous
component has increased, the concentration of elements of felsic such as Zr and Hf has gone up. Elevated
concentrations of Ni, Co and Sc are contributed by chlorite and other components characteristic of basic
volcanic debris. The data suggest that these formations were generated by chemical and clastic
sedimentary processes on a shallow shelf. During transgression, chemical precipitation took place at the
sediment-water interface, whereas at the time of regression. Iron ore formed with sedimentary structures
and textures in Kammatturu area, in a setting where the water column was oxygenated.
Experimental Investigation on Characteristic Study of the Carbon Steel C45 in...IJMER
In this paper, the mechanical characteristics of C45 medium carbon steel are investigated
under various working conditions. The main characteristic to be studied on this paper is impact toughness
of the material with different configurations and the experiment were carried out on charpy impact testing
equipment. This study reveals the ability of the material to absorb energy up to failure for various
specimen configurations under different heat treated conditions and the corresponding results were
compared with the analysis outcome
Non linear analysis of Robot Gun Support Structure using Equivalent Dynamic A...IJMER
Robot guns are being increasingly employed in automotive manufacturing to replace
risky jobs and also to increase productivity. Using a single robot for a single operation proves to be
expensive. Hence for cost optimization, multiple guns are mounted on a single robot and multiple
operations are performed. Robot Gun structure is an efficient way in which multiple welds can be done
simultaneously. However mounting several weld guns on a single structure induces a variety of
dynamic loads, especially during movement of the robot arm as it maneuvers to reach the weld
locations. The primary idea employed in this paper, is to model those dynamic loads as equivalent G
force loads in FEA. This approach will be on the conservative side, and will be saving time and
subsequently cost efficient. The approach of the paper is towards creating a standard operating
procedure when it comes to analysis of such structures, with emphasis on deploying various technical
aspects of FEA such as Non Linear Geometry, Multipoint Constraint Contact Algorithm, Multizone
meshing .
Static Analysis of Go-Kart Chassis by Analytical and Solid Works SimulationIJMER
This paper aims to do modelling, simulation and performing the static analysis of a go
kart chassis consisting of Circular beams. Modelling, simulations and analysis are performed using 3-D
modelling software i.e. Solid Works and ANSYS according to the rulebook provided by Indian Society of
New Era Engineers (ISNEE) for National Go Kart Championship (NGKC-14).The maximum deflection is
determined by performing static analysis. Computed results are then compared to analytical calculation,
where it is found that the location of maximum deflection agrees well with theoretical approximation but
varies on magnitude aspect.
In récent year various vehicle introduced in market but due to limitation in
carbon émission and BS Séries limitd speed availability vehicle in the market and causing of
environnent pollution over few year There is need to decrease dependancy on fuel vehicle.
bicycle is to be modified for optional in the future To implement new technique using change in
pedal assembly and variable speed gearbox such as planetary gear optimise speed of vehicle
with variable speed ratio.To increase the efficiency of bicycle for confortable drive and to
reduce torque appli éd on bicycle. we introduced epicyclic gear box in which transmission done
throgh Chain Drive (i.e. Sprocket )to rear wheel with help of Epicyclical gear Box to give
number of différent Speed during driving.To reduce torque requirent in the cycle with change in
the pedal mechanism
Integration of Struts & Spring & Hibernate for Enterprise ApplicationsIJMER
The proposal of this paper is to present Spring Framework which is widely used in
developing enterprise applications. Considering the current state where applications are developed using
the EJB model, Spring Framework assert that ordinary java beans(POJO) can be utilize with minimal
modifications. This modular framework can be used to develop the application faster and can reduce
complexity. This paper will highlight the design overview of Spring Framework along with its features that
have made the framework useful. The integration of multiple frameworks for an E-commerce system has
also been addressed in this paper. This paper also proposes structure for a website based on integration of
Spring, Hibernate and Struts Framework.
Microcontroller Based Automatic Sprinkler Irrigation SystemIJMER
Microcontroller based Automatic Sprinkler System is a new concept of using
intelligence power of embedded technology in the sprinkler irrigation work. Designed system replaces
the conventional manual work involved in sprinkler irrigation to automatic process. Using this system a
farmer is protected against adverse inhuman weather conditions, tedious work of changing over of
sprinkler water pipe lines & risk of accident due to high pressure in the water pipe line. Overall
sprinkler irrigation work is transformed in to a comfortableautomatic work. This system provides
flexibility & accuracy in respect of time set for the operation of a sprinkler water pipe lines. In present
work the author has designed and developed an automatic sprinkler irrigation system which is
controlled and monitored by a microcontroller interfaced with solenoid valves.
On some locally closed sets and spaces in Ideal Topological SpacesIJMER
In this paper we introduce and characterize some new generalized locally closed sets
known as
δ
ˆ
s-locally closed sets and spaces are known as
δ
ˆ
s-normal space and
δ
ˆ
s-connected space and
discussed some of their properties
Intrusion Detection and Forensics based on decision tree and Association rule...IJMER
This paper present an approach based on the combination of, two techniques using
decision tree and Association rule mining for Probe attack detection. This approach proves to be
better than the traditional approach of generating rules for fuzzy expert system by clustering methods.
Association rule mining for selecting the best attributes together and decision tree for identifying the
best parameters together to create the rules for fuzzy expert system. After that rules for fuzzy expert
system are generated using association rule mining and decision trees. Decision trees is generated for
dataset and to find the basic parameters for creating the membership functions of fuzzy inference
system. Membership functions are generated for the probe attack. Based on these rules we have
created the fuzzy inference system that is used as an input to neuro-fuzzy system. Fuzzy inference
system is loaded to neuro-fuzzy toolbox as an input and the final ANFIS structure is generated for
outcome of neuro-fuzzy approach. The experiments and evaluations of the proposed method were
done with NSL-KDD intrusion detection dataset. As the experimental results, the proposed approach
based on the combination of, two techniques using decision tree and Association rule mining
efficiently detected probe attacks. Experimental results shows better results for detecting intrusions as
compared to others existing methods
Natural Language Ambiguity and its Effect on Machine LearningIJMER
"Natural language processing" here refers to the use and ability of systems to process
sentences in a natural language such as English, rather than in a specialized artificial computer
language such as C++. The systems of real interest here are digital computers of the type we think of as
personal computers and mainframes. Of course humans can process natural languages, but for us the
question is whether digital computers can or ever will process natural languages. We have tried to
explore in depth and break down the types of ambiguities persistent throughout the natural languages
and provide an answer to the question “How it affects the machine translation process and thereby
machine learning as whole?” .
Today in era of software industry there is no perfect software framework available for
analysis and software development. Currently there are enormous number of software development
process exists which can be implemented to stabilize the process of developing a software system. But no
perfect system is recognized till yet which can help software developers for opting of best software
development process. This paper present the framework of skillful system combined with Likert scale. With
the help of Likert scale we define a rule based model and delegate some mass score to every process and
develop one tool name as MuxSet which will help the software developers to select an appropriate
development process that may enhance the probability of system success.
Material Parameter and Effect of Thermal Load on Functionally Graded CylindersIJMER
The present study investigates the creep in a thick-walled composite cylinders made
up of aluminum/aluminum alloy matrix and reinforced with silicon carbide particles. The distribution
of SiCp is assumed to be either uniform or decreasing linearly from the inner to the outer radius of
the cylinder. The creep behavior of the cylinder has been described by threshold stress based creep
law with a stress exponent of 5. The composite cylinders are subjected to internal pressure which is
applied gradually and steady state condition of stress is assumed. The creep parameters required to
be used in creep law, are extracted by conducting regression analysis on the available experimental
results. The mathematical models have been developed to describe steady state creep in the composite
cylinder by using von-Mises criterion. Regression analysis is used to obtain the creep parameters
required in the study. The basic equilibrium equation of the cylinder and other constitutive equations
have been solved to obtain creep stresses in the cylinder. The effect of varying particle size, particle
content and temperature on the stresses in the composite cylinder has been analyzed. The study
revealed that the stress distributions in the cylinder do not vary significantly for various combinations
of particle size, particle content and operating temperature except for slight variation observed for
varying particle content. Functionally Graded Materials (FGMs) emerged and led to the development
of superior heat resistant materials.
Energy Audit is the systematic process for finding out the energy conservation
opportunities in industrial processes. The project carried out studies on various energy conservation
measures application in areas like lighting, motors, compressors, transformer, ventilation system etc.
In this investigation, studied the technical aspects of the various measures along with its cost benefit
analysis.
Investigation found that major areas of energy conservation are-
1. Energy efficient lighting schemes.
2. Use of electronic ballast instead of copper ballast.
3. Use of wind ventilators for ventilation.
4. Use of VFD for compressor.
5. Transparent roofing sheets to reduce energy consumption.
So Energy Audit is the only perfect & analyzed way of meeting the Industrial Energy Conservation.
An Implementation of I2C Slave Interface using Verilog HDLIJMER
The focus of this paper is on implementation of Inter Integrated Circuit (I2C) protocol
following slave module for no data loss. In this paper, the principle and the operation of I2C bus protocol
will be introduced. It follows the I2C specification to provide device addressing, read/write operation and
an acknowledgement. The programmable nature of device provide users with the flexibility of configuring
the I2C slave device to any legal slave address to avoid the slave address collision on an I2C bus with
multiple slave devices. This paper demonstrates how I2C Master controller transmits and receives data to
and from the Slave with proper synchronization.
The module is designed in Verilog and simulated in ModelSim. The design is also synthesized in Xilinx
XST 14.1. This module acts as a slave for the microprocessor which can be customized for no data loss.
Discrete Model of Two Predators competing for One PreyIJMER
This paper investigates the dynamical behavior of a discrete model of one prey two
predator systems. The equilibrium points and their stability are analyzed. Time series plots are obtained
for different sets of parameter values. Also bifurcation diagrams are plotted to show dynamical behavior
of the system in selected range of growth parameter
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Leading Change strategies and insights for effective change management pdf 1.pdf
Scan-Based Delay Measurement Technique Using Signature Registers
1. International Journal of Modern Engineering Research (IJMER)
www.ijmer.com
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3042-3048
ISSN: 2249-6645
Scan-Based Delay Measurement Technique Using
Signature Registers
Telukutla Sahithi1, Mr. V. T. Venkateswarlu2 M. Tech., [Ph.D.],
1
2
PG Student, Associate professor, Department of ECE, Vasireddy Venkatadri Institute of Technology, Nambur,
Guntur (Dt.), Andhra Pradesh, India
ABSTRACT: With the scaling of semiconductor process technology, performance of modern VLSI chips will
improve significantly. However, as the scaling increases, small-delay defects which are caused by resistiveshort, resistive-open, or resistive-via become serious problems. The proposed method uses a signature analysis
and a scan design to detect small delay defects. The proposed measurement technique measures the delay of the
explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design
realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement
technique and extra latches for storing the test vectors.
Index terms: Very large scale integration (VLSI), signature register, design for testability (DFT).
I.
INTRODUCTION
Semiconductor process technology has developed rapidly to improve the performance of modern VLSI
chips. As a continuous process scaling produces large-scale chips. With the rapid development of semiconductor
technology, delay testing has become a critical problem. The major types of delays are occurred because of
resistive-shorts, resistive-open and resistive-vias. These small delays can cause a fail of a system if they are
activated for a longer time. Furthermore their life time become very short. Therefore to overcome these
drawbacks some embedded delay measurement techniques have been proposed. Scan-based delay measurement
technique with variable clock generator is one of these on-chip delay measurement techniques. The delay of
path is measured by continuous sensitization of path under measurement with test clock width reduced
gradually. The advantage of this technique is its high accuracy. This technique has some drawbacks. Therefore
we present a scan-based delay measurement technique which uses signature registers.
A.EXISTING SYSTEM
These days, various methods for small-delay defect detection have been proposed. Scan-based delay
measurement technique with variable clock generator is most widely used. In this technique the delay of path is
measured by continuous sensitization of path under measurement with test clock width reduced gradually by
resolution. In this technique the accuracy is high. The reason of the high accuracy is that the technique measures
just the period between the time when a transition is launched to the measured path and the time when the
transition is captured by the flip flop connected to the path, directly. The variation of the measured value just
depends on the variation of the clock frequency of the clock generator. Therefore, if the clock generator is
compensated the influence of the process variation, the measured value does not depend on the process
variation.
B. DRAWBACKS OF EXISTING SYSTEM
Disadvantages of existing system are as follows.
The gap between the functional clock and scan clock frequency increases. Therefore the measurement time
becomes too long to make it practical.
Area reduction technique of the self testing scan-FFs is also proposed. The flip flop reduces the required
number of scan operations, which makes the measurement time practical.
However, the area overhead of these methods is still expensive compared with the conventional scan
designs.
C. PROPOSED SYSTEM
We present a scan-based delay measurement technique using signature registers for small-delay defect
detection. The proposed method does not require the expected test vector because the test responses are
analyzed by the signature registers. The overall area cost is of the order of conventional scan designs for design
for test (DFT). The measurement time of the proposed technique is smaller than conventional scan-based delay
measurement. The extra signature registers can be reused for testing, diagnosis, and silicon debugging.
D. ADVANTAGES OF PROPOSED SYSTEM
Proposed method does not require expected test vectors.
The measurement time is smaller.
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2. International Journal of Modern Engineering Research (IJMER)
www.ijmer.com
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3042-3048
ISSN: 2249-6645
The overall area cost is of the order of conventional scan designs for design for test (DFT).
E. VARIABLE CLOCK GENERATOR
In the proposed method, the clock width should be reduced continuously by a constant interval. It is
difficult for an external tester to control this clock operation. Therefore an on-chip variable clock generator is
used for the proposed method. In this paper, we use the on-chip variable clock generator. Figure1 illustrates the
circuit. The circuit consists of the arbitrary clock frequency generator and the 2-pulse generator. The arbitrary
clock frequency generator generates an arbitrary clock width. The 2-pulse generator generates 2-pulse test
clocks with arbitrary timing in response to a trigger signal.
Figure 1: variable clock frequency generator
II.DELAY MEASUREMENT TECHNIQUE USING SIGNATURE REGISTER
The proposed measurement is scan-based delay measurement. The difference from the existing one is
use of signature registers and additional latches. In this measurement latches are used to store test vector after
scan-in operation.
A.SCAN FLIP FLOPS
An important flip-flop function for ASIC testing is so-called scan capability. The idea is be able to
drive the flip-flop’s D input with an alternate source of data during device testing. When all of the flip-flops are
put into testing mode, a test pattern can be “scanned in” to the ASIC using the flip-flops’ alternate data inputs.
After the test pattern is loaded, the flip-flops are put back into “normal” mode, and all of the flip-flops are
clocked normally. After one or more clock ticks, the flip-flops are put back into test mode, and the test results
are “scanned out. Figure2 shows the gate level description of scan flip flop. The lines D, Q, and clk are the
input, output, and clock lines, respectively. When se0=0, the flip flop is in normal operation mode. When se0=1
and se1=1, the flip flop is in scan operation mode. When se0=1, se1=0, the flip flop loads the value stored in the
latch connected to the latch line. The lines si and s0 are the input and output for constructing the scan path.
Figure 2: scan flip flop
B.RECONFIGURABLE SIGNATURE REGISTER
Signature analysis registers are often used in combination with standard LFSRs for on-chip self test of
VLSI circuits. The signature register for the proposed measurement requires the following functions to meet the
demand of the proposed measurement.
• Capturing the test response in arbitrary timing.
• Shifting out the signature data in arbitrary timing.
Figure3 shows the architecture of the signature register for the proposed measurement. It has four flip
flops FF0, FF1, FF2, and FF3. . When sge = 1 , it works as a signature register. When sge=0, it works as a shift
register. The line in is the input of the signature register. The clock line is controlled by sck . When sck = 0 , the
signature register does not capture the input value. When sck = 1 , the signature register captures the input
value synchronizing with the positive edge of clk . By controlling sck, the signature registers capture only the
target test response. The output is sg0. The measurement system requires multiple signature registers generally.
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3. International Journal of Modern Engineering Research (IJMER)
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3042-3048
ISSN: 2249-6645
Figure3: 4- bit reconfigurable signature register
III.DELAY MEASUREMENT SYSTEM
Delay measurement system is shown figure 4. The proposed system consists of the low cost tester and
the chip with the variable clock generator (VCG) explained in and a BCD decoder. The chip is assumed to have
single functional clock in the proposed method, and the chip has two reset lines for initializing the flip flops and
the signature registers independently. The reset operations are controlled by the tester. The low cost tester
controls the whole measurement sequence. The clock frequency tck is slower than the functional clock. The line
sg0 retrieves the signature data from the signature registers to estimate the measured delay. The line sci sends
the test vectors to the scan input of the chip. The line sc0 gets the data of the flip flops from the scan output of
the chip. In the proposed measurement sequence, sc0 is not used. However, it is used to check the flip flops or
the additional latches before the measurement. The line cs is the clock control line. The proposed measurement
uses both the slow tester clock tck and the fast double pulse generated by on-chip VCG. The line selects the
slow and fast clock. If cs is 1, the fast clock is sent to the clock line clk of the components. Otherwise the slow
tester clock tck is sent. The lines trg and cnt are the input lines for VCG. The fast double pulse is launched
synchronizing with the positive edge of trg . The line cnt controls the width of the double pulse. The line se
controls the scan flip flops. The line lck controls the latches for storing test vectors. The lines scj 0, scj1…..scjl-1
are the inputs for the encoded data to control the capture operation of the signature registers. The BCD decoder
decodes the encoded input data to the control data of the signature registers sck0…sck m-1. As explained later, the
decoder is used to reduce the input lines for the control data of the signature registers. The sge is the enable
signal for the signature registers. The control lines of the signature registers are connected to the BCD decoder.
Figure 4: measurement system
A. MEASUREMENT SEQUENCE PER TEST VECTOR
When the measurement system has m signature registers, m paths can be measured in parallel
maximally. The measurement strategy using the example is depicted in figure5. In this example, the proposed
method consists of six flip flops 𝐹𝐹0 -𝐹𝐹5 .the flip flops are classified to the two clusters 𝑐𝑙0 and𝑐𝑙1 . Each cluster
has its own signature register 𝑆𝐼𝐺0 and 𝑆𝐼𝐺1 respectively. The paths𝑝1 , 𝑝2 , 𝑝3 , 𝑝5 are sensitized by the test
vector (𝐹𝐹0 , 𝐹𝐹1 , 𝐹𝐹2 , 𝐹𝐹3 , 𝐹𝐹4 , 𝐹𝐹5 ) = (0, 0, 1, 0, 1, 1).The test response of𝑝 𝑖 , is captured by𝐹𝐹𝑖 . The expected
test response is (𝐹𝐹0 , 𝐹𝐹1 , 𝐹𝐹2 , 𝐹𝐹3 , 𝐹𝐹4 , 𝐹𝐹5 ) = (1,1,0,1,0,0). The paths 𝑝1 and 𝑝2 are measured by 𝑆𝐼𝐺0 . The
paths 𝑝3 and 𝑝5 are measured by 𝑆𝐼𝐺1 . The combination of two paths, one of which is selected from 𝑝1 and𝑝2 ,
the other which is selected from 𝑝3 and 𝑝5 , can be measured simultaneously. First, the test vector is set to the
flip flops with scan-in operation. After that, the values of flip flops are set to extra latches. Second, the first
stage is performed. Third the second stage is performed. In each stage, the paths under measurement are tested
multiple times with reducing test clock width. Steps (b) and (c) show the state after test execution. The flip flops
hold the test response. The latches hold the test vector. After testing, the responses are shifted to signature
registers with clock operation of𝑐𝑙𝑘. The number of required shift clocks varies in each stage.
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4. International Journal of Modern Engineering Research (IJMER)
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3042-3048
ISSN: 2249-6645
Figure 5: measurement of paths sensitized in attest vector in parallel. (a) scan-in test vector and store it in
latches. (b) Sending test responses of 𝑝1 and 𝑝5 to 𝑆𝐼𝐺0 and𝑆𝐼𝐺1 . (c) Send test responses of 𝑝2 and 𝑝3
𝑆𝐼𝐺0 and 𝑆𝐼𝐺1 .
Figure6 shows the timing chart of operation. The low cost tester controls the whole measurement
sequence. For measurement both VCG clock and tester clock are used. The clock controlled by 𝑐𝑠. The triggered
signal 𝑡𝑟𝑔 and control signal 𝑐𝑛𝑡 are provided to VCG. The control data 𝑐𝑛𝑡 is updated after each testing
operation. In 𝑆𝑇𝐺0 , 𝑆𝐼𝐺0 captures the test response in second shift-out clock. Therefore 𝑠𝑐𝑘0 turns to 1
synchronizing with the negative edge of first clock of the shift-out operation. The latch clock 𝑙𝑐𝑘 captures the
value of the flip flops just after scan-in operation is finished.
1) Scan-in test vector.
2) Set initial vector to 𝐿 𝑗 .
3) Apply test clock.
4) Transfer test responses to signature registers.
5) Retrieve signature data.
Figure 6: timing chart of the sequence of figure5.
B.WHOLE MEASUREMENT SEQUENCE
Let us assume that the test set for measurement 𝑇𝑆 has 𝑁 𝑇𝑉 test vectors𝑡𝑣0 , … . . 𝑡𝑣 𝑁𝑇𝑉 −1 . The number
of stages of 𝑡𝑣 𝑖 is𝑁 𝑠𝑡(𝑖) . Before measurement, we have to check if the flip flops, the latches, and the clock
generator work correctly by applying test vectors. After that the following measurement sequence is executed.
Step 1: Initialize the variable𝑖 = 0.
Step 2: if 𝑖 is equal to𝑁 𝑇𝑉 , finish, otherwise initialize the variable 𝑗 to0, and set 𝑡𝑣 𝑖 to the flip flops with scan-in
operation.
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3042-3048
ISSN: 2249-6645
Step 3: send the values of flip flops to the latches.
Step 4: the paths included in 𝑆𝑇𝐺𝑗 are measured simultaneously. After that, 𝑗is updated to
(𝑗 + 1).
Step 5: if 𝑗 equal to 𝑁 𝑠𝑡(𝑖) , go to step 6, otherwise load the test vector from the latches to flip flops, and go to
step 4.
Step 6: 𝑖 is updated to 𝑖 + 1 , and go to step 2.
C.TESTER CHANNEL REDUCTION
If 𝑠𝑐𝑘 of each signature register is directly fed to the inputs of the chip, it requires the same number of
extra inputs as the number of the signature registers. It increases tester channel width. To keep the tester channel
width short, we use BCD decoder. The decoder circuit transforms 𝑛 bit binary code in to the corresponding
2 𝑛 width decimal code. The example to encode 𝑠𝑐𝑘 bit sequences to the corresponding binary code is shown in
figure7. It consists of three clusters 𝑐𝑙0 , 𝑐𝑙1 , and 𝑐𝑙2 . Each cluster has three flip flops. Consider the case that test
response of sensitized paths are captured in 𝐹𝐹01 , 𝐹𝐹12 , 𝐹𝐹20 .in the shift out operation after a testing, the test
response of 𝐹𝐹01 is captured by 𝑆𝐼𝐺0 two clocks later. Therefore the bit sequence “010” should be sent
to 𝑠𝑐𝑘0 .the test response of 𝐹𝐹12 is captured by 𝑆𝐼𝐺1 one clock later. Therefore the bit sequence “100” should
be sent to 𝑠𝑐𝑘1 . The test response of 𝐹𝐹02 is captured by 𝑆𝐼𝐺2 three clocks later. Therefore bit sequence “001”
should be sent to 𝑠𝑐𝑘2 . Each bit value of this bit sequence is grouped. The group of 0 th bit value
is 𝑠𝑐𝑘0 𝑠𝑐𝑘1 𝑠𝑐𝑘2 = 010.
Those
of
first
bit
values
and
second
bit
values
are
𝑠𝑐𝑘0 𝑠𝑐𝑘1 𝑠𝑐𝑘2 = 100, 𝑠𝑐𝑘0 𝑠𝑐𝑘1 𝑠𝑐𝑘2 = 001, respectively. We call each group slice. Here, 𝑠𝑙 𝑖 represents the
slice of 𝑖 𝑡ℎ bit. Finally the decimal codes are transformed to binary code. The 0th slice 𝑠𝑙0 “010” is transformed
to “10”. The 1st slice 𝑠𝑙1 “100” is transformed to “10”. The second slice 𝑠𝑙2 “001” is transformed to “11”. As a
result the bit width of data is reduced from 3 bit to 2 bit by transformation. Generally, the width of the slice of
𝑠𝑐𝑘 is 𝑛, the width of encoded slice of 𝑠𝑐𝑗 is 𝑙𝑜𝑔2 𝑛 . However, for the encoding, each slice is permitted only
1 bit with the value 1. More than two bits with the value are not permitted.
Figure 7: encoding the output data of BCD decoder
D.TEST RESPONSE TRACING
The target paths of proposed measurement are single-path sensitizable. In single path sensitizable
measurement, it is guaranteed that once the test fails the test with higher frequency than the failing frequency is
fail. Let 𝐿 𝑆𝐼𝐺 be the length of the signature register, the measurement sequence of a path with test response
tracing mode is described as follows.
Step1: SIG is initialized.
Step2: Test vector is loaded from the latches.
Step3: Test clock width T is set to normal clock width.
Step4: Test clock is applied.
Step5: The test response is sent to SIG with scan-out operation.
Step6: If testing is equal to 𝑁 𝑚𝑒𝑎𝑠 or multiple number of 𝐿 𝑆𝐼𝐺 , the values of flip flops of SIG is retrieved. After
that, if testing time is equal to 𝑁 𝑚𝑒𝑎𝑠 , go to step 7, otherwise go back to step 2after the test clock width T is
updated to 𝑇 − Δ𝑇 .
Step 7: The delay value is estimated by comparing the retrieved signature value and the signature table.
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3042-3048
ISSN: 2249-6645
IV.SIMULATION RESULTS
In this section, on-chip path delay under different process variations will be simulated and measured.
During the simulation we measure the delay of each path under test. Random faults were injected in circuits to
generate erroneous data. Random input patterns were applied to the ISCAS-89 benchmark circuits and
compared with proposed method. The length of the signature register is 8 bit. The test set consists of test vectors
which detects all single-path sensitizable transition faults. The paths sensitized by these test vectors are
measured. The measurement times using the proposed scan design and is calculated by Tsig =time required for
{whole scan-in + double pulse + SIG data}
Simulation results of delay measurement using signature register are shown in figure8 and figure9
Figure 8: Simulation results
Figure9: simulation results
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7. International Journal of Modern Engineering Research (IJMER)
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3042-3048
ISSN: 2249-6645
The device utilization summary for the delay measurement technique is shown in Table I
Logic utilization
Total number of slice register
Number used as flip flop
Number used as latches
Number of 4 input LUTs
Number of occupied cells
Number of slices containing only
related logic
Number of slices containing unrelated
logic
Number of 4 input LUTs
Number of bonded IOBs
Number of BUFGMUXs
Average fan out non clock nets
used
43
31
12
47
47
47
available
7,168
Utilization
1%
7,168
3,584
47
1%
1%
100%
0
47
0%
47
7,168
13
141
3
8
2.76
Table I: device utilization summary
1%
9%
37%
CONCLUSION
• The proposal of the delay measurement method using signature analysis and variable clock generator.
• The proposal of a scan design for the delay measurement of internal paths of SOC.
The first proposal can be applied not only SOC but also field programmable gate array (FPGA). A
future work is the low cost application of the proposed measurement to FPGA. When we measure short paths
the measurement error can increase for the IR drop induced by higher test clock frequency. It can reduce the test
quality. Another future work is the reduction and the avoidance of the measurement error caused by the IR drop.
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