DFT (design for testability) is a technique that facilitates making a design testable after production by adding extra logic during the design process. This extra logic helps with post-production testing. DFT is needed because manufacturing processes are not perfect and can introduce defects. Methods like adding scan chains are used, where scanned flip-flops are connected in series to form a shift register and improve controllability and observability for testing. Common fault models tested for include stuck-at faults, where a line is stuck at either a 0 or 1 value due to defects introduced during manufacturing.

1. DFT (design for testability)

2. OBJECTIVES
 What is DFT?
 Why we need DFT?
 DFT methods.
 What is scanned flip flop?
 What is scan chain?
 Fault models.
 Stuck at fault models.

3. What is DFT?
 DFT is a technique, which facilitates a design to become
testable after production. Its the extra logic which we put in
the normal design, during the design process, which helps
its post-production testing.

4. Why we need DFT?
 Post-production testing is necessary because, the process of
 manufacturing is not 100% error free.
 There are defects in silicon which contribute towards the errors introduced
in the physical device.
 Of course a chip will not work as per the specifications if there are any
errors
 To increase Productivity
 To improve Quality
 how to detect that?

5. Basic principles:-
 Controllability
 Observability

6. DFT methods
There are two types of dft methods are
DFT methods for digital circuits:
 Ad-hoc methods
 Structured methods

7. DFT techniques
Ad-hoc technique:-
 it Is temporary technique
 Good design practice learnt through experience are used as guide lines for ad-
hoc DFT
 Structural technique:-
 it provides more systematic & automatic approach to enhance the design
testability.
 It targets manufacturing defects.

9. Sequential circuit( before adding scan chain)

10. What is scanned flip flop?
 D flip flop followed by mux…

11. Scan chain
 A scan chain is formed by connecting the scanned flip -flops in serial manner , it will
function like a shift register. And it is used to perform controllability and observability.

12. After adding scan chain

13. Fault models
FAULT MODELS
 Stuck-at fault model
 Transistor faults
 Bridging faults
 Delay faults
• Delay faults can be classified as:
• Gate delay fault
• 2) Transition fault
• 3) Hold Time fault
• 4) Slow/Small delay fault

14. Fault modeling
Def:-
Due to defect during manufacturing of integrated circuit, There is need to
model the possible faults that might occur during fabrication process, this is
called fault modelling.
 Stuck-at-fault.
 Transition fault

15. Stuck at fault:-
 It is most popular fault model used in practice .
 These faults occurred due to process variations , manufacturing defects.

16. Stuck at fault models