This document presents the design and analysis of different layout approaches for an SR flip flop circuit using NAND gates on a 90nm technology node. It first describes the schematic design using 16 MOS transistors and its simulation. Layouts are then generated using a fully automatic technique and two semi-custom techniques with either one or two transistor "fingers". The semi-custom layouts with one and two fingers consume 40-62% and 62-91% less area and power, respectively, compared to the automatic layout, though they have more nodes. Analyzing the simulated results, the paper concludes that a semi-custom layout approach can reduce area and power consumption at the cost of increasing the number of nodes.