This document describes the design and simulation of an efficient CMOS full subtractor circuit layout using 90nm technology. It compares an automatically generated layout from DSCH software to a semi-custom layout designed manually in Microwind. The semi-custom layout has a 99% reduction in area at 393.6 μm2 compared to 2054.3 μm2 for the automatic layout, though it has a 74% increase in power consumption. The semi-custom design is more area efficient while the automatic design has lower power consumption. Simulation waveforms verify the logical correctness of both designs.

1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 40
Efficient Layout Design of CMOS
Full Subtractor
Harmeet Singh
ME Scholar, Department of Electronics and Communications Engineering
National Institute of Technical Teachers Training & Research, Chandigarh, India
harmeet_s_d@yahoo.co.in
Abstract—Arithmetic circuits and for that matter
Combinational circuit design is very important part of VLSI
design process. The pertinent issues involved are layout area
and power consumption. The main aim of this paper is to
design a full subtractor using 90 nm technology. The
proposed full subtractor has been designed and simulated
using DSCH 3.1 auto-generated design and using Microwind
3.1 simulation software for semi-custom design. The results
obtained show that the semi-custom design is area efficient
than the auto-generated design. On the other hand, power
consumption in the later is more as compared to the auto-
generated design.
Keywords—Automatic,Full Subtractor, Semi-Custom, VLSI
INTRODUCTION
Advances in CMOS technology have led to a invigorated
interest in the development and methods of basic
functional units for digital systems. Increased usage of the
battery-operated portable devices, like cellular phones,
personal digital assistants (PDAs), and notebooks demand
VLSI(Very Large Scale Integration) is the technology, and
ULSI i.e. Ultra Large-Scale Integration designs with an
improved power-delay characteristics. Full
subtractors/adders, being one of the most fundamental
building block of all the aforementioned circuit
applications, remain a key focus domain of the researchers
over the years [1], [2]. Due to this, technology scaling and
energy-efficiency of functional units is of increasing
importance to system designers. VLSI is the technology for
creating an integrated circuit by combining millions of
transistors in a single Integrated Circuit. The
microprocessors used in DSP operations e.g. in image
processing applications. Before the introduction of VLSI
technology, most ICs had a limited functionality. ICs have
three key advantages over digital circuits viz. size, power
consumption and speed. This leads to layout design and its
simulation so as to get very near to an implementable
circuit design on silicon wafer. So far several technologies
have been used to design full subtractor cell to improve
area and power consumption [4]-[8]. Design of full
subtractor by using conventional CMOS design style has
been presented. To study the performance of reduced
transistor circuit count design, a transistor level design of
CMOS full subtractor containing a total of 17 PMOS and
17 NMOS transistors has been implemented. It is required
to adjust the transistor dimensions individually to get
optimized time domain performance of the circuit. Here,
all NMOS and PMOS transistors used in this circuit have
the same W/L ratio. This leads to a semi-custom design.
SUBTRACTOR
Half-Subtractor
A half subtractor is a circuit using combinational design
principles that performs a subtraction between two bits as
shown in Fig.1. The circuit performs its function using two
inputs A, B viz. minuend, subtrahend and two outputs, one
bit for result of subtraction viz. Diff , and an output
borrow Bout [9].
Fig. 1 Logic Diagram of conventional Half Subtractor
Full Subtractor
1- bit full Subtractor is a circuit based upon combining two
half-subtractors that performs subtraction between two
binary bits. This circuit performs its function using three
inputs keeping account of a previous borrow and two
outputs. The three inputs are A, B and Bin and Boout and
Diff are two outputs[9]. Logic diagram of 1-bit full
Subtractor has been shown in Fig.2. The corresponding
Truth Table is given in Table 1.
Fig. 2 Logic Diagram of conventional 1 bit Full Subtractor

2. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
41 NITTTR, Chandigarh EDIT-2015
Table 1:
From the Truth Table,we find the logical expressions for
the full subtractor as follows:
Bout = Bin (A’B’ + AB) + A’B
Diff= A ⊕ B ⊕ Bin
In subtraction process on two bits, a minuend and a
subtrahend, and also takes into consideration whether a 1
has been borrowed by the previous adjacent lower
minuend bit or not. As a result, there are three bits to be
handled at the input of a Full-Subtractor, namely the two
bits to be subtracted and a borrow bit designated as Bin.
There are two outputs, namely the Difference output Diff
and the Borrow output Bout. The Borrow output bit tells
whether the minuend bit needs to borrow a 1 from the next
possible higher minuend bit.
III. LAYOUT DESIGN SIMULATION
In first method the schematic of full subtractor using two
half subtractors is designed using DSCH. Using
Microwind software auto-generated layout of full-
subtractor is created, and then it is simulated for analog
simulation. In the present design, 90 nm foundary is
selected. Figure 3 shows the auto-generated layout. The
layout is checked for DRC so that the errors if any are
removed, and then it is simulated for Timing Waveforms.
Generated waveforms are verified for logical /functional
correctness. Also Power and Surface Area are measured by
the simulation results[10].
Figure 4 shows the timing diagram of auto-generated
layout.
Fig. 3. Manually designed Layout of XOR/FS
Fig 4. Analog Simulation of auto-generated FS
Here, the Power consumption is 1.295 µW. Area required
for this particular layout is 1810.3 µm2
. In the second
approach i.e. semi-custom approach, we prepare layout
using manual approach; an xor design using lesser number
of transistors is used but the designer uses lambda rules as
a whole. Figure 5 shows the layout thus generated.
Fig. 5. Manually designed Layout of FS
The semi-custom layout is checked for DRC so that errors
are removed. The circuit is simulated and timing
waveforms are generated. The timing waveforms are
verified using Truth Table for logical correctness. Fig. 6
shows the results of this simulation.
Fig. 6 Analog Simulation of Semi-custom FS
Here, the Power consumption is 1517.7 mW. Area
required for this particular layout is 393.6 µm2
. In the
second approach i.e. Semicustom approach, we prepare
layout using manual approach; an xor design using lesser
number of transistors is used but the designer uses lambda
rules as a whole. Figure 6 shows the layout thus generated.
IV. PERFORMANCE
The performance of proposed full subtractor layout is
compared with semicustom approach when the auto

3. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 42
generated design is the reference. The performance
parameters are area and power. From the results obtained,
a comparative study can be done between three design
approaches Table II shows the comparative analysis.
S.No.
Performance parameters
Design
method
Area(µm2
) Power(µW)
1
2
Auto-
generated
2054.3 393.2
Semi-custom 16.683 1517.7
From the above table, we observe that there is a reduction
of 99% in area with autogenerated layout. Simultaneously
there is 74% increase in area with the semicustom design
approach.
IV. CONCLUSIONS
From the above analysis it is clear that the semicustom
design is significantly more efficient in terms of area. So
this design can be implemented where area reduction is the
main consideration . A large number of application abound
where this is required as in portable devices like smart
phones, remote controls , tablets and so on. There is some
degradation in logic levels during simulation which shall
be worked upon and improved upon in the continuing
research effort, by the authors,in this particular area.
ACKNOWLEDGEMENTS
The authors would like to thank Director, National Institute
of Technical Teachers Training & Research, Chandigarh,
India and Director, Sunrise Group of Engineering and
Technology for their constant inspiration and support
throughout Research Work.
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