Ramya Project

PERFORMANCE ANALYSIS OF CMOS FULL ADDER CIRUITS AND
VLSI DESIGN OF MULTIPLIER USING MENTOR GRAPHICS
CHAPTER 1
INTRODUCTION
In electronics, digital circuit consisting of adder does summing of two numbers.
Adders are used in ALU units, processors, and in other places such as calculation of
addresses like physical addresses, counters, timers. Most of adders use binary numbers only.
Representation of signed numbers is quite complex than unsigned. 2’s complement and 1’s
complement operation must be performed to add signed numbers.
In logical designs half adders and full adders are preferred for binary calculations;
either half adder or full adder mainly deals with binary numbers. Half adder consists of three
inputs (e.g: A, B, and C), and outputs sum and carry, which performs two bit addition of
binary numbers. For multistage addition in the circuit carry signal signifies that overflow for
next digit. Further, combining of two half adders constitute a full adder digital circuit, which
performs an addition of three inputs and two outputs. For higher level designs of computer
processor efficient full adders are used. Full adders can be constructed in many ways through
basic gates, custom transistor level etc. Consider full adder using XOR with AND gate for
calculating the delay.

Figure 1.1 Full adder using basic gates
From the figure of full adder using basic gates, sum output obtained from XOR gate.
For example to compute operation of addition, XOR gate takes 3delay, and then delay from
critical sum path is
TFA = 2, TXOR = 2*3D= 6D
The block of carry consists of 2gates therefore the delay is TC =2D
Considering more complex adders like, Ripple carry adder, Look ahead carry unit,
Carry save adders are much difficult to design. Ripple carry adders are complex adders,
which are used for addition of N-bit numbers, previous carry bit ripples to fore coming full
adder’s input, nothing but full adders are cascaded each other. Like this other adders like
carry select adders, conditional sum adders, carry skip adders, and carry complete adders.
Look ahead carry adders are used as units for some higher level bits addition, like 32 bits,
64bits. In the case of carry save adders three input full adders are cascaded, after all addition
finally conventional adder as ripple carry or look ahead adders are combined for final sum
and carry outputs.
An electronic circuit used to multiply two binary numbers in digital electronics called
as a binary multiplier. Most many computers until the year 1970’s had no instruction to
multiply, so they were using ‘multiple routine’ which shifts and accumulates repeatedly as a
partial results, though first introduced microprocessors also was not composed with a
multiply instructions. Later on in 1978 Motorola 6809 introduced a multiply instructions for
16-bit processors. Basic operation of binary multiplication of two numbers, each digits of
binary numbers multiplied with each digits of another multiplicand , the each partial product

is listed by shifting left by one place, at the end add all partial products gives the multiplied
result of binary numbers.
In the beginning multiplier design was made with shifter and accumulator for each
partial product which led a complexity in the area. As an evolution in multiplier Baugh
Wooley and Dadda or Wallace Tree multiplier algorithms were used in modern multiplier.
FMA (Fused multiply and add) method of multiplication, deals with multiplications of
floating point numbers. If c and b are floating numbers which are going to multiply, this
product will be rounded to N significant numbers and store in accumulator as ‘a’, that is
a+b*c, hence it is known as FMA.
1.1 PROBLEM STATEMENT
The purpose of this project is to find high performable circuit in terms of time delay,
power dissipation and PDP. The full adder with high speed, low power dissipated is used in
the design of multipliers. Newly designed multiplier is also analyzed for speed and power
dissipation. For any VLSI design, speed is the major concern, so keeping this in mind adders
and multipliers are analyzed.
1.2 SCOPE OF THE PROJECT
In this project work, performance analysis of group of different structures of full
adders is analyzed; the high speed full adder is used in designing multipliers and analyzed the
parameters. Further according to the application multipliers can also be used in multiplier-
and-accumulator (MAC), filters for high end designs.

CHAPTER 2
LITERATURE SURVEY
The work carried out by R. Dhayabarani, R. S. D. Wahida Banu, [1] proposes 8T
1bit full adder consists of six MOSFETS and multiplexer using two MOSFETs for reducing
the power consumption and delay. The proposed design and other designs like 14Trasistor
full adder, 20Transistor full adder, 28Transistor full adder, Conventional full adder, and
Transmission gate full adder are analysed via HSPICE simulations with 0.18um technology
and 1.2V supply voltage. Then high speed proposed full adder was considered to design
Wallace tree multiplier, Array multiplier, Braun multiplier, Baugh Wooley multiplier. Author
said that, Wallace tree multiplier a viable to efficient design for Digital FIR filter.
The work carried out by Deepak Garg, Mayank Kumar Rai,[2] proposed the
implementation of full adder 3T XOR and 2-to-1 multiplexer modules were used and with
total 8Transistors. Proposed full adder was compared against 10T full adder, 12T full adder,
16T full adder, 28T full adder. Here results are simulated through TANNER-EDA with 2.3
supply voltage based on 0.18um CMOS technology. An author said that, compared to other
full adders 8T adder successfully embeds the buffering circuit. 3T XOR based full adder
gives high speed, low voltage, and that lead to less energy consumption. As the transistor

count is less it consumes less chip area, less cost of manufacturing, that was done via
designing and simulating the layout.
The work carried out by Deepali Sandhu, Sudhir Singh, Satwinder Singh [3]
presents the comparative work of low voltage, high speed full adder circuits. Here hybrid
design full adder approach combined in a single unit, and adder is designed using XOR-
XNOR. Also discussed conventional full adder combined with MOSCAP is called hybrid
design. This technique helps to reduce propagation delay, power consumption, and area of the
chip design. Simulation results in terms of delay, power, power delay product (PDP) are
compared against conventional CMOS, TG, and hybrid adder circuits.
Shipra Mishra, Shelendra Singh Tomar, Shyam Akashe, in “Design low power
10T full adder using process and circuit technique” [4] proposed 10T full adder analysed for
minimizing the leakage current, leakage power and boost up the speed. This analysis carried
out in different process and circuit techniques. To minimize the leakage power, minimum
transistors were used, and made variation in transistor dimension for reducing leakage
current. These simulations carried out through Cadence environment virtuoso tool with a
0.45um technology and for different supply voltages. This also expresses that, design lines
need to select suitable to required design features. On implementing on deep sub micron
method CMOS leakage current reduced at the process level. Most of the power consumption
decreased at the circuit level by constructing designs using less number of MOSFETs.
K. Nehru, A. Shanmugam, S. Vadivel in “CLRCL full adder based low power
multiplier architectures” [5] this power consumption, speed and area are the major concern.
The introducing CLRCL (complementary and level restoring carry logic) adder performance
analysed from designing multipliers using full adder. Here Braun multiplier, Array multiplier
and Baugh Wooley multiplier is designed using CLRCL full adder. As we all know designing
an efficient circuit is challenge in VLSI design stream. All multipliers were simulated for 4
bit data, verified results on a Tanner EDA tool with 250nm technology. Conventional based
multipliers are less performed than CLRCL based multipliers and exhibits better area on chip.
Among designed and simulated multipliers, array multiplier gives better performance of
power consumption compared with Braun and Baugh Wooley.
Dhireesha Kudithipudi and Eugene John in this, [6] compared parameters such as
power, delay and power delay product of multipliers. Here four different designs of digital

Multipliers are constructed using 10T full adder, SERF full adder, 28T full adder. Multiplier
constructed using 28T full adder given the significant response on 180nm technology, but not
on 70nm. Using SERF designed multiplier resulted less power consumption than 10T full
adder used multiplier. Regarding propagation delay 10T full adder used multiplier established
better than others. Designed multipliers were Carry save multiplier, Bit array multiplier,
Wallace multiplier, Baugh Wooley multiplier, among these Carry save multiplier had better
PDP than other multipliers, and this demonstrated using 2*2, 4*4, and 8*8 bits to all
multipliers, and also said that, at the final stage of multiplication by incorporating hybrid
adder module forms critical path delay and high static leakage current zone.
The authors, Saradindu Panda1, A. Banerjee, B. Maji, Dr. A. K.
Mukhopadhyay,[7] proposes the research on evolution of full adder to achieve high
performed full adder in all important parameters. Starting from conventional 28T CMOS full
adder, 20T transmission gate full adder, 14T full adder, 10T static energy recovery full adder,
10T realised using GDI (gate diffusion input), 9TA, and 9T B full adder, at last 8T full adder.
Above all the adders have advantages and disadvantages with their respect. GDI based adder
performed better but fabrication of MOSFET are cost effective, fabrication process is twin
well CMOS SOI (silicon on chip). TG (transmission gate) based adders showed low average
delay, but 14T full adder had low power delay product. So they thought that, 8T full adder
was the best option for optimization of power and delay.
The work carried out by Prof. S. Murugeswari, Dr. S. Kaja Mohideenn [8]
presents that, Wallace tree multiplier and truncated multiplier was constructed by carry save
adder and that was demonstrated. Further author had replaced proposed carry save adder
with a modified carry save adder (MCSA) and implemented using multiplexer. Multiplexer
based full adder was used instead of regular full adder in truncated multiplexer. 8 x 8
Multiplier had simulated on Model sim 6.3c and on Xilinx10.1 had carried out. The proposed
multiplexer based multiplier had reduced 25% of area and 10% of power reduction than
existing system these all carried out on Xilinx Spartan 3 XC3S50 FPGA. Hence truncated
multiplier with MUX based full adder would be the less power dissipated and less chip area
occupied.
Saravanan R, Kalaiyarasi M, S. Jim Hawkinson, D Sathya, [9] this presented in
order to achieve high speed, low power dissipation, and power delay product various

technique style had used, those were hybrid CMOS logic style to decrease PDP, Gate
diffusion input (GDI) logic styles, and alternative internal logic styles. Author also presented
full voltage swing along with high speed, low power dissipation. There was an evolution in
full adder parameters by conducting different experiments from different designs. Initial
design was the hybrid logic style, later constructed by utilizing GDI based full adder, and
GDI technique also eradicated from construction of full adder with XOR/XNOR. This
approach provided the high speed, very low power, and voltage swing. This work was
compared with the other full adder in 1-bit, 2-bit, 4-bit, 8-bit and 16-bit structures and this
technique was better. All designs were simulated in 180nm technology on Mentor Graphics
tool and results analyzed in test bench forms.
Shahebaj Khan, Sandeep Kakde , Yogesh Suryawanshi, [10] in digital signal
processors, FIR filters and microprocessors multipliers are the weighty blocks. As the
research was keep on going about optimizing area and increasing speed of multipliers, so
they were resulted as high speed with the large area. Here author had proposed solution for
that; by introducing reduced complexity Wallace Tree (RCWT) form previous Wallace Tree
multiplier, it also required a high efficient full adder. RCWT had less number of adders than
previous, at final stage of multiplier connected with a carry propagating adder hence both
gave save time delay. Then RCWT was constructed using energy efficient CMOS full adder.
As a result power, area and speed were improved. Thus the proposed method of multiplier
reduced total 70-80% of half adders count than standard Wallace Tree multiplier.
Karthik Reddy. G [11] in integrated circuits power consumption is the major
concerns and in leakage power is the major concept. ALU containing major roles of full
adder, by lowering the power consumption of full adder, power consumption of ALU would
be reduced and lowering power consumption ALU processors power consumption could also
reduce. Here the author proposed that designing low power and less transistor count full
adder on cadence tool and virtuoso platform with 180nm n-well CMOS technology by
supplying voltage 1.8V and frequency 100MHz. New designed 6T full adder saved 93.1% of
power, compared to 28T adder, SERF by 80.2%. It also highly performed than pass transistor
and GDI techniques.

The work carried out by P.V. Rao, Cyril Prasanna Raj P, S. Ravi, [12] proposes
that, now a days in digital signal processing high clock frequencies and low power multipliers
are very important. Here author proposed the performance analysis of array multipliers,
Baugh Wooley multipliers and Wallace Tree multipliers. Physical verifications and
functionality checking were carried out on HSPICE. On Cadence Virtuoso layouts were
designed, DRC and LVS rules were verified using Hercules I. Multipliers should be selected
with respect to the application and performance based. Wallace Tree multiplier exhibited
least power and delay and less area in array multiplier.
CHAPTER 3
IMPLEMENTATION
3.1 INTRODUCTION
Adders are the fundamental building blocks for designing of any VLSI system
architectures; in this project three inputs and two outputs full adders are considered. A group
of full adders are analyzed according to their performance in terms of time delay, power
dissipation, power delay product (PDP) and power consumption. Time delay is that,
minimum period of time to drive output from the input, power dissipation is the loss of power
in the circuit to drive the output, and total power used by the circuit to perform the operation
is power consumption. Among those considered adders, high performed full adder that is
high speed, less power loss and less power consumed adder will be used in higher designs.
The high performed full adder is used for the design of multipliers.
Here group of full adders are taken for analysing the performance. In that some
special type of full adders are considered like CLRCL (complementary and level restoring
carry logic), SERF (static energy recovery full adder), GDI (gate diffusion input) based full
adders, and other adders are GDI_XOR full adder, GDI_XNOR full adder, full adder 9TA,
full adder 9TB, 8T full adder, 9T full adder, 6T full adder type I, 6T full adder type II are
analyzed.
All ten different full adders are designed using various numbers of MOSFETs. These
full adders are analyzed using Mentor Graphics tool with 180nm technology. The simulated
results are observed and found the high speed, less power dissipated, less PDP and less power

consumable full adder as the best performed full adder. This high performed full adder is
used for designing Multipliers.
Basically multipliers are for multiplying two signed or unsigned numbers. In this
project 4*4 multipliers are considered for multiplication. There are many kinds of multipliers;
structure based multipliers, logic based multipliers, and algorithm based multipliers. High
performance full adder is used in different multipliers such as array multipliers, Braun
multipliers, Baugh Wooley multiplier and Wallace tree multiplier. Each designed multipliers
using full adder, performed according to the complexity of the circuit. Then these multipliers
can be used for further high designs of VLSI architectures.
As a result of Full adder analysis 8T full adder is exhibited high speed, low power and
less PDP. The high performed 8T full adder further used in designing of multipliers, and
observed the time delay and power dissipation for each multipliers.
3.2 BLOCK DIAGRAM
3.2.1 FULL ADDER
Addition is the initial step for most of digital designs, so here the full adder is
considered as initial design for next higher level circuit operation. It consists of three inputs
as A, B and C, two outputs as Sum and Carry. Functional table of full adder shown below
Table 3.1 Full adder input combinations and outputs
Inputs
Outputs
A B Cin
Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0

1 1 0 1 0
1 1 1 1 1
There are group of full adders with different circuit designs, and various number of
transistors count. The block diagram of full adders such as GDI_XOR full adder,
GDI_XNOR full adder, 9TA full adder, 9TB full adder, SERF full adder, 8T full adder,
CLRCL full adder, 9T full adder, 6T type I full adder, and 6T type II full adder are shown in
figure 3.1 to 3.10
Figure3.1 GDI_XOR#ADDER
In full adder, using Gate Diffusion Input (GDI) technique structures are designed. In
the Circuit operation sum is generated through the second stage XOR design of full adder and
Cout is obtained by multiplexing B and Cin restricted by A xor B. GDI cell has three inputs
for the particular transistor, this is one major advantage, based on the application this
technique can be used. Also reduces the transistor counts than CMOS design. It requires SOI
or twin-well CMOS fabrications, which leads to more cost effective for huge designs. And
has slow driving capability difficult for chip designing.

Figure 3.2 GDI_XNOR#ADDER
In GDI_XNOR full adder, using Gate Diffusion Input (GDI) technique structures are
designed. Arrangement of transistors is same as GDI_XOR full adder, only interconnections
between transistors manipulated. The sum is generated through the second stage XNOR
design of full adder and Cout is obtained by multiplexing B and Cin restricted by A xor B.
Figure 3.3 9TA full adder
9transistors full adder designed using a CMOS technology. Circuit operates according
to inputs given; outputs can be driven as Sum and Cout. By observing transistor count of this
full adder can say that it consumes less power and high speed compare over 10T full adder

and 28T full adder. Full adder using 9transistors can be designed in two ways so named as
9TA and 9TB.
Figure 3.4 9TB Full adder
Above structure is another way of designing full adder using 9Transistor is named as
9TB full adder. By manipulating Cin input connection gives the full adder results.
Figure 3.5 SERF Full adder
As explained for the GDI_XOR and GDI_XNOR, SERF full adder also performs
same. Sum is obtained from the result of the second stage of XNOR circuit. Cout resulted by
multiplexing a and Cin is controlled from a xor b. Consider first module of XNOR attached

to the capacitor, when a=b=0 capacitor will be charged by Vdd, then b reaches a high voltage
with keeping constant low voltage for next stage, then some charge is remained in ‘a’ after
discharging capacitor via a, hence no need of charging again when a reaches high voltage
level.
Figure 3.6 8T-full adder
Above 8T full adder is designed using three transistors XOR and 2:1 multiplexer so
total 8 transistors with a technique of PMOS pass transistor and inverter using CMOS, which
can improve in delay. A Sum result is obtained from two XOR circuits and carry from
multiplexer. This technique also says that by varying W/L ratios of transistors it is possible to
achieve minimum voltage drop, increased noise margin. Power delay product as well as area
on chip also reduces since it consists if only 8transistors.

Figure 3.7 CLRCL full adder
The Complementary and level restoring carry logic full-adder is to overcome from
multiple threshold losses in carry result. It is a low complexity circuit, hence can obtain fast
enough cascade operations. It is designed basically inverter based technique, so it has 5
inverter pairs. XOR circuit also implemented through the inverter. To overcome from
threshold loss CLRCL adder functions as a level restoring adder circuit, through MUX2/3
restored output is fed. To speed up the carry propagation, adder acts as a buffer with carry
output. To simplify XOR design complementary signal outputs are useful. CLRCL adder is
proposed to solve problems in the SERF signal. This adder is designed due to overcome
problems of distortion in the carry signal.
Figure 3.8 9T full adder

The 9transistor is a modified design of CMOS inverter as well as pMOS transistor, it
consists of 3T XOR gates. Voltage degradation occurs because of threshold voltage drop over
transistor M3 when input A=1, and B=0. By increasing W/L ratios of M3 transistor the
voltage degradation can be reduced.
Figure 3.9 6T type II full adder
The 6T full adder is constructed using basic PMOS and NMOS logic, in the 6T full
adder, twice 2T XOR module sum is generated, and by the NMOS and PMOS pass transistor
logic devices carry is generated.
Figure 3.10 6T type I full adder

3.2.2 MULTIPLIER
In digital electronics a binary multiplier is an electronic circuit, which is used in
processors of computer, for multiplying the two binary numbers. It is designed using binary
full adders. Basic operation of the multiplier is shown below.
Figure 3.11 Basic operation of multiplier
Here are different types of multipliers. Some of them are considered,
i. Wallace Tree multiplier
ii. Array multiplier
iii. Braun multiplier
iv. Baugh Wooley multiplier
i. Wallace Tree multiplier
In the year 1964, C.S. Wallace developed the fast process for multiplication of
numbers. He invented that, structure of multiplier which exhibits the parallel addition
operations; here partial product bits arranged like a tree of adders, hence the name as
“Wallace Tree”. A Wallace tree is an efficient hardware implementation of a digital circuit.

Using Wallace tree technique to perform particular operation, partial product matrix is
reduced to a two-row matrix by using full adders and obtained carry bit shifted for the next
adder.
Design structure of the Wallace tree is shown below, each stage of addition gives one
bit of multiplied product, initial partial product adder bits are fed to the full adders as a
inputs, and full adders are cascaded between each.
Figure 3.12 Operation of Wallace Tree multiplier

ii. Array multiplier
Array Multiplier is a regular structure design. The design structure is almost similar as
previously explained multiplier, here each stage of full adder consist of individual AND
gates, which is input to the adders. A structural diagram of a 4×4 array multiplier is shown in
Figure. Each partial product is generated by the multiplication of two input binary bits. The
intermediate products are shifted according to their bit orders and then added. In array
multiplication there a compulsion to add as many intermediate products as there are
multiplier bits.
Figure 3.13 Basic operation of Array multiplier
iii. Braun multiplier
In the year of 1963 Braun Edward Louis first proposed Braun multiplier; it is also
called as carry array multiplier because it is a simple parallel multiplier. It performs unsigned
numbers and which is only restricted to that. AND gates and adders are arranged in an
iterative structure, does not requirement of logic registers. It does not add any additional
operand to the multiplication result so it is called as non-additive multiplier. For a*b

multiplier, requires a*b number of AND gates, b number of half adders, (a-2)*n number of
full adders. For example 4*4 multiplier 16 AND gates, 4 half adders, 8 full adders are
required. The 4*4 Braun multiplier figure is shown below.
Figure 3.14 Operation of Braun multiplier
iv. Baugh Wooleymultiplier
Baugh Wooley Multiplier is used for computation of 2’s complement multiplication.
For maximizing the regularity of each multiplication array, it adjusts the partial products.
Rather than subtracting partial products, it adds negation to negative numbers and it moves
partial products at the last steps. This technique, suites for 2’s complements numbers, in order
to design regular multipliers it had been developed. Get the 2’s complements of last two
terms and add all to get final result instead of subtracting operation. 4*4 Baugh Wooley
multiplier design is shown below with a0-a3, b0-b3 inputs and p0-p7 outputs.

Figure 3.15 Operation of Baugh Wooley multiplier
CHAPTER 4

SOFTWARE REQUIREMENTS
All the full adder circuits and newly designed multipliers are executed on the
Mentor Graphics tool. Mentor Graphics is an EDA (Electronic Design Automation) tool,
which is used to design electronic systems such as chip layout; PCBs. Mentor Graphics
Company established on the concept of computer aided designs for electronics in the year
1981.
Mentor Graphics custom IC consisting following features,
 Pyxis Schematic
 Pyxis layout
 Pyxis Schematic
Pyxis schematic, where electronics circuits such as both Analog circuits and
Digital circuits can be drawn with the help of available library files. Here the group of
adders are executed and analysed the result. After designing circuit on the tool, should
run circuit using run eldo feature. Software consists of library files and all the
parameters analysing tools such as power calculators, delay analyzer.
 Pyxis layout
Pyxis layout, where the models of electronic functions are designed and they are
going to verify for various parameters. Those parameters are DRC, LVS, and PEX.
These are verified after designing layout from schematic diagram which is drawn
SDL (Schematic Driven Layout).
DRC (Direct Rule Check): This is used for the checking designs rules for designed
layouts. There are many design rules for designs MOSFET example: minimum width
of polysilicon is 2lambda. Once rules are verified designer will move further.
LVS (Layout Verses Schematic): This is to check for layout has designed same as
schematic diagram by invoking all the steps. Once these all are correct, tool results as
a smiley with right mark.
PEX (Parasitic Extraction): It will generate a PEX Netlist file which has to be used
in post layout simulation.

Figure 4.1The Mentor Graphics Custom IC flow
Above figure is the flow diagram of Custom IC in Mentor Graphics tool. First block
is the Pyxis schematic, which does the interaction analysis such as placing components, edit,
run eldo, view waves, netlist, ACII files etc. From the schematic, layout can be drawn hence
it is schematic driven layout (SDL). After designing layout, design need to check the design
rules that is DRC, LVS is layout verses schematic, and PEX parasitic extraction.
CHAPTER 5
RESULTS

5.1 FULL ADDER RESULT
All ten full adders GDI_XOR full adder, GDI_XNOR full adder, full adder 9TA,
full adder 9TB, 8T full adder, CLRCL, SERF, 9T full adder, 6T full adder type I, 6T full
adder type II are simulated on Pyxis schematic of Mentor Graphics tool with 180nm
technology and 1.8V supply voltage.
Figure 5.1 Schematic design of 8T full adder
Above figure is the schematic representation of full adder using 8transistors. This
adder is constructed using 3T XOR logic. The W/L ratio of transistors M1-M8 are 180nm.
The delay is obtained by summing Sum and Cout delay, and also voltage drop is due to
threshold drop in M3 and M6. This can be reduced when a=0, b=0 then nMOS pass transistor
M8 will turn on hence obtain the output |VT, p| -VT, n. similarly, the threshold drop of the
transistors M7 and M8 can be reduced by suitably increasing in the aspect ratios of M7 and
M8 transistors.

Figure 5.2 Symbolic diagram of 8Tfull adder
Above figure represents the symbolic diagram of 8T full adder, which is instanced
from schematic design of same 8T full adder. This diagram says that full adder schematic is
combined in one functional box. Simulation is carried out by giving input bits to all input
ports, and observes respective outputs. Observed output parameters are noted.

Figure 5.3 Output waveform of 8Tfull adder
Figure 5.4 Time delay observation of 8Tfull adder

Figure 5.5 Average power consumption observation of 8Tfull adder
Above figure represents the Average power consumption of the 8T full adder.
Power consumption is calculated using wave calculator from current and voltage wave form
of each output (sum, carry). Figure 5.5 is a time delay observation of 8T full adder, which has
observed from delay calculation option in the tool. Power dissipation is extracted from the
netlist after simulating the design.
Like the method mentioned above time delay, power dissipation and power
consumption observation, rest of the nine full adders are designed as the same way of 8T full
adder and observed the results and noted down.

Figure 5.6 Schematic of GDI_XOR full adder
Above figure is the schematic representation of full adder using GDI_XOR
technique. In GDI, there is a possibility of giving three inputs for each terminal of MOSFET;
this advantage can be used based on application. So those concepts has applied here and
observed the output parameters in terms of time delay, power dissipation, power delay
product (PDP) and power consumption.
Symbolic diagram is generated after designing schematic diagram and then
appending inputs to the input ports, simulated and observed the results with respect to the
inputs.

Figure 5.7 Schematic of 9T full adder
Above figure represents the schematic design of full adder using 9tansistors, from
this schematic symbolic diagram generated. Then feeding inputs to the input ports, all
combinations three bit inputs of adders (000 to 111) to input ports and observe the output and
corresponding parameters.
Figure 5.8 Schematic of CLRCL full adder

Figure 5.9 Schematic of SERF full adder
Figure 5.10 Schematic of 9TA full adder

Figure 5.11 Schematic of 9TB full adder
Figure 5.12 Schematic of 6T type I full adder

Figure 5.13 Schematic of 6T type II full adder
Figure 5.14 Schematic of GDI_XNOR full adder

Table 5.1 Comparison of different full adders
Types of full
adder Delay (ns)
Power
dissipation
(nW)
PDP
(W-sec)
(10-15)
Power
consumption(mW)
8Transistor 150.1527 0.0325798 0.0048919 14.6504
GDI_XOR 347.29 294232.9 102184 38.5163
9T A 298.494 90747.6 27087.6 3.8159
9T B 298.517019 88855.9 26525 3.8003
SERF 297.75375 88855.9 26457 3.8051
GDI_XNOR 248.208 90747.6 22524 3.7561
9T 220.57968 0.0333791 0.0073628 16.843
CLRCL 299.66322 88856 26627 6.09307
6T Type I 251.63314 0.0260638 0.0065585 8.8676
6T Type II 200.055779 0.0755058 0.015105 9.5348
Above table represents the performance parameters of all designed and simulated
full adders using 180nm technology. It contains the list of delay, power dissipation, power
delay product (PDP) and power consumption of each full adder. According to the work flow
of observation, designed for 8transistor full adder exhibits less time delay, lower power
dissipation and of course low PDP. But it can be noted that high speed, less power dissipated
8T full adder consumes more power. The GDI_XNOR full adder consumes low power.
Hence this analysis can say that 8transistor full adder showed high speed, low power and
PDP, also more power consumption. In VLSI designs mainly concerned about speed of the
design, so compromising with power consumption, we can conclude that 8transistor full
adder is the viable option for high preformed full adder, further using this full adder, high
level design structures.

Figure 5.15 Comparative chart of delay in Full adders
Above bar chart represents the time delay of each full adder in ns. It can be observed that
8transistor full adder is the high speed adder compared to all other full adders.
Figure 5.16 Comparative chart of power dissipation in Full adders
Above bar chart shows the power dissipation of every full adder, and it can be
observed 8T full adder dissipates less power.
0
50
100
150
200
250
300
350
400
Delay(ns)
0
50000
100000
150000
200000
250000
300000
350000
Powerdissipation(nW)

Above bar chart shows the power delay product in every full adder, it can be
observed that 8T full adder has low power delay product.
Above bar chart represents the power consumption in all ten full adders, it can be
observed that, 8T full adder consumes more power.
0
20000
40000
60000
80000
100000
120000
PDP(W-Sec)*10-15
0
5
10
15
20
25
30
35
40
45
Powerconsumption(mW)

4.2 MULTIPLIER RESULT
Figure 5.19 Schematic of Array Multiplier
Figure 5.19 shows the schematic design of the Array multiplier, which consists of 14
AND gates, 8 full adders and 4 half adders. The high performance 8T full adder is use to
construct multiplier. AND gates, half adders are designed using basic CMOS logic. All
designed structures are instanced from schematic and arranged in a respective logic to get
multiplier result. After designing multiplier design, constructed the symbolic diagram, by
feeding inputs to the each input ports and observe the results respectively.

Figure 5.20 Schematic of Baugh Wooley Multiplier
Above schematic design is the Baugh Wooley multiplier, which consists of 16 AND
gates, 15 full adders and 8 inverters. The high performance 8T full adder is used here to
construct multiplier. AND gates, inverters are designed using basic CMOS logic. All
designed structures are instanced and arranged in respective logic to get a multiplier result.
After designing multiplier design, constructed the symbolic diagram, for symbolic diagram
by feeding inputs to the each input ports observed the results respectively.

Figure 5.21 Schematic of Braun Multiplier
Above schematic design is the Braun multiplier, which consists of 16 AND gates, 12
full adders. The high performance 8T full adder is used here to construct multiplier. AND
gates are designed using basic CMOS logic. All designed structures are instanced and
arranged in respective logic to get a multiplier result. After designing multiplier design
constructed the symbolic diagram, by feeding inputs to the symbolic diagram to each input
ports observed the results respectively.

Figure 5.22 Schematic of Wallace Tree Multiplier
Above schematic design is the Wallace Tree multiplier, which consists of 16 AND
gates, 10 full adders and 2 half adders. The high performance 8T full adder is used here to
construct multiplier. AND gates, half adders are designed using basic CMOS logic. All
designed structures are instanced and arranged in respective logic to get a multiplier result.
After designing multiplier design constructed the symbolic diagram, by feeding inputs to the
each input ports and observed the results respectively.

Table 5.2 Comparison of different Multipliers
Types of multipliers Delay (ns) Power dissipation
(mW)
PDP (W-sec)
(10-12)
Wallace Tree 2.83792 4.2414 12.03675
Baugh Wooley 3.0429582 3.0351 9.235682
Braun 6.268 3.0537 19.14059
Array 5.341614 5.5911 29.86549
Figure 5.23 Pie Diagram of Delay in Multipliers
Above Pie diagram is representation of Delay in multipliers, here it explains the time
delay performance of each multiplier. Less visible area is the high speed performance that is
Wallace Tree multiplier and more area occupied multiplier is Braun multiplier, which is low
speed multiplier.
Delay (ns)
Wallace Tree
Baugh Wooley
Braun
Array

Figure 5.24 Pie Diagram of Power dissipation in Multipliers
Above Pie diagram is the representation of Power dissipation in multipliers, here it
explains power dissipation performance of each multiplier. Less visible area is low power
dissipation performance of Baugh Wooley multiplier and more area occupied multiplier is
Array multiplier, which is high power dissipated multiplier.
Figure 5.25 Pie Diagram of PDP in Multipliers
Power dissipation (mW)
Wallace Tree
Baugh Wooley
Braun
Array
PDP(W-sec)
(10-12 )
Wallace Tree
Baugh Wooley
Braun
Array

Figure 5.25 shows the Pie diagram representation of Power delay product (PDP) in
multipliers, here it explains about PDP performance of each multiplier. Less visible area is
the low PDP performance that is Baugh Wooley multiplier and more area occupied multiplier
is the Array multiplier, which is high PDP multiplier.
Observing the results of multipliers, this project work says that Wallace Tree
Multiplier is the high speed multiplier but dissipates comparatively high power. Baugh
Wooley multiplier dissipates less power but more time delay in driving results, and it has low
PDP also.

CHAPTER 6
ADVANTAGES AND DISADVANTAGES
6.1 ADVANTAGES
 From this project work, the high performance full adder, which is used for designing
efficient VLSI designs.
 In full adder loss of power is less, so it gives more accurate voltage power.
 Full adder using multiplier also exhibited less power loss and more speed, which leads
to efficient designs.
6.2 DISADVANTAGES
 This project concentrates only on speed and power of the adder and multiplier
designs.
 Other parameters such as leakage current, voltage, area on chip also confirms the
performance of the designs.
6.3 FUTURE WORK
High performance 8T full adder is implemented in designing a different multipliers,
among these multipliers which is high speed and less power dissipates multiplier can be used
in MCA (multiply and accumulate) construction, digital FIR filters. 8T full adder can be used
for constructing parallel adder, carry save adder, look ahead adder and so on.

CONCLUSION
In this project work a group of ten full adders of different designs are simulated
and analyzed the performance parameters, in terms of delay, power dissipation, PDP and
power consumption. Full adders are designed and simulated on the Mentor Graphics tool with
an 180nm technology by constant W/L ratio for all full adder and all eight combinations are
given as inputs. From the analysis found that best efficient full adder as a 8T full adder,
which is less in delay, low power dissipation, PDP, but high power consumption. Hence we
can conclude that 8T full adder is viable efficient adder for multiplier and high level designs.
Using 8T full adder, constructed a different four types of digital multipliers, and is analyzed
performance parameters in terms of delay, power consumption, and PDP. Thus found a less
delay in Wallace Tree multiplier, less power dissipation and PDP in Baugh Wooley
multiplier.

ABSTRACT
Adders are the fundamental building blocks for any digital processors and VLSI
designs. The speed of the higher level designs depends on the speed of the full adders. So the
efficient design of the full adder is the major concern. This project presents the comparative
analysis of power, delay and power delay product (PDP) of different Full adder circuit
designs. Here group of different full adders structures are considered. Performance
parameters in terms of power and delay are analyzed, for special full adders also like CLRCL
(complementary and level restoring carry logic), SERF adder (static energy recovery full
adder), and GDI_XOR full adder. All adder designs are simulated in Mentor Graphics tool
with 180nm technology. Among the simulated full adders 8Transistor XOR based full adder
is the high performed adder cell, which is the option for an efficient VLSI design.
As a result, 8T full adder is a viable efficient adder. This is used in designing
multipliers, such as Wallace Tree multiplier, Braun multiplier, Baugh Wooley multiplier and
Array multiplier. Designed multipliers are simulated and resulted in high speed Wallace Tree
multiplier and low power dissipation, PDP in Baugh Wooley multiplier.

Ramya Project

More Related Content

What's hot

Similar to Ramya Project

Ramya Project