This document is a resume for Ramesh Kumar Bankapalli summarizing his objective, qualifications, skills and projects. He has a PG Diploma in ASIC Design from RV-VLSI Design Center and an M.Tech in VLSI. He has experience with synthesis tools like PrimeTime and design tools like IC Compiler. His projects include block level physical design of a torpedo subsystem and static timing analysis using 180nm technology.

1. RAMESH KUMAR BANKAPALLI
E-mail: ramesh.bankapalli@gmail.com
Contact no: +91 9493234238.
CAREER OBJECTIVE
Looking for an opportunity to work as a physical design engineer in a dynamic work environment.
CERTIFICATION
I done my certification on physical design domain from RV-VLSI.
CORE COMPETENCY
 Good understanding of Physical design flow-Floor Planning, Placement, CTS, Routing, Physical
Verification & DFM.
 Good knowledge in understanding and resolving timing violations of various timing paths (STA).
 Comprehensive knowledge of ASIC Flow, Fundamentals of Transistors, Circuit theory and Digital
Design concepts.
 Good exposure to industry standard tools, has undergone additional training by industry experts on VLSI
Design.
 Good working knowledge of Linux and C programming.
 Familiar with scripting languages.
EDUCATIONAL QUALIFICATIONS
Degree Discipline
Year of
passing
Educational Institution Aggregate
PG Diploma
Advanced Diploma in
ASIC Design
2015 RV-VLSI Design Center 7.00
M. Tech VLSI 2013
MVGR College of
Engineering,Vizianagaram.
72.42
B. Tech
Electronics and
Communication
Engineering
2010
Newton’s Institute of
Engineering, Guntur.
67.56
Intermediate MPC 2006
Narayana Junior College,
Vishakhapatnam.
85.30
SSC(10th
) SSC 2004
Suresh Residential School,
Parvathipuram.
75.50
TECHNICAL SKILLS
 Synthesis Tools : Prime Time
 Design Tools : IC Compiler (Synopsys)
 Operating System : Linux, Windows 98/XP/Professional/2007
 Packages : MS-Office
ACHIEVEMENTS
 Attended a “WORKSHOP ON VLSI DESIGN USING MENTOR GRAPHICS TOOLS” at
MVGR College of Engineering, Vizianagaram on 3rd
& 4th
January 2013.
 Attended a Two-Day National Level “WORKSHOP ON LATEST TECHNOLOGIES IN
ELECTRONICS COMMUNICATIONS (WOLTEC-11)” at MVGR College of Engineering,
Vizianagaram on 22nd
& 23rd
December 2011.

2. PROJECT DETAILS
PROJECT NAME BLOCK LEVEL PHYSICAL DESIGN OF TORPEDO SUB-SYSTEM.
ORGANIZATION RV-VLSI Design Center.
DESCRIPTION Worked on Torpedo sub block includes 32 macros, 43275 standard cells
with supply voltage of 1.8v, working at operating frequency of 400MHz It
has total 5 clocks (3 propagated, 2 generated), 6 metal layers are used.
TOOLS USED Synopsys IC compiler, Prime Time, Hercules.
CHALLENGES Placement of macros during Floor plan, deciding number of power straps
to meet IR drop (VDD+VSS) budget, Fixing floating Pin and floating
shape errors, controlling congestion at each point of flow, analyzing
timing reports
PROJECT NAME STATIC TIMING ANALYSIS FOR ALL THE TIMING PATHS USING
180nm TECHNOLOGY NODE.
ORGANIZATION RV-VLSI Design Center.
DESCRIPTION Analysis of timing reports for provided net lists for MCMM, OCV,
Signal Integrity and Timing Closure for the Timing paths.
TOOLS USED Synopsys - Prime Time.
CHALLENGES Understanding setup & hold violations by analyzing timing paths for
Input-Reg, Reg-Reg, Reg-Output and Input - Output. Analyzed multi cycle
paths & false paths exceptions. Understanding Time Borrow concept with
latch based timing analysis.
PROJECT NAME ANALYZING TCL SCRIPTS.
ORGANIZATION RV-VLSI Design Center.
DESCRIPTION Analyzing TCL scripts for the given templates of Floor plan, placement,
CTS, routing, DFM.
TOOLS USED TCLsh, Perl, IC Compiler.
CHALLENGES Learning TCL from basics and understanding already written scripts
with the help of MAN pages.
PROJECT NAME DESIGN AND SIMULATION OF 64-POINT FFT USING RADIX-4
ALGORITHM.
ORGANIZATION MVGR College of Engineering.
DESCRIPTION Implementation of parallel and pipelined FFT algorithm by designing a
64 bit FFT processor for wide band signal transmission.
TOOLS USED Xilinx ISE 11.1, Model SIM 6.5
CHALLENGES FFT computes the DFT and produces exactly the same result as evaluating
the DFT definition directly and using radix 4 reduce the number of stages,
less voltage, number of complex additions and complex multiplications
compared to radix 2 butterfly.
PROJECT NAME BUILDING A REMOTE SUPERVISIONARY CONTROL.
ORGANIZATION Newton’s Institute of Engineering
DESCRIPTION Project demonstrate the application of the zigbee wireless protocol in
Controlling of home appliances with the help of Micro controller.
TOOLS USED Microcontroller, LCD, Power supply, ZIGBEE, KEIL Compiler.
CHALLENGES By using zigbee we can control the home devices (fan, light, AC, etc.,)
with wireless. In this project a user interface is designed in C / VB
which gives a clear graphical interaction to the user.