Power System Simulation: History, State of the Art, and ChallengesLuigi Vanfretti
This talk will give an overview of power system simulation technology through several decades, aiming to provide an understanding of the modeling philosophy and approach that has lead to the state of the art in (domain specific) power system simulation tools. This historical perspective will contrast the de facto proprietary software development method used by the power engineering community, against the open source development model. Aspects of resistance to change particular to the power system engineering community will be highlighted.
Given this particular context, power system simulation faces enormous challenges to adapt in order to satisfy simulation needs of both cyber-physical and sustainable system challenges. Such challenges will be highlighted during the talk.
There is, however, an opportunity for disruptive change in power system simulation technology emerging for the EU Smart Grid Mandate M/490, which requires "a set of consistent standards, which will support the information exchange (communication protocols and data models) and the integration of all users into the electric system operation." These regulatory aspects will be explained to highlight the importance of collaboration between the power system domain and computer system experts.
Open modeling and simulation standards may have a large role to play in the development of the European Smart Grid which will have to overcome challenges related to the design, operation and control of cyber-physical and sustainable electrical energy systems. To contribute to this role, the KTH SmarTS Lab research group has been applying the standardized Modelica language and the FMI standard for model exchange in order to couple the domain specific data exchange model (CIM) with the powerful and modern simulation technologies developed by the Modelica community. These efforts will be also discussed.
Most importantly one can identify locations of inputs and outputs of the portions of a model and specify the operating conditions about which the model is linearized for further analysis. Other important feature of Simulink is a Linear-Quadratic-Gaussian LQG control technique which is used to design optimal dynamic regulators, Kalman estimators and filters.
MODELLING ANALYSIS & DESIGN OF DSP BASED NOVEL SPEED SENSORLESS VECTOR CONTRO...IAEME Publication
Unscented Kalman Filter (UKF), which is an update d version of EKF, is proposed as a state estimator for speed sensorless field oriented contr ol of induction motors. UKF state update computations, different from EKF, are derivative fr ee and they do not involve costly calculation of Jacobian matrices. Moreover, variance of each state is not assumed Gaussian, therefore a more realistic approach is provided by UKF. In order to examine the rotor speed (state V) estimation performance of UKF experimentally under varying spe ed conditions, a trapezoidal speed reference command is embedded into the DSP code. EKF rotor speed estimation successfully tracks the trapezoidal path. It has been observed that the est imated states are quite close to the measured ones. The magnitude of the rotor flux justifies that the estimated dq components of the rotor flux are estimated accurately. A number of simulations were carried out to verify the performance of the speed estimation with UKF. These simulated results are confirmed with the experimental results. While obtaining the experimental results, the real time stator voltages and currents are processed in Matlab with the associated EKF and UKF programs.
Binding CIM and Modelica for Consistent Power System Dynamic Model Exchange a...Luigi Vanfretti
Poster Presentation at the IEEE PES General Meeting.
The Common Information Model (CIM) is considered the most prominent data model for power systems information exchange between Transmission System Operators (TSO), facilitating coordination of TSO for steady-state operation. However, information exchange should also consider power systems dynamic models required to perform dynamic simulations so to coordinate TSOs operations under emergency conditions. This work describes the design and implementation of a mapping between CIM and Modelica. The Modelica models provide a strict mathematical representation of power system dynamic models using a standardized modeling language. The proposed solution combines both modeling languages, thus providing a CIM-compliant unambiguous power system model exchange and simulation solution considering both steady-state and dynamic models.
Power System Simulation: History, State of the Art, and ChallengesLuigi Vanfretti
This talk will give an overview of power system simulation technology through several decades, aiming to provide an understanding of the modeling philosophy and approach that has lead to the state of the art in (domain specific) power system simulation tools. This historical perspective will contrast the de facto proprietary software development method used by the power engineering community, against the open source development model. Aspects of resistance to change particular to the power system engineering community will be highlighted.
Given this particular context, power system simulation faces enormous challenges to adapt in order to satisfy simulation needs of both cyber-physical and sustainable system challenges. Such challenges will be highlighted during the talk.
There is, however, an opportunity for disruptive change in power system simulation technology emerging for the EU Smart Grid Mandate M/490, which requires "a set of consistent standards, which will support the information exchange (communication protocols and data models) and the integration of all users into the electric system operation." These regulatory aspects will be explained to highlight the importance of collaboration between the power system domain and computer system experts.
Open modeling and simulation standards may have a large role to play in the development of the European Smart Grid which will have to overcome challenges related to the design, operation and control of cyber-physical and sustainable electrical energy systems. To contribute to this role, the KTH SmarTS Lab research group has been applying the standardized Modelica language and the FMI standard for model exchange in order to couple the domain specific data exchange model (CIM) with the powerful and modern simulation technologies developed by the Modelica community. These efforts will be also discussed.
Most importantly one can identify locations of inputs and outputs of the portions of a model and specify the operating conditions about which the model is linearized for further analysis. Other important feature of Simulink is a Linear-Quadratic-Gaussian LQG control technique which is used to design optimal dynamic regulators, Kalman estimators and filters.
MODELLING ANALYSIS & DESIGN OF DSP BASED NOVEL SPEED SENSORLESS VECTOR CONTRO...IAEME Publication
Unscented Kalman Filter (UKF), which is an update d version of EKF, is proposed as a state estimator for speed sensorless field oriented contr ol of induction motors. UKF state update computations, different from EKF, are derivative fr ee and they do not involve costly calculation of Jacobian matrices. Moreover, variance of each state is not assumed Gaussian, therefore a more realistic approach is provided by UKF. In order to examine the rotor speed (state V) estimation performance of UKF experimentally under varying spe ed conditions, a trapezoidal speed reference command is embedded into the DSP code. EKF rotor speed estimation successfully tracks the trapezoidal path. It has been observed that the est imated states are quite close to the measured ones. The magnitude of the rotor flux justifies that the estimated dq components of the rotor flux are estimated accurately. A number of simulations were carried out to verify the performance of the speed estimation with UKF. These simulated results are confirmed with the experimental results. While obtaining the experimental results, the real time stator voltages and currents are processed in Matlab with the associated EKF and UKF programs.
Binding CIM and Modelica for Consistent Power System Dynamic Model Exchange a...Luigi Vanfretti
Poster Presentation at the IEEE PES General Meeting.
The Common Information Model (CIM) is considered the most prominent data model for power systems information exchange between Transmission System Operators (TSO), facilitating coordination of TSO for steady-state operation. However, information exchange should also consider power systems dynamic models required to perform dynamic simulations so to coordinate TSOs operations under emergency conditions. This work describes the design and implementation of a mapping between CIM and Modelica. The Modelica models provide a strict mathematical representation of power system dynamic models using a standardized modeling language. The proposed solution combines both modeling languages, thus providing a CIM-compliant unambiguous power system model exchange and simulation solution considering both steady-state and dynamic models.
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
Multiplications and additions are most widely and more often used arithmetic computations performed in
all digital signal processing applications. Addition is the basic operation for many digital application. The
aim is to develop area efficient, high speed and low power devices. Accurate operation of a digital system
is mainly influenced by the performance of the adders. Multipliers are also very important component in
digital systems
This paper presents a recursive designing approach for high energy efficient carry select adder (CSA). Nowadays, the portable equipment’s like mobile phones and laptops have higher demands in the market. So, the designers must focus greater attention while designing such devices. Which means that have the devices must have lesser power consumption, low cost and have a better performance. The customers mainly focus on the equipment’s which have lesser power consumption, low cost and better performance. As we all know that the adders are the basic building block of microprocessors. The performance of the adders greatly influences the performance of those processors. The carry select adder is most suitable among other adders which have fast addition operation at low cost. The carry select adder (CSA) consists of chain full adders (FAs) and multiplexers. Here a carry select adder is designed with four FAs and four multiplexers. The proposed structure is assessed by the power consumption of the carry select adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that the carry select adder has low power consumption.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...IAEME Publication
CPUs in general-purpose personal computers, such as desktops and laptops, dissipate significantly more power in the order of few watts because of their higher complexity and speed. ALU is a fundamental building block of CPU. It does all process related to arithmetic and logic operations. As the operations become more complex, the ALU become more complex, more expensive, takes up more space in the CPU and contributes more power dissipation within the CPU. Hence power consumption of ALU is a major issue in the designing of CPU.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
Performance analysis of adaptive beamforming at receiver side by using lms an...Ijrdt Journal
The Least Mean Squares (LMS) algorithm is an important member of the family of stochastic gradient algorithms. A significant feature of the LMS algorithm is its simplicity. The recursive least squares (RLS) algorithm recursively finds the filter coefficients for minimizing linear least squares cost function. Smart antenna generally refers to any antenna array. Beamforming is a signal processing technique used in sensor arrays for directional signal transmission or reception. This spatial selectivity is achieved by using adaptive or fixed receive/transmit beam patterns. The improvement compared with an omnidirectional reception/transmission is known as the receive/transmit gain (or loss). In this study, fixed weight beamforming basics and maximum signal to interference ratio are given. The theoretical information of adaptive beamforming, LMS (Least Mean Square) and RLS (Recursive Mean Squares) algorithms are explained. Adaptive beamforming in recieve antenna is simulated by using LMS and RLS algorithms. Simulation results are discussed and explained.
Wanted!: Open M&S Standards and Technologies for the Smart Grid - Introducing...Luigi Vanfretti
Title:
Wanted! - Open M&S Standards and Technologies for the Smart Grid
Subtitle:
Introducing the Open Source iTesla Power Systems Modelica Library and the RaPId Toolbox for Model Identification and Validation
Abstract:
Modeling and Simulation (M&S) technologies have a broad set of applications in power systems, from infrastructure planning, through real-time testing of components, and even for training operators to use decision support systems. However, power system M&S technologies face a great challenge to meet when designing, testing, operating and controlling cyber-physical and sustainable electrical energy systems and components, a.k.a “Smart Grids”.
The speaker claims that open M&S standards can have a large role to play in the development of Smart Grids. This claim will be justified with three examples.
The first example describes the experience gained during the EU FP7 iTesla project where the iTesla Power Systems Modelica Library (iPSL) was designed using the Modelica language. The Modelica language, being standardized and equation-based, has proven valuable for the project for model exchange, and even simulation of actual power networks.
Within the iTesla project, the KTH SmarTS Lab research group has been also applying the FMI standard for model exchange in order to develop a software prototype called RaPId. The RaPId Toolbox aims to provide a “virtual laboratory” to solve parameter identification and model validation problems for any kind of model represented in an FMU, but specifically, for power systems.
The third example comes from a collaboration with Xogeny. It will be shown how it is possible to exploit the FMI to decouple the model from the simulator tool, and thus, exploit the model in unforeseen ways. This shows that is possible develop customized and stand-alone analysis tools using web technologies, giving analyst more time for “analysis”. This approach has an enormous potential for typical analysis applications, but even more, for education.
Design and Implementation of 16-bit Arithmetic Logic Unit using Quantum dot C...IJERA Editor
Quantum Dot Cellular Automata (QCA) is an advanced nanotechnology that attempts to create general computational at the nano-scale by controlling the position of single electrons. Quantum dot cellular automata (QCA) defines a new device architecture that permits the innovative design of digital systems. QCA technology has large potential in terms of high space density and power dissipation with the development of the faster computer with smaller size & low power consumption.QCA help us to overcome the limitations of CMOS technology. In this paper, A design 16-bit arithmetic logic unit (ALU) based on the Quantum dot cellular automata (QCA) is presented. The simulation result of 16 bit ALU is verified using QCA Designer tool.
Deep segmentation of the liver and the hepatic tumors from abdomen tomography...IJECEIAES
A pipelined framework is proposed for accurate, automated, simultaneous segmentation of the liver as well as the hepatic tumors from computed tomography (CT) images. The introduced framework composed of three pipelined levels. First, two different transfers deep convolutional neural networks (CNN) are applied to get high-level compact features of CT images. Second, a pixel-wise classifier is used to obtain two outputclassified maps for each CNN model. Finally, a fusion neural network (FNN) is used to integrate the two maps. Experimentations performed on the MICCAI’2017 database of the liver tumor segmentation (LITS) challenge, result in a dice similarity coefficient (DSC) of 93.5% for the segmentation of the liver and of 74.40% for the segmentation of the lesion, using a 5-fold cross-validation scheme. Comparative results with the state-of-the-art techniques on the same data show the competing performance of the proposed framework for simultaneous liver and tumor segmentation.
In power engineering the power flow analysis (also known as load flow study) is an important tool involving numerical analysis applied to a powe r system. This project deals with a model of existing power system using the actual data taking care of all parameters required for the simulation and analysis. With the help of Maharasht ra State Electricity Transmission co. Ltd.,a model of 220KV lines,of Solapur District grid usin g MATLAB software will be modeled. In this project,an algorithm will be used for power f low study and data collection and coding required for modeling. Load flow studies will be ca rried out using Newton Raphson method and voltage profile of buses will be analyzed. New meth od for the improvement of voltage profile will be suggested and analyze using the developed m odel. The optimization techniques include power factor compensation,tap changing,up gradati on of substation,up gradation of line and load shifting will be analyzed. Importance of power flow or Load flow studies is in planning future expansion of power system as well as determi ning the best operation of existing systems. From results of simulation buses with low voltage p rofile will be identified and possible solutions can be suggested.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Comparative analysis of FACTS controllers by tuning employing GA and PSOINFOGAIN PUBLICATION
Stability exploration has drawn more attention in contemporary research for huge interconnected power system. It is a complex frame to describe the behaviour of system, hence it can create an overhead for modern computer to analyse the power system stability. The preliminary design and optimization can be achieved by low order liner model. In this paper, the design problems of SMIB-GPSS and SMIB-MBPSS are considered to compare the performance of PSO and GA optimization algorithms. The performance of both optimization techniques are then compared further. Simulation results are presented to demonstrate the effectiveness of the proposed approach to improve the power system stability
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
Multiplications and additions are most widely and more often used arithmetic computations performed in
all digital signal processing applications. Addition is the basic operation for many digital application. The
aim is to develop area efficient, high speed and low power devices. Accurate operation of a digital system
is mainly influenced by the performance of the adders. Multipliers are also very important component in
digital systems
This paper presents a recursive designing approach for high energy efficient carry select adder (CSA). Nowadays, the portable equipment’s like mobile phones and laptops have higher demands in the market. So, the designers must focus greater attention while designing such devices. Which means that have the devices must have lesser power consumption, low cost and have a better performance. The customers mainly focus on the equipment’s which have lesser power consumption, low cost and better performance. As we all know that the adders are the basic building block of microprocessors. The performance of the adders greatly influences the performance of those processors. The carry select adder is most suitable among other adders which have fast addition operation at low cost. The carry select adder (CSA) consists of chain full adders (FAs) and multiplexers. Here a carry select adder is designed with four FAs and four multiplexers. The proposed structure is assessed by the power consumption of the carry select adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that the carry select adder has low power consumption.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...IAEME Publication
CPUs in general-purpose personal computers, such as desktops and laptops, dissipate significantly more power in the order of few watts because of their higher complexity and speed. ALU is a fundamental building block of CPU. It does all process related to arithmetic and logic operations. As the operations become more complex, the ALU become more complex, more expensive, takes up more space in the CPU and contributes more power dissipation within the CPU. Hence power consumption of ALU is a major issue in the designing of CPU.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
Performance analysis of adaptive beamforming at receiver side by using lms an...Ijrdt Journal
The Least Mean Squares (LMS) algorithm is an important member of the family of stochastic gradient algorithms. A significant feature of the LMS algorithm is its simplicity. The recursive least squares (RLS) algorithm recursively finds the filter coefficients for minimizing linear least squares cost function. Smart antenna generally refers to any antenna array. Beamforming is a signal processing technique used in sensor arrays for directional signal transmission or reception. This spatial selectivity is achieved by using adaptive or fixed receive/transmit beam patterns. The improvement compared with an omnidirectional reception/transmission is known as the receive/transmit gain (or loss). In this study, fixed weight beamforming basics and maximum signal to interference ratio are given. The theoretical information of adaptive beamforming, LMS (Least Mean Square) and RLS (Recursive Mean Squares) algorithms are explained. Adaptive beamforming in recieve antenna is simulated by using LMS and RLS algorithms. Simulation results are discussed and explained.
Wanted!: Open M&S Standards and Technologies for the Smart Grid - Introducing...Luigi Vanfretti
Title:
Wanted! - Open M&S Standards and Technologies for the Smart Grid
Subtitle:
Introducing the Open Source iTesla Power Systems Modelica Library and the RaPId Toolbox for Model Identification and Validation
Abstract:
Modeling and Simulation (M&S) technologies have a broad set of applications in power systems, from infrastructure planning, through real-time testing of components, and even for training operators to use decision support systems. However, power system M&S technologies face a great challenge to meet when designing, testing, operating and controlling cyber-physical and sustainable electrical energy systems and components, a.k.a “Smart Grids”.
The speaker claims that open M&S standards can have a large role to play in the development of Smart Grids. This claim will be justified with three examples.
The first example describes the experience gained during the EU FP7 iTesla project where the iTesla Power Systems Modelica Library (iPSL) was designed using the Modelica language. The Modelica language, being standardized and equation-based, has proven valuable for the project for model exchange, and even simulation of actual power networks.
Within the iTesla project, the KTH SmarTS Lab research group has been also applying the FMI standard for model exchange in order to develop a software prototype called RaPId. The RaPId Toolbox aims to provide a “virtual laboratory” to solve parameter identification and model validation problems for any kind of model represented in an FMU, but specifically, for power systems.
The third example comes from a collaboration with Xogeny. It will be shown how it is possible to exploit the FMI to decouple the model from the simulator tool, and thus, exploit the model in unforeseen ways. This shows that is possible develop customized and stand-alone analysis tools using web technologies, giving analyst more time for “analysis”. This approach has an enormous potential for typical analysis applications, but even more, for education.
Design and Implementation of 16-bit Arithmetic Logic Unit using Quantum dot C...IJERA Editor
Quantum Dot Cellular Automata (QCA) is an advanced nanotechnology that attempts to create general computational at the nano-scale by controlling the position of single electrons. Quantum dot cellular automata (QCA) defines a new device architecture that permits the innovative design of digital systems. QCA technology has large potential in terms of high space density and power dissipation with the development of the faster computer with smaller size & low power consumption.QCA help us to overcome the limitations of CMOS technology. In this paper, A design 16-bit arithmetic logic unit (ALU) based on the Quantum dot cellular automata (QCA) is presented. The simulation result of 16 bit ALU is verified using QCA Designer tool.
Deep segmentation of the liver and the hepatic tumors from abdomen tomography...IJECEIAES
A pipelined framework is proposed for accurate, automated, simultaneous segmentation of the liver as well as the hepatic tumors from computed tomography (CT) images. The introduced framework composed of three pipelined levels. First, two different transfers deep convolutional neural networks (CNN) are applied to get high-level compact features of CT images. Second, a pixel-wise classifier is used to obtain two outputclassified maps for each CNN model. Finally, a fusion neural network (FNN) is used to integrate the two maps. Experimentations performed on the MICCAI’2017 database of the liver tumor segmentation (LITS) challenge, result in a dice similarity coefficient (DSC) of 93.5% for the segmentation of the liver and of 74.40% for the segmentation of the lesion, using a 5-fold cross-validation scheme. Comparative results with the state-of-the-art techniques on the same data show the competing performance of the proposed framework for simultaneous liver and tumor segmentation.
In power engineering the power flow analysis (also known as load flow study) is an important tool involving numerical analysis applied to a powe r system. This project deals with a model of existing power system using the actual data taking care of all parameters required for the simulation and analysis. With the help of Maharasht ra State Electricity Transmission co. Ltd.,a model of 220KV lines,of Solapur District grid usin g MATLAB software will be modeled. In this project,an algorithm will be used for power f low study and data collection and coding required for modeling. Load flow studies will be ca rried out using Newton Raphson method and voltage profile of buses will be analyzed. New meth od for the improvement of voltage profile will be suggested and analyze using the developed m odel. The optimization techniques include power factor compensation,tap changing,up gradati on of substation,up gradation of line and load shifting will be analyzed. Importance of power flow or Load flow studies is in planning future expansion of power system as well as determi ning the best operation of existing systems. From results of simulation buses with low voltage p rofile will be identified and possible solutions can be suggested.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Comparative analysis of FACTS controllers by tuning employing GA and PSOINFOGAIN PUBLICATION
Stability exploration has drawn more attention in contemporary research for huge interconnected power system. It is a complex frame to describe the behaviour of system, hence it can create an overhead for modern computer to analyse the power system stability. The preliminary design and optimization can be achieved by low order liner model. In this paper, the design problems of SMIB-GPSS and SMIB-MBPSS are considered to compare the performance of PSO and GA optimization algorithms. The performance of both optimization techniques are then compared further. Simulation results are presented to demonstrate the effectiveness of the proposed approach to improve the power system stability
Impact of Electric Vehicle Integration on Gridvivatechijri
Load flow analysis is most essential and important approach to investigate problems in power system. It can provide balance steady state operation of power system without considering transients in it. This project presents a new and efficient method for solving the Load flow problem of a distribution network. By using Backward/Forward sweep method parameters like voltage profile, total power losses, load on each bus of the Distribution Network will be known. By using Load Flow load balancing of the Distribution system can be achieved. For load balancing we will use the power stored in the Electric vehicle. As Electric vehicle has large battery pack for storage. The impact of Electric Vehicle and load flow of distribution network is computer programed to implement the power flow solution scheme in MATLAB software.
Implementation of Linear Controller for a DC-DC Forward Converterijceronline
This paper discusses the controller implementation of a DC to DC Forward converter. The open loop response is obtained initially. Then the closed loop control is given in real time for the Forward converter. The MATLAB interfacing is done with the help of data acquisition card. The conventional PI controller is used for the closed loop control and the results are analyzed under MATLAB/SIMULINK environment
High Performance Layout Design of SR Flip Flop using NAND Gates IJEEE
This paper presents optimized layout of SR flip flop using NAND gates on 90nm technology. The proposed SR flip flop has been designed using different technology namely fully-automatic design and semi-custom design. In the first approach layout has been generated using fully automatic technique with the help of SR flip flop schematic. In second approach layout has been generated manually by using one finger. In the last approach semicustom layout is further optimized by using two fingers. The area and power consumption of all the designs has been compared and analyzed. It can be observed from the simulated results that SR flip flop with two fingers and SR flip flop with one finger using semicustom technique consumes (62.92% , 91.20%) and (40.04%, 80.40%) less (area, power) as compare to the SR flip flop using fully automatic technique respectively.
In the era of technological advancement, use of computer technology has become inevitable. Hence it has become the need of the hour to integrate software methods in engineering curriculum as a part to boost pedagogy techniques. Simulations software is a great help to graduates of disciplines such as electrical engineering. Since electrical engineering deals with high voltages and heavy instruments, extra care must be taken while operating with them. The viable solution would be to have appropriate control. The appropriate control could be well designed if engineers haveknowledge of kind of waveforms associated with the system. Though these waveforms can be plotted manually, but it consumes a lot of time. Hence aid of simulation helps to understand steady state of system and resulting in better performance. In this paper computer, aided teaching of transformer is carried out using MATLAB/Simulink. The test carried out on a transformer includes open circuit test and short circuit respectively. The respective parameters of the transformer are then calculated using the values obtained from the open circuit and short circuit test respectively using Simulink.
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
High efficiency push pull converter for photovoltaic applicationsEklavya Sharma
The object of this project is to design a high efficient DC-DC converter using Push-Pull topology.
A compact Dc-Dc converter with grid connection possibility and less switching losses.
An approach to Measure Transition Density of Binary Sequences for X-filling b...IJECEIAES
Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CFOA based Integrator Suitable for Analog Signal Processing by Praween K Sinha*, Mohit Kumar, Gautam Kunal Haruray and Neelam Sharma in COJ Electronics & Communications
CFOA based Integrator Suitable for Analog Signal Processing by Praween K Sinha*, Mohit Kumar, Gautam Kunal Haruray and Neelam Sharma in Crimson Publishers¬: Electronics and Communication
Current Feedback Operational Amplifier (AD844) uses a circuit design that emphasizes current-mode operation, which is inherently much faster than voltage-mode operation because it is less effected by stray node-capacitances. When fabricated using high-speed complementary bipolar processes, CFOA’s can be orders of magnitude faster than other available feedback amplifiers ex. VFA’s. With CFOAs, the amplifier gain may be controlled independently of bandwidth. All these constitutes the major advantages of CFOAs. Some new and more efficient active RC integrator circuit realizations, using minimum passive components grounded and a current feedback operational amplifier (CFOA) device are proposed. Integrator with Grounded passive components allow better usability in VLSI. Finally, experimental result by wave processing has been verified using Proteus software.
https://crimsonpublishers.com/cojec/fulltext/COJEC.000513.php
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This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from the degree of the polynomial generator. Last, we from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polynomial is given.
2. Closing the Hardware Design Loop with Multisim®: A Case Study
Abstract
Most electronics courses taught these days are planned around what is called a lecture-and-lab
environment. This environment traditionally uses lectures on subject matter and is supplemented
by laboratory experience. If the laboratory experiments are not generating the expected results,
very often the whole experiment needs to be repeated. The unexpected results could be due to
faulty components, incorrect design specifications, or improper connections. Nonetheless,
implementing a circuit in the lab with undesired output might be time consuming. However,
having an electronics simulator will enable the students as well as the instructor to analyze the
performance of a circuit prior to implementing the actual hardware components.
This paper investigates design, simulation and implementation of a decade counter using modern
computer hardware and software. This effort will focus on developing an integrated solution of a
digital electronics project that will be based on a hybrid environment in which the design and
experiments will be simulated and tested in virtual as well as with real electronics components.
Students’ outreach program in this study is to motivate students to enroll in Electronics
Engineering Technology program.
Introduction
Traditionally, many institutions world-wide supports the teaching model in which the students
learn circuit theory by participating in lectures, and acquire a deeper fundamental understanding
through complimentary experiments. The laboratory experiments presents a design challenge
that requires students to apply theory from lectures using hand calculations, create and measure
their designs, and then compare their results with the expected values [3]. However, these
laboratory experiments are costly, time-consuming, and complicated to schedule.
With the progression in computer technology several electronics laboratory simulation software
packages are available to academia and industry. The Multisim® software developed by the
Electronics Workbench and National Instruments is a popular circuit capture and simulation
software that is frequently used for education and training. With power and flexibility provided
by Multisim® students gain the advantages of an industry-caliber, easy-to-use circuit simulator.
Multisim® includes powerful virtual instruments, which are simulated instruments found in the
laboratory such as oscilloscopes, multimeters, and function generators, among many others.
These instruments provide students with a fast and intuitive method for obtaining simulation
results while preparing them for the instruments they will use in the laboratory.
Multisim® provides the integrated platform which provides an uninterrupted flow of data from
simulation to prototyping and measurement, bridging the gap between theory and hands-on
learning. This platform will allow students quick and easy access to measurements. An
integrated laboratory presents a unified platform for simulation, prototyping, measurement and
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3. comparison. With a consistent approach and the power of computer-based measurement,
students will quickly and easily understand how to implement their design, carry out powerful
simulations, and take important measurements. A conceptual view of the integrated platform is
shown in Figure 1.
Figure 1: A conceptual view of Integrated Platform
This paper explores the hardware design and software simulation of a decade counter. Design
experience included sequential design concepts, selection of components, and software
simulation with Multisim®.
Following paragraphs will describe the sequential design of a decade counter, followed by the
traditional and design implementation of the counter. The comparison of traditional and design
implementation shows that the worst case timing situation are the counting transition from state
0011 to state 0100 and from state 0111 to state 1000.
Methods (Sequential Design)
The design of a synchronous sequential circuits starts from a set of specifications and culminates
in a logic diagram or a list of Boolean functions from which a logic diagram can be obtained. In
contrast to a combinational logic, which is fully specified by a truth table, a sequential circuit
requires a state table for its specification. Steps for the design of sequential circuits are shown in
Figure 2. Page12.365.3
4. Figure 2: Steps for the Design of Sequential Circuits
A synchronous sequential circuit is made of flip-flops and combinational gates. The design of the
circuit consists of choosing the flip-flops and then finding the combinational structure which,
together with the flip-flops, produces a circuit that fulfils the required specifications. The number
of flip-flops is determined from the number of states needed in the circuit. We wish to design a
decade counter whose state diagram is shown in Figure 3.
Figure 3: State Diagram for the Decade Counter
The type of flip-flop to be used is J-K. The circuit has no inputs other than the clock pulse and no
outputs other than its internal state. The next state of the counter depends entirely on its present
state, and the state transition occurs every time the clock pulse occurs. Once the sequential
circuit is defined by the state diagram, the next step is to obtain the next-state table, which is
derived from the state diagram in figure 3 and is shown in Table 1.
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5. Table 1.0: Next State Table
Present
State
Next
State
0000 0001
0001 0010
0010 0011
0011 0100
0100 0101
0101 0110
0110 0111
0111 1000
1000 1001
1001 0000
Since there are ten states, the number of flip-flops required would be four. Now we want to
implement the counter design using JK flip-flops. Next step is to develop an excitation table
from the state table, which is shown in Table 2.
Table 2.0: Excitation Table
Present
State
Next
State
J3 K3 J2 K2 J1 K1 J0 K0
0000 0001 0 X 0 X 0 X 1 X
0001 0010 0 X 0 X 1 X X 1
0010 0011 0 X 0 X X 0 1 X
0011 0100 0 X 1 X X 1 X 1
0100 0101 0 X X 0 0 X 1 X
0101 0110 0 X X 0 1 X X 1
0110 0111 0 X X 0 X 0 1 X
0111 1000 1 X X 1 X 1 X 1
1000 1001 X 0 0 X 0 X 1 X
1001 0000 X 1 0 X 0 X X 1
Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to
derive a simplified Boolean expression for each flip-flop. This is shown in Figure 4. The 1s in
the Karnaugh maps of figure 4 are grouped with “don’t cares” and the following expressions for
the J and K inputs of each flip-flop are obtained:
Page12.365.5
6. Figure 4: Karnaugh Map
The final step is to implement the combinational logic from the equations and connect the flip-
flops to form the sequential circuit. Multisim was used to simulate the designed sequential
circuit. Simulation diagram is shown in Figure 5.
Figure 5: Simulation of the design of decade counter
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7. Schematic of a decade counter using the 7490, 7447 (decoder driver), and 7- segment display is
shown in figure 6. Close analysis of both the design and standard chip implementation indicates
that the worst case timing situations are counting transition from state 0011 to state 0100, and
from state 0111 to state 1000.
Next section will discuss the work conducted by Luiz Carolos Kertly and Daniel Cardoso de
Souza [4] to resolve the timing issues. The authors have suggested for transitions to properly
occur, the added propagation delays in FF1, FF2, and FF3 have to be less than half the period of
the clock signal. For the first transition, after the negative clock edge, propagation time delay of
FF1 passes until QA goes down, then one more time propagation time delay of FF2 passes until
QB goes down, and finally one more time propagation time delay of FF3 for QC to rise. For
counter operation at a 1GHz clock frequency, tPD, FF1 + tPD, FF2 + tPD, FF3 <= 500ps, which means that
the tPD of each FF must be less than approximately 160ps [6].
First, one FF must be designed to meet this timing constraint, while also showing an acceptable
Vpp with a realistic tool load; then, after this compliant FF cell has been simulated and found to
be adequate, it will be used as a reference point in addressing the decade counter problem. The
study conducted by Luiz et al shows that the flip-flops need to be redesigned at the chip level to
achieve better and robust performance of the counter.
The decade counter was also simulated using NI-ELVIS [5]. The step up of the counter and NI-
ELVIS interface is shown in Figure 6. The timing diagram analysis also shows that the transition
of the counter is not smooth from the states 0 to 3 and 7 to 8.
Figure 6: Decade counter with off the shelf chips Page12.365.7
8. Figure 6: NI -ELVIS and Decade Counter Interface
Student Outreach Program
The project offered an opportunity for students to work with others in their class whom they had
never worked with. This activity focused on important learning concepts such as Electronics,
Programming, Teamwork, and Cross Disciplinary Interaction.
Electronics symbolize the interrelationship between various substructures of the circuit. This
includes an understanding of electronic components and the manner in which all these
components function together as a deterministic whole system. Basic components such as flip-
flops, displays, counters and electronics which include NI-ELVIS, and the Multisim system are
the major components of the project activity. Integrating these components offered an
opportunity for the students to understand the design/development of digital systems.
Programming varied from high school students to college students. The high school level
students were trained to program the circuit from the user end point of view. At college level the
students were introduced to design concepts.
The project carried out the concept of teamwork in all phases of design and implementation. The
goal of linking the students into a learning community is to give the student a peer group in
which they feel comfortable. The team work prepares the students to solve technical problems in
a group environment in addition to meet new challenges encountered in the work place. Students
experience being on successful teams to appreciate and understand the value of good team work.
The project emphasizes on the word team because team is not same as group. The term group
implies a somewhat more than a collection of individuals but the team implies much more [2].
The curriculum in any specific area of study tends to narrowly focus students on that area,
whereas real-world multifaceted systems tend to incorporate components from multiple
disciplines. The development of such systems has shifted from designing individual components
in segregation to working in cross-functional teams that include the variety of proficiencies
needed to design an entire system [1].The counter design provides an opportunity for students
interested in electronics, design, application and troubleshooting to combine their interest in
building a digital systems project..
Page12.365.8
9. The goal of this outreach program was to exemplify the impact of design and implementation of
digital systems in learning Mathematics and Science at the secondary school level. Significant
trends were measured from the activity which included the Electronics, Programming,
Teamwork, and cross disciplinary interaction. The results show that the students learned tangible
lessons from each topic.
Results
The design and implementation of the decade counter was completed. The simulation analysis of
the decade counter using the Mutlisim revealed that the worst case timing situations were from
counting transition from state 0011 to state 0100, and from state 0111 to state 1000. VI was
developed using LabView to acquire data from the decade counter circuit built on NI-ELVIS. It
was observed that for the transitions to occur properly, the added propagation delays in FF1,
FF2, and FF3 have to be less than half the period of the clock signal. Final analysis of this case
study revealed that the redesign of the flip-flop is required for counter to work properly.
However, testing of the circuit board under actual working was successful. The circuit was
constructed on NI-ELVIS and the tests were successful and the checks were correctly performed.
Conclusion
The project was a successful collaboration between the faculty of SSU and GTREP students at
SSU. The designed unit met expectations of the circuit performance. The students had an
opportunity to work on a project that involved design and implementation of digital systems. The
students will also assist the faculty to promote the design and application concepts to the high
school and college students which will serve as a model for improving and creating interest in
Engineering and Technology education.
Acknowledgements
Closing the Hardware Design Loop with Multisim®: A Case Study was funded by MAGEC-
STEM which is a NSF funded activity. We gratefully acknowledge our students Ayush Bhardwaj
and Crystal Reeves for their significant contributions.
Page12.365.9
10. References
[1] Aldridge, M.D. (1996) Cross-Disciplinary Teaming and Design (ASEE Annual Conference
and Exposition, 1996.)
[2] Courtner, Lyons, Millar, and Bailey (1999) Student Outcomes and Experiences in a
Freshman Engineering Design Course. (1999 ASEE Annual Conference and Exposition,
session 2553)
[3] Evan, Robinson (June 2006). An Integrated Platform for Electronics Education: A Case
Study.
[4] Luiz, Carolos Kertly & Daniel, Cardoso de Souza. Design of a “7490-Like” Decade-Counter
Integrated Circuit, Using GaAs MESFET DCFL Family, for Frequencies up to 1GHz.
[5] National Instruments NI-ELVIS. Dallas, TX.
[6] Vitesse Semiconductor Corp (1993) “Foundry Design Manual” (Version 6.0).
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