UNIT-5
Design of Arithmetic building
blocks and subsystems
Arithmetic Building Blocks
•Datapath elements
• Adder design
Static adder
Dynamic adder
• Multiplier design
Array multipliers
• Shifters, Parity circuits
Composition of digital processor
Inter connections of basic
combinational functions
Addition, multiplication,
comparison & shift
Logical(AND,OR & XOR)
RAM, ROM,
Buffers, Shift
registers
- Finite state
machine (PLA,
random logic.) -
Counters
Interconnect - Switches - Arbiters - Bus
Bit sliced data path organization
Adders
•Commonly used in arithmetic operation
•Also speed limiting element.
•Optimization
1. logic level rearrange the Boolean equation
2. circuit level manipulate transistor sizes and circuit
topology
Binary adder
Full adder
Ripple-Carry Adder
Goal: Make the fastest possible carry path circuit
Static CMOS Full Adder
Static implementation of CLA
Dynamic implementation of CLA
Carry bypass adder
If
Cin=1 & p0,p1,p2..=1
C4=1 or cin
Generally cout=cin
Carry bypass in Manchester carry chain adder
Carry select adder
Linear Carry select adder
Squart Root Carry select adder
MULTIPLIER
22
18: Datapath Functional Units
MULTIPLICATION
 Example:
 M x N-bit multiplication
 Produce N M-bit partial products
 Sum these to produce M+N-bit product
1100 : 1210
0101 : 510
1100
0000
1100
0000
00111100 : 6010
multiplier
multiplicand
partial
products
product
23
18: Datapath Functional Units
GENERAL FORM
 Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
 Multiplier: X = (xN-1, xN-2, …, x1, x0)
 Product:
1 1 1 1
0 0 0 0
2 2 2
M N N M
j i i j
j i i j
j i i j
P y x x y
   

   
   
 
   
 
 
  
x0
y5
x0
y4
x0
y3
x0
y2
x0
y1
x0
y0
y5
y4
y3
y2
y1
y0
x5 x4 x3 x2 x1 x0
x1
y5
x1
y4
x1
y3
x1
y2
x1
y1
x1
y0
x2
y5
x2
y4
x2
y3
x2
y2
x2
y1
x2
y0
x3
y5
x3
y4
x3
y3
x3
y2
x3
y1
x3
y0
x4
y5
x4
y4
x4
y3
x4
y2
x4
y1
x4
y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p0
p1
p2
p3
p4
p5
p6
p7
p8
p9
p10
p11
multiplier
multiplicand
partial
products
product
24
BINARY MULTIPLICATION
18: Datapath Functional Units
Multiplication Steps:
1.Patial product generation
3.Final addition
2.Partial product accumulation
array multiplier
Carry save multiplier
Tree multiplier
Baugh wooley multiplier
Braun Multiplier
Array Multiplier
CARRY SAVE ARRAY MULTIPLIER
WALLACE TREE MULTIPLIER
31
BINARY SHIFTER
18: Datapath Functional Units
32
BARREL SHIFTER
18: Datapath Functional Units

Design of Arithmetic Building Block Unit-5 VLSI.pptx