The document discusses the design and functionality of combinational and sequential logic circuits in digital systems. Combinational circuits generate outputs based only on present inputs and do not store states, while sequential circuits rely on clock cycles and past inputs, featuring memory elements. It also highlights various implementations and considerations related to timing, clock skew, and jitter in digital circuit designs.

1. UNIT-IV
SEQUENTIAL LOGIC CIRCUIT DESIGN

2. DIGITAL CIRCUITS
1. Combinational Circuits:
As the time independent circuits which do not depends upon
previous inputs to generate any output are termed as
combinational circuits.
•In this output depends only upon present input.
•Speed is fast.
•It is designed easy.
•There is no feedback between input and output.
•This is time independent.
•Elementary building blocks: Logic gates
•Used for arithmetic as well as boolean operations.
•Combinational circuits don’t have capability to store any state.
•As combinational circuits don’t have clock, they don’t require
triggering.
•These circuits do not have any memory element.
•It is easy to use and handle.
•Examples – Encoder, Decoder, Multiplexer, Demultiplexer

3. 2. Sequential Circuits:
which are dependent on clock cycles and depends on present as
well as past inputs to generate any output.
•In this output depends upon present as well as past input.
•Speed is slow.
•It is designed tough as compared to combinational circuits.
•There exists a feedback path between input and output.
•This is time dependent.
•Elementary building blocks: Flip-flops
•Mainly used for storing data.
•Sequential circuits have capability to store any state or to retain
earlier state.
•As sequential circuits are clock dependent
they need triggering.
•These circuits have memory element.
•It is not easy to use and handle.
Examples – Flip-flops, Counters

4. STATIC LATCHES AND
REGISTERS

5. Under the condition that the gain of the inverter in the
transient region is larger than 1, only A and B are stable
operation points, and C is a metastable operation point.
The Bistability Principle

6. Every deviation (even the smallest one)
causes the operation point to run away
from its original bias.
Operation points with this property are
termed metastable.
the loop gain is much smaller than unity.
cross-coupling of two inverters results in a
bistable circuit, that is, a circuit with two
stable states, each corresponding to a logic
state. The circuit serves as a memory, storing
either a 1 or a 0 (corresponding to positions A
and B).

7. •a bistable circuit has two stable states.
•In absence of any triggering, the circuit remains in a
single state (assuming that the power supply remains
applied to the circuit), and hence remembers a value.
•A trigger pulse must be applied to change the state of the
circuit.
•Another common name for a bistable circuit is flip-flop
(unfortunately, an edge-triggered register is also referred
to as a flip-flop).

8. SR Flip-Flops

9. Multiplexer Based Latches
Positive latch built using transmission gates.

10. It is possible to reduce the clock load to two transistors by using
implement multiplexers using NMOS only pass transistor
The advantage of this approach is the reduced clock load of only two
NMOS devices.
NMOS only pass transistors results in the passing of a degraded high
voltage of VDD-VTn to the input of the first inverter.
It also causes static power dissipation in first inverter

11. Master-Slave Based Edge Triggered Register
On the low phase of the clock, the master stage is transparent and the
D input is passed to the master stage output
During this period, the slave stage is in the hold mode, keeping its previous
value using feedback.

13. Another problem with this scheme is the reverse conduction

14. Non-ideal clock signals
Create Clock Skew overlapping of clock signals,
Clk,clkbar  both are high  direct path will be create from D to
Q
Race condition

15. To over come this problem by using non overlapping clock signal PH1
& PH2

16. Low-Voltage Static Latches
At very low power supply voltages, the input to the inverter cannot be raised
above the switching threshold, resulting in incorrect evaluation.

17. DYNAMIC LATCHES
AND REGISTERS

18. The useful property that a stored value remains valid as long
as the supply voltage is applied to the circuit, hence the name
static.
A stored value can hence only be kept for a limited amount of
time, typically in the range of milliseconds. If one wants to
preserve signal integrity, a periodic refresh of its value is
necessary. Hence the name dynamic storage

19. Dynamic Transmission-Gate Based Edge-triggred
Registers
CLK0  input data D sampled on node 1
Slave hold mode  node 2 high impedance.
CLK1  T2 on node 1 value propagate to Q.
node1 is stable  T1 is off.
Setup time  Simply delay of transmission gate ( node 1 to sample D input)
Hold time Zero
Transmission gate is turned off on clock edge.
Propagation delay2* inverter delay+ transmission gate delay

20. Important consideration:
1. Storage nodes has to be periodically refreshed
To prevent loss due to
1. Leakage of charge,
2. diode leakage,
3.subthreshold current.
2.clock overlap
During the 0-0 overlap period,
The NMOS of T1 and the PMOS of T2 are simultaneously on.
creating a direct path for data to flow from the D input of the register
to the Q output.
This is known as a race condition.
overlap period constraint is given as:
Similarly, the constraint for the 1-1 overlap is given as:

21. C2
MOS Dynamic Register
Positive edge-triggered register based on the master-slave concept which is
insensitive to clock overlap.
CLK=0 Master  Tristate
inverter
Node X inversion of D
Slave  Hold Mode (M7 and M8 off)
CLK=1 Master  Hold Mode
Node X inversion of D
Slave  Tristate inverter Q=D

22. Data sampled on node X
(M2 & M4 ON)
X 0 to 1 transition during overlap
period
End of overlap period CLK bar
=1(M7 & M8 off) slave hold mode.
Any new data sample on falling edge
 it can not propagte through Q
Data sampled on node X
(M1 & M3 ON)
X 1 to 0 transition during overlap
period
End of overlap period CLK bar
=M8 on) 0 is propagate to output.
Problem is fixed by the data D
should be stable during the overlap
period.

23. Dual-edge Triggered Registers
Edge-triggered registers that sample the
input data on only one of the clock edges
(rising or falling).
Also possible to design sequential circuits
that sample the input on both edges
Lower frequency of the CLK is Distributed
 power will be
saved.

24. C2
MOS provides a skew-tolerant solution, it is possible to design
registers that only use a single phase clock.
The True Single-Phase Clocked Register (TSPCR) proposed by Yuan
and Svensson uses a single clock (without an inverse clock).
True Single-Phase Clocked Register (TSPCR)
Positive Latch:
Clk high Latch transparent
propagates input to output.
Clk LOW Latch Disabled Hold
Mode
Advantages: use single phase CLK,
& delay is reduced
Overall performance is
improved
Disadvantages:
Slight Transistor count increased.

25. Further reduced complexity
Only the first inverter is controlled by the clock.
Reduced the no.of transistor
Clock load is reduced by half
But the output can not be a full logic swing.

26. Specialized single-phase edge-triggered register
CLK0 sample the data to node X.
2nd
inverter is precharge Y=Vdd
3 inverter is hold mode.
CLK1 2nd
inverter is Evaluates X propagtae to Y
3 inverter  Y is passed to Q X1  Y discharge

27. Pulse Registers
Until now, we have used the master-slave configuration to create an edge-
triggered register
different approach for constructing a register uses pulse signals
idea is to construct a short pulse around the rising (or falling) edge of the
clock
This pulse acts as the clock input to a latch sampling the input only in a
short window.
Race conditions are thus avoided by keeping the opening time (i.e, the
transparent period) of the latch very short.
Positive edge-triggered register = glitch generation circuitry + latch

28. When CLK = 0, node X is charged up to VDD (MN is off since CLKG is low)
When CLK =1, short period of time when both inputs of the AND gate are
high causing CLKG to go high.
This in turn activates MN, pulling X and eventually CLKG low
The length of the pulse is controlled by the delay of the AND gate and the
two inverters.

29. •Set-up time is essentially zero,
•Hold time is equal to the length of the pulse (if the contamination
delay is zero for the gates),
•Propagation delay (tc-q) equals two gate delays.
Advantages:
Reduced clock load
Small no. of transistors required.
Disadvantage:
Substantial increase in verification complexity
Another Version:( used in AMDK6 processor)

30. Sense-Amplifier Based Registers
Building edge-triggered registers:1. master-slave, 2. glitch technique
Sense amplifier circuits
accept small input signals
and amplify them to generate
rail-to-rail swings
Used extensively in
1. memory cores
2. low swing bus drivers to amplify
small voltage swings present in
heavily loaded wires.
Precharged front-end amplifier

31. cross-coupled inverter (M5-M8)
CLK 0 : whose outputs (L1 and L2) are
precharged using devices M9 and M10
PMOS transistors M7 and M8 to be turned
off
NAND FF is holding its previous state
Transistor M1 is similar to an evaluate
switch in dynamic circuits
CLK=1  M1 is enabled , differential input
pair (M2 and M3) is enabled
difference between the input signals
is amplified on the output nodes on L1 and
L2

32. PIPELINING
used to accelerate the operation of the datapaths in digital processors
log(|a − b|),

33. Latch- vs. Register-Based Pipelines

34. NORA-CMOS—A Logic Style for Pipelined Structures
A C2MOS-based pipelined circuit is race-free as long as all the logic
functions F (implemented using static logic) between the latches are
noninverting.

36. Non-Bistable Sequential Circuits
•Focused on one single type of sequential element-latch
•Two stable states-bistable
•Other regenerative circuits: astable and monostable.
used for on-chip clock Generation
•one-shot circuits
•Schmitt trigger
the useful property of showing hysteresis in its dc characteristics—
its switching threshold is variable and depends upon the direction of
the transition (low-to-high or high-to-low).
Peculiar feature can come in handy in noisy environments.

37. The Schmitt Trigger
two important properties:
1. It responds to a slowly changing input waveform with a fast transition
time at the output.
2. The voltage-transfer characteristic of the device displays different
switching thresholds for positive- and negative-going input signals.
The switching thresholds for the low-to-
high and high to-low transitions are called
VM+ and VM−, respectively
The hysteresis voltage is
defined as the difference
between the two. One of the main uses of the Schmitt
trigger is to turn a noisy or slowly
varying input
signal into a clean digital output signal.

38. Switching threshold of a CMOS
inverter is determined
by the (kn / kp) ratio between the
NMOS and PMOS transistors
Increasing the ratio results in a
reduction of the threshold, while
decreasing it results in an increase in VM.

39. single NMOS transistor (M1) in the pull-down chain.
This modifies the effective transistor ratio of the inverter to
kM1/(kM2+kM4), which moves the switching threshold upwards.
Once the inverter switches, the feedback loop turns off M4, and the
NMOS device M3 is activated.
extra pull-down device speeds up the transition and produces a clean
output signal with steep slopes.
Vin=0 vout=0; M4 conductive mode ;
M3 is off
The input signal effectively connects to an
inverter consisting of two PMOS transistors in
parallel.

40. Monostable Sequential Circuits
A monostable element is a circuit that generates a pulse of a
predetermined width every time the quiescent circuit is triggered by a
pulse or transition event.
It is called monostable because it has only one stable state (the
quiescent one).

41. An astable circuit has no stable states. The output oscillates back and forth
between two quasi-stable states with a period determined by the circuit
topology and parameters
Astable Circuits
One of the main applications of oscillators is the on-chip generation of
clock signals.
The ring oscillator is a simple, example of an astable circuit
It consists of an odd number of inverters connected in a circular chain.
Due to the odd number of inversions, no stable operation point exists,
In many applications, it is necessary to control the frequency of the
oscillator

43. TIMING CLASSIFICATIONS
 Synchronous systems
 All memory elements in the system are simultaneously updated using
a globally distributed periodic synchronization signal (i.e., a global
clock signal)
 Functionality is ensure by strict constraints on the clock signal
generation and distribution to minimize
 Clock skew (spatial variations in clock edges)
 Clock jitter (temporal variations in clock edges)
 Asynchronous systems
 Self-timed (controlled) systems
 No need for a globally distributed clock, but have asynchronous
circuit overheads (handshaking logic, etc.)
 Hybrid systems
 Synchronization between different clock domains
 Interfacing between asynchronous and synchronous domains

44. REVIEW: SYNCHRONOUS TIMING BASICS
 Under ideal conditions (i.e., when tclk1 = tclk2)
T  tc-q + tplogic + tsu
thold ≤ tcdlogic + tcdreg
 Under real conditions, the clock signal can have both
spatial (clock skew) and temporal (clock jitter) variations
 skew is constant from cycle to cycle (by definition); skew can
be positive (clock and data flowing in the same direction) or
negative (clock and data flowing in opposite directions)
 jitter causes T to change on a cycle-by-cycle basis
D Q
R1
Combinational
logic
D Q
R2
clk
In
tclk1 tclk2
tc-q, tsu,
thold, tcdreg
tplogic, tcdlogic

45. SOURCES OF CLOCK SKEW AND
JITTER IN CLOCK NETWORK
PLL
1
2
4
3
5
6
7
clock
generation
clock drivers
power supply
interconnect
capacitive load
capacitive
coupling
temperature
 Skew
 manufacturing device
variations in clock drivers
 interconnect variations
 environmental variations
(power supply and
temperature)
 Jitter
 clock generation
 capacitive loading and
coupling
 environmental variations
(power supply and
temperature)

46. POSITIVE CLOCK SKEW
D Q
R1
Combinational
logic
D Q
R2
clk
In
tclk1 tclk2
delay
  > 0: Improves performance, but makes thold harder to meet. If thold
is not met (race conditions), the circuit malfunctions independent of
the clock period!
T
T + 
 > 0
 + thold
T +   tc-q + tplogic + tsu so T  tc-q + tplogic + tsu - 
thold +  ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg - 
1
2
3
4
 Clock and
data flow in
the same
direction
T :
thold :

47. NEGATIVE CLOCK SKEW
D Q
R1
Combinational
logic
D Q
R2
clk
In
tclk1 tclk2
delay
 Clock and
data flow in
opposite
directions
T
T + 
 <
0
T +   tc-q + tplogic + tsu so T  tc-q + tplogic + tsu - 
thold +  ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg - 
1
2
3
4
  < 0: Degrades performance, but thold is easier to meet
(eliminating race conditions)
T :
thold :

48. CLOCK JITTER
 Jitter causes T to vary
on a cycle-by-cycle
basis
R1
Combinational
logic
clk
In
tclk
T
-tjitter +tjitter
T - 2tjitter  tc-q + tplogic + tsu so T  tc-q + tplogic + tsu + 2tjitter
 Jitter directly reduces the performance of a sequential
circuit
T :

49. COMBINED IMPACT OF SKEW
AND JITTER D Q
R1
Combinational
logic
D Q
R2
In
tclk1 tclk2
 Constraints
on the
minimum
clock period
( > 0)
  > 0 with jitter: Degrades performance, and makes
thold even harder to meet. (The acceptable skew is
reduced by jitter.)
T
T + 
 > 0
1
6 12
-tjitter
T  tc-q + tplogic + tsu -  + 2tjitter thold ≤ tcdlogic + tcdreg –  – 2tjitter

50. CLOCK DISTRIBUTION NETWORKS
 Clock skew and jitter can ultimately limit the performance
of a digital system, so designing a clock network that
minimizes both is important
 In many high-speed processors, a majority of the dynamic power
is dissipated in the clock network.
 To reduce dynamic power, the clock network must support clock
gating (shutting down (disabling the clock) units)
 Clock distribution techniques
 Balanced paths (H-tree network, matched RC trees)
 In the ideal case, can eliminate skew
 Could take multiple cycles for the clock signal to propagate to the
leaves of the tree
 Clock grids
 Typically used in the final stage of the clock distribution network
 Minimizes absolute delay (not relative delay)

51. H-TREE CLOCK NETWORK
Clock
Clock
Idle
condition
Gated
clock
Can insert clock gating at
multiple levels in clock tree
Can shut off entire subtree
if all gating conditions are
satisfied
 If the paths are perfectly balanced, clock skew is zero

52. CLOCK GRID NETWORK
 Distributed buffering reduces absolute delay and makes clock
gating easier, but is sensitive to variations in the buffer delay
Clock
secondary clock buffers
local logic
area
main clock
buffer
 The secondary buffers
isolate the local clock
nets from the upstream
load and amplify the
clock signals degraded
by the RC network
 decreases absolute skew
 gives steeper clocks
 Only have to bound the
skew within the local
logic area