It is based on low power technique. One of these techniques are adiabatic logic. This presentation is simple seminar presentation at college.

1. ADIABATIC LOGIC OR
CLOCK POWERED
LOGIC
By:
Tuhinansu Pradhan
Roll number – 1559025
M.Tech 1st year in VLSI Design and Embedded
System
KIIT University

2. CONTENTS
 Introduction
 Adiabatic logic
 Terminology and key rules
 Basics of adiabatic circuits
 Power clock
 Power supply
 Examples of adiabatic circuits
 Types of adiabatic logic circuits
 Which adiabatic circuits can be further used ??
 Positive feedback adiabatic logic (PFAL)
 Dissipation of energy for an inverter w.r.t frequency and supply voltage
 Pros and cons
 Future work
 References

3. INTRODUCTION
 Full-swing voltage-mode CMOS logic styles have been extremely successful
both technically and in terms of market share.
 But switching power dissipation of CMOS circuit with capacitive load 𝐶𝐿 has a
lower limit of
1
2
𝐶𝐿 𝑉𝑑𝑑
2
.
 To solve this problem we tried to reduce the supply voltage, known as supply
voltage scaling and we tried to reduce the capacitance of the device. But as
the CMOS technology is going into nanometres, the reduction of load
capacitance is limited and of course there is a limitation of voltage scaling
that depends on threshold voltages.
 So the other alternative is adiabatic switching circuits, where the switching
energy dissipation is below this lower limit.

4. ADIABATIC LOGIC
 “Adiabatic” is a term of Greek origin that has spent most of its history
associated with classical thermodynamics.
 It refers to a system in which a transition occurs without energy (usually
in the form of heat) being either lost to or gained from the
environment.
 In the context of electronic systems, rather than heat, electronic charge
is preserved. Thus, an ideal adiabatic circuit would operate without the
loss or gain of electronic charge.
 Practically, an ideal adiabatic circuit is not possible
 By adopting a real adiabatic logic, each charge can be recycled for many
time so that a significant energy dissipation reduction would be
possible.

5. TERMINOLOGY AND KEY RULES
Adiabatic switching:
 It means that the output node is charged slowly compared to its time
constant and we ensure that the voltage drop across the transistor is
relatively small at the time when the switching occurs.
charge recycling:
 It means that instead of dumping the charge to ground on every clock
cycle, the charge can be designed to flow back to the power clock.
Key Rules :
 Never turn on a transistor if there is a voltage across it (VDS > 0)
 Never turn off a transistor if there is a current through it (IDS ≠ 0)
 Never pass current through a diode

6. BASICS OF ADIABATIC CIRCUITS:
Conventional CMOS:
When PMOS is Switched ON,
Energy in Capacitor= ½CV2
Energy Dissipation = ½CV2 -> PMOS
When NMOS is Switched ON,
Energy Drained= ½CV2
Energy Dissipation = ½CV2 -> NMOS

7. BASICS OF ADIABATIC CIRCUITS
(Continued):
In adiabatic logic, one of the two power supplies can be used:
 Constant slow charging current power supply
 Variable voltage supply (with slow ramp)

8. BASICS OF ADIABATIC CIRCUITS
(Continued):
𝑖 𝑡 = 𝐶
𝑑𝑣
𝑑𝑡
= 𝐶
𝑉 𝑑𝑑
𝑇
(Constant Current)
𝐸𝑛𝑒𝑟𝑔𝑦 𝐷𝑢𝑟𝑖𝑛𝑔 𝑇𝑟𝑎𝑛𝑠𝑖𝑡𝑖𝑜𝑛 𝑇𝑖𝑚𝑒 𝑇 = 𝐼2
. 𝑅. 𝑇
= (𝐶
𝑉𝑑𝑑
𝑇
)2
. 𝑅. 𝑇 =
𝑅𝐶
𝑇
. 𝐶. 𝑉𝑑𝑑
2
Energy Dissipated During Transition Time also depends upon the charging time
T, If T>> 2RC then energy dissipation will be smaller than the conventional
CMOS .

9. BASICS OF ADIABATIC CIRCUITS
(Continued):
 The energy stored at output can be retrieved by the reversing the current
source direction during discharging process instead of dissipation in NMOS
network. Hence adiabatic switching technique offers the less energy
dissipation in PMOS network and reuses the stored energy in the output
load capacitance by reversing the current source direction.

10. BASICS OF ADIABATIC CIRCUITS
(Continued):
Conventional CMOS Adiabatic Logic

11. POWER CLOCK :
 Adiabatic system requires:
– Digital core: adiabatic gates
– Generation of power clock
signal/signals
 Adiabatic Logic circuits are operated
with an oscillating power-supply, the
so-called power-clock.
 Depending on the regarded adiabatic
family, more than one power-clock
signal is used to operate a system
consisting of Adiabatic Logic gates.

12. POWER CLOCK (Continued):
 Each power-clock cycle consists of four
intervals E,H,R,W.
 Evaluate (E): outputs are evaluated from
stable input signals
 Hold (H): outputs are kept stable to supply
subsequent gate with stable input signal.
 Recover (R): Energy is recovered
 Wait (W): for symmetry reasons because
symmetric signals are easier to generate

13. POWER SUPPLY
 Either inductor or capacitor is to be used for storing the recovered energy.LC
tank circuit can also be used but capacitor is most preferred.
 Another way of power supply is Stepwise charging
– Charging of output to VDD is not done abruptly,
but is divided into N steps

14. EXAMPLES OF ADIABATIC CIRCUITS
Inverter and Buffer NAND and AND Logic
Both Inputs and Outputs are Dual-Rail Encoded
Transmission Gate Adiabatic Logic

15. TYPES OF ADIABATIC LOGIC CIRCUITS
 Quasi/Partial Adiabatic Logic Circuits:
(i) Efficient Charge Recovery Logic (ECRL).
(ii) 2N-2P Adiabatic Logic.
(iii) 2N-2N2P Adiabatic Logic.
(iv) Positive Feedback Adiabatic Logic (PFAL).
 Full Adiabatic Logic Circuits:
(i) Pass Transistor Adiabatic Logic (PAL).
(ii) Split- Rail Charge Recovery Logic (SCRL).
Pass Transistor Adiabatic Logic (PAL)
Split- Rail Charge Recovery Logic (SCRL).

16. Efficient Charge Recovery
Logic (ECRL).
Positive Feedback Adiabatic
Logic (PFAL).
2N-2N2P Adiabatic Logic.2N-2P Adiabatic Logic.
Transistor count and Power Dissipation of
different Logics for a fulladder adder

17. Conventional Symmetrical CMOS
Full Adder
Pass transistor based adiabatic full adder

18. Positive feedback adiabatic full adder a) Sum
b) carry
Transmission gate based adiabatic full adder
a) Sum b) Carry

19.  Fully Adiabatic circuits reduce the power consumption significantly, but they
are very complex to design.
 Fully Adiabatic circuits are relatively slow.
 They require higher supply voltage.
 Although the partially adiabatic circuits are not as efficient as fully adiabatic
circuits in terms of power consumption but they reduce the circuit complexity
and conserve the power.
 So we can say that partially adiabatic circuits are fair compromise between
the power consumption and complexity trade off.
 Among quasi adiabatic circuits the positive feedback adiabatic logic(PFAL)
circuit shows the lowest energy consumption and a good robustness against
technological parameter variations.
WHICH ADIABATIC CIRCUITS CAN BE
FURTHER USED ??

20. POSITIVE FEEDBACK ADIABATIC LOGIC (PFAL)
 The partial energy recovery circuit structure named
Positive Feedback Adiabatic Logic (PFAL) has been
used, since it shows the lowest energy consumption if
compared to other similar families, and a good
robustness against technological parameter variations.
 It is a dual-rail circuit with partial energy recovery.
 The core of all the PFAL gates is an adiabatic amplifier,
a latch made by the two PMOS M1-M2 and two NMOS
M3-M4, that avoids a logic level degradation on the
output nodes out and/out.
 The two n-trees realize the logic functions.
 This logic family generates both positive and negative
outputs. The functional blocks are in parallel with the
PMOSFETs of the adiabatic amplifier and form a
transmission gate.
The general schematic of the PFAL gate

21. DISSIPATION OF ENERGY FOR AN INVERTER
w.r.t FREQUENCY AND SUPPLY VOLTAGE
Fig. Energy consumption per cycle versus frequency for
an inverter at VDD = 2.5V and load capacitance = 20fF.

22. PROS AND CONS
 + Less Power if high switching activity or disconnect system from
power supply while idle (sleep transistors).
 + We get output as the required function and its complement
 - Slower than conventional CMOS (generally limited to MHz range)
 - Requires special power supply
 - Area required is more (can be neglected if the aftermath of
cooling effects for CMOS circuits are taken into account)

23. FUTURE WORK
 From the study it was found that the adiabatic logic circuits can play a
significant role in designing applications where power conservation is of
prime importance such as pacemaker which does not need to operate at a
very high frequency, but saving of energy is extremely important, because
user cannot replace the battery every few years and battery placement is
hazardous.
 Another usage can be portable digital systems running on batteries such as
personal digital assistants and GPS system where the battery life is more
important then speed.
 Research is on to identify applications, where adiabatic techniques
outperform conventional ones and to use adiabatic circuits effectively.
 In future research depending on the application and the system
requirements, a suitable adiabatic circuit design approach can be selected
and analysed to reduce the power dissipation of such systems.

24. References
1. MIT International Journal of Electronics and Communication
Engineering, Vol. 3, No. 2, August 2013, pp. 108–114 ISSN No.
2230-7672 ©MIT Publications “Adiabatic Logic Circuits: A
Retrospect”
2. Adiabatic Logic Future Trend and System Level Perspective -
Teichmann, Philip (google books)
3. CMOS Digital Integrated Circuits Analysis & Design - by Sung-Mo
(Steve) Kang (Author), Yusuf Leblebici (Author)
4. NPTEL Lecture on Low Power VLSI Circuits and Systems by Prof.
Ajit Pal