CMOS Fabrication Flow

1. Fabrication Process Flow
Sudhanshu Janwadkar , Teaching Assistant, SVNIT, Surat
Lecture Notes 20-27 January 2017.

3. Crystal Growth
 Electron Grade Silicon (EGS), a polycrystalline material of high purity is the raw
material for the preparation of Single Crystal Silicon
 The metallurgy grade silicon is not suitable - impurities of Boron, Carbon and
residual donors should be in ppb range
 Czocharalsky (CZ) technique – Crystal Growth
 Crystal Growth involves a phase change from solid/liquid/gas phase to a
crystalline solid phase.
 CZ technique involves solidification of atom in liquid state at the interface.

4. *Note: Figure Intended only for Understanding of the Concept

5. Crystal Growth
 In the crystal-growing process, polycrystalline silicon (EGS) is placed in the crucible and
the furnace is heated above the melting temperature of silicon.
 A seed crystal is suspended over the crucible in a seed holder.
 The seed is inserted into the melt.
 Part of it melts, but the tip of the remaining seed crystal still touches the liquid surface.
 It is then slowly withdrawn.
 Progressive freezing at the solid-liquid interface yields a large, single crystal.
 The wafers are obtained by cutting single-crystal ingot into thin slices
 Typically, wafers have dimensions: diameter between 4 to 12 inch & at most 1mm
thickness
 Surface grinding and polishing operations follow
 Chemical etching follows

6. Epitaxial Growth
 This Process involves growth of single-crystal semiconductor layers on a single-crystal
semiconductor substrate.
 Epitaxy - Greek words epi (meaning "on") and taxis (meaning "arrangement").
 Epitaxial layer can be grown at a temperature well below the melting point, usually 30-40%
lower than the melting point
 Homoepitaxy: The epitaxial layer and the substrate materials are the same, material. For
example, an n-type silicon can be grown epitaxially on an n+-silicon substrate.
 Heteroepitaxy: The epitaxial layer and the substrate are chemically and often
crystallographically different, we have, such as the epitaxial growth of AlxGa(1-x)As on GaAs
 Techniques: Chemical Vapour Deposition , Molecular Beam Epitaxy

7. Epitaxial Growth (Chemical Vapour
Deposition- CVD Process)
 CVD is a process whereby an epitaxial layer is formed by a chemical reaction
between gaseous compounds at appropriate pressure
 SiCl4 (gas) + 2H2 (gas) Si (solid) + 4HC1 (gas
*Note: Figure Intended only for Understanding of the Concept

8. Epitaxial Growth(CVD Process)
 The mechanism of CVD involves a number of steps:
(a) The reactants such as the gases and dopants are transported to the substrate
region
(b) They are transferred to the substrate surface where they are adsorbed
(c) A chemical reaction occurs, catalysed at the surface, followed by growth of the
epitaxial layer
(d) The gaseous products are desorbed into the main gas stream, and
(e) The reaction products are transported out of the reaction chamber.

9. Epitaxial Growth (Molecular Beam Epitaxy)
 MBE is an epitaxial process involving the reaction of one or more thermal beams of
atoms or molecules with a crystalline surface under ultrahigh-vacuum conditions
 MBE can achieve precise control in both chemical compositions and doping profiles.
 Single-crystal multilayer structures with dimensions on the order of atomic layers can
be made using MBE

10. Oxidation
 The Oxidation process is chiefly used to form silicon dioxide (SiO2)
 Thin Oxide – Gate Oxide Layer Thick Oxide – Field Oxide Layer
 Gate-oxide layer is a thin-film under which a conducting channel can be formed between
the source and the drain.
 Field-Oxide layer is a thick layer of silicon dioxide, which acts as the insulator between
the neighbouring devices
 Semiconductors can be oxidized by various methods: thermal oxidation, electrochemical
anodization, and plasma reaction. Among these methods, thermal oxidation is by far the
most important for silicon devices.

11. Oxidation
*Note: Figure Intended only for Understanding of the Concept

12. Oxidation
 Dry and Wet Oxidation:
Si (solid) + 02 (gas) + SiO2 (solid) Dry Oxidation
Si (solid) + 2H20 (gas) + SiO2 (solid) +2H2 (gas) Wet Oxidation
 The oxidation temperature is generally in the range of 900"-1200°C and the typical
gas flow rate is about 1 liter/min.
 Oxides grown in dry oxygen have the best electrical properties,
 Considerably more time is required to grow the same oxide thickness at a given
temperature in dry oxygen than in water vapor.
 For relatively thin oxides such as the gate oxide in a MOSFET (typically 120 nm),
dry oxidation is used.
 However, for thicker oxides such as field oxides (220 nm ) in MOS integrated
circuits, oxidation in water vapor (or steam) is used.

13. Impurity Doping : Diffusion and Ion
Implantation
 Impurity doping is the introduction of controlled amounts of impurity dopants into
semiconductors.
 The impurity doping is done to mainly to change the electrical properties of the
semiconductors.
 Ex: Creation of Source/Drain Regions, Well & Substrate Contacts etc
 Two approaches for this – Diffusion & Ion Implantation
 Generally, Both diffusion and ion implantation are used in fabrication
 Typically, diffusion is used to form a deep junction (e.g., a twin well in CMOS)
whereas ion implantation is used to form a shallow junction (e.g., a source/drain
junction of a MOSFET).

14. C-> Concentration
*Note: Figure Intended only for Understanding of the Concept

15. Diffusion
 Diffusion in a semiconductor can be visualized as atomic movement of the
diffusant (dopant atoms) in the crystal lattice
 Diffusion of impurities is typically done by placing semiconductor wafers in a
carefully controlled high-temperature quartz-tube furnace and passing a gas
mixture that contains the desired dopant through it.
 The temperature usually ranges between 800°C and 1200°C for silicon
 For diffusion in silicon, boron is the most popular dopant for introducing a p-type
impurity, whereas arsenic and phosphorus are used extensively as n-type dopants.
 The final dopant concentration is greatest at surface and decreases in a Gaussian
manner deeper in the material.
 Diffusion Equation

16. *Note: Figure Intended only for Understanding of the Concept

17. Ion Implantation
 Ion implantation is the process of introduction of energetic charged particles
(dopant ions) into the substrate
 The main advantages of ion implantation are its more precise control and
reproducibility of impurity doping and its lower processing temperature compared
with those of the diffusion process.
 The energetic ions lose their energies through collision with electrons and nuclei in
the substrate and finally come to rest at some depth within the lattice.
 The average depth can be controlled by adjusting the acceleration energy. The
dopant dose can be controlled by monitoring the ion current during implantation.
 The principle side effect is the disruption or damage of the semiconductor lattice
due to ion collisions.
 Therefore, a subsequent annealing treatment is needed to remove these
damages.

18. *Note: Figure Intended only for Understanding of the Concept

19. Deposition
 Repetitive deposition of layers of a material over the complete wafer to act as
buffers for a processing step or as insulating or conducting layers.
 Si3N4 (Silver nitride) is used as sacrificial buffer material during formation of the
filed oxide
 Silver Nitride is deposited everywhere using Chemical Vapour Deposition (CVD)
 Polysilicon is deposited using a chemical deposition process, in which silane gas
flows over the heated wafer coated with SiO2 at 650 deg C. The resulting reaction
produces a non-crystalline material called Polysilicon
 To increase the conductivity of the material, deposition has to be followed by an
implantation step.
 Aluminium interconnect layers are deployed using a process called sputtering –
Aluminium is evaporated in a vacuum with the heat of evaporation delivered by
ion-beam bombarding.

20. Lithography
 Lithography is the process of transferring patterns of geometric shapes on a mask to a
thin layer of radiation-sensitive material (called resist) covering the surface of a
semiconductor wafer.
 The resist patterns defined by the lithographic process are the replicas of circuit features,
to be designed
 These patterns define the various regions in an integrated circuit such as the
implantation regions, the contact windows etc
 Techniques:
Classical: Optical Lithography or Photolithography
Advanced: Electron-beam lithography, X-ray lithography, ion-beam lithography etc

21. Lithography
 Masks
 Masks used for IC manufacturing are usually reduction reticles.
 Designers describe the circuit pattern to be generated on a CAD (Computer Aided
Design) tool.
 The digital data produced by the CAD tool, then drives a pattern generator, which
transfers the pattern directly to the (electron-sensitized*) mask.
 The patterns on a mask represent one level of an IC design.
 The composite layout is broken into mask levels that correspond to the IC process
sequence such as the isolation region on one level, the gate region on another,
and so on.
 Typically, 15-20 different mask levels are required for a complete IC process cycle
*Note: Detailed explanation on Mask can be referred from Page 411 of S.M Sze

22. Lithography (Photolithography or Optical
Lithography)
 Photoresist:
 The photoresist is a radiation-sensitive compound
 Photoresists can be classified as positive and negative, depending on how they
respond to radiation.
 For positive resists, the exposed regions become more soluble and thus are easily
removed in the development process. The net result is that the patterns formed
(also called images) in the positive resist are the same as those on the mask.
 For negative resists, the exposed regions become less soluble, and the patterns
formed in the negative resist are the reverse of the mask patterns.

23. Lithography
 Positive Photoresist
 Prior to exposure, the photosensitive compound is insoluble in the developer
solution. After exposure, the photosensitive compound absorbs radiation in the
exposed pattern areas, changes its chemical structure, and becomes soluble in the
developer solution.
 After development, the exposed areas are removed.

24. Lithography
 Negative Photoresist:
 Negative photoresists are polymers combined with a photosensitive compound.
 After exposure, the photosensitive compound absorbs the optical energy and
converts it into chemical energy to initiate a polymer linking reaction. This reaction
causes cross linking of the polymer molecules. The cross-linked polymer becomes
insoluble in the developer solution.
 After development, the unexposed areas are removed.
 Drawback: In the development process, the whole resist mass swells by absorbing
developer solvent. This swelling action limits the resolution of negative
photoresists.

25. Etching
 Once a material has been deposited, etching is used selectively to form patterns
such as wires and contact holes
 Also, the material that is not covered by photoresist are selectively removed by
etching
 Wet and Dry Etching

26. Wet-etching
 Wet-Etching Process: makes use of acid or basic solutions – depends on the
material that is to be removed
 For example,
In wafer etching, Mixture of Hydrochloric acid and Nitric acid are held in an acid
tank.
Batches of tens of wafers are introduced and are rotated to maintain uniformity-
desired thickness wafers are obtained
 In a wet chemical etching, the etch rate is generally isotropic (i.e., the lateral and
vertical etch rates are the same –
 results in undercutting of the layer underneath the mask, resulting in a loss of
resolution in the etched pattern.
 Go for dry etching

27. Dry etching
 Also called plasma etching
 A wafer is placed in etch tool processing chamber and given a negative electric
charge
 The chamber is heated to 100 deg C and filled with positively charged plasma
(usually a mixture of nitrogen, chlorine & boron trichloride)
 The opposing electric charges causes rapidly moving plasma molecules to align
themselves in vertical direction – the microscopic chemical action removes the
exposed material
 Plasma etching offers the advantage of well-defined directionality to the etching
direction

28. *Note: Figure Intended only for Understanding of the Concept

29. Single Photolithographic Cycle
*Note: Figure Intended only for Understanding of the Concept

30. 1. Oxidation Layering:
 Optional Step
 Deposit a thin layer of SiO2 over complete wafer by exposing to high purity oxygen and
hydrogen at 1000 C
 Oxide layer is used as insulation layer (& in gate formation)
2. Photoresist Coating
 Light sensitive polymer (photoresist) is evenly applied across the wafer
 Positive Photoresist or negative photoresist – what ?
3. Stepper Exposure
 A glass mask(or reticle) containing the pattern we want to transfer to the silicon is brought in
proximity to the wafer
 Mask is opaque in the region that we want to process and transparent in others (negative
photoresist) – and vice versa
 Combination of mask and wafer is now exposed to ultraviolet light
 Areas where mask is transparent become insoluble (negative photoresist) and vice-versa

31. 4. Photoresist Development and baking
 The wafers are developed in acid/base solution to remove exposed areas of photoresist
 Once the exposed photoresist is removed, the wafer is soft-baked at low temperature to harden
the remaining photoresist.
5. Acid Etching:
 Material is selectively removed from areas of wafer that are not covered by photoresist
 Accomplished through use of different types of acid and base solutions
 Choice of solvent based on material that is to be removed.
6. Spin-rinse & dry
 Special tool is used to clean the wafer with deionized water and dry it with nitrogen
 At microscopic scale, even a dust particle can destroy the circuitary
 Wafers must be constantly cleaned to avoid contamination and remove leftover of previous
steps

32. 7. Various Process steps
 The exposed area is subjected to various process steps like ion-implantation, metal deposition
etc
8. Photoresist Removal:
 A high temperature plasma is used to selectively remove the remaining photoresist without
damaging device layers.

33. Process steps for Patterning of SiO2

34. N-Well Process