Uploaded by8885684828
PPTX, PDF174 views

Module-1.pptx

The document summarizes the key steps in integrated circuit (IC) fabrication and technologies. It discusses the major fabrication processes including wafer preparation, oxidation, photolithography, diffusion, etching, deposition, ion implantation, encapsulation, metallization, and packaging. It also reviews enhancement and depletion MOS transistors and compares NMOS, PMOS, and CMOS technologies. Finally, it provides an overview of the basic MOSFET construction and operation.

Embed presentation

Download to read offline
IC Fabrication and Technologies Presented by: Dr. Vasudeva Bevara Assistant Professor Department of ECE 10-10-2023 1
Outline of IC Fabrication and Technologies 1. IC Fabrication: • Steps in Fabrication-Oxidation • Lithography • Diffusion • Ion implantation • Encapsulation and Metallization. 2. IC Technologies • Review of Enhancement and Depletion MOS transistors, • NMOS, PMOS & CMOS fabrications • Comparison of NMOS, CMOS & BiCMOS technologies. 10-10-2023 2
VLSI Design Flow 10-10-2023 3
Transistors inside IC 10-10-2023 4
IC Fabrication Process- Video from Intel 10-10-2023 5
Fabrication Processes The basic fabrication processes of the Integrated Circuits 10-10-2023 6 • Fabrication is the process of constructing an industrial product. We can also define it as a set of methods to manufacture an electronic device or product. • For example, silicon semiconductor chips, etc. In the case of metals, fabrication is a process used to convert the raw materials into the finished product.
Wafer Preparation 10-10-2023 7 • The wafer preparation is the first step for IC fabrication. It involves cutting, shaping, and polishing the wafer material to make it suitable for further fabrication. Some wafers are modified because of their sharp edges, irregular surface, and shape to convert them to the required wafer. • A wafer is a thin material used for making various Integrated circuits and transistors. Wafer acts as a base for such devices. The material of a wafer is the semiconductor, especially crystalline silicon. The silicon crystals used for the wafer manufacturing are highly pure. The process of extracting pure metal from the melt is known as a boule. The impurities are further added to the molten state of the material in a specific amount to make it n-type or p- type.
Oxidation – Create Oxide Film on Wafer Surface. 10-10-2023 8 • Oxidation is the process of adding oxygen. In a semiconductor, the oxygen and the silicon react to form silicon dioxide. The oxidation is carried out in furnaces at high temperatures up to 1250 degrees Celsius. Oxidation is classified as wet oxidation or dry oxidation. Both processes are widely used and have their own advantages and disadvantages. Wet oxidation is fast, while dry oxidation has good electrical properties. • Wet oxidation is also known as steam. Both types of oxidation have excellent electrical insulation properties. The deposition of silicon dioxide on the silicon wafer protects from many impurities. The dopants can be applied only to areas not covered with the SiO2.
Photolithography – Draw Circuit Design on Wafer 10-10-2023 9 • Next step is to draw a circuit design onto a wafer which is called the photolithography process. It is also called “photo” for short because it is similar to developing a photo taken on a film camera with semiconductors. • A photo mask functions as the film. A photo mask is a glass substrate with a computer designed circuit pattern. • In order to draw the circuit on the wafer, the photoresist, a material that responds to light is applied thinly and evenly on the oxide film previously placed on the wafer. • Now, when light transfers the patterned photo mask, the circuit is drawn on the wafer surface. Just like developing a photo, a circuit pattern is imprinted on the wafer by spraying, developer and removing unlit areas from the areas that are exposed to light.
Diffusion 10-10-2023 10 • Diffusion is a process of adding impurities atoms from a region with high concentration to a region of low concentration. The dopants or impurity atoms are added to the silicon (semiconductor material), which changes its resistivity. The process of diffusion is highly dependent on the temperature. The high doping concentration improves the conductivity of a metal. • The dopants can be of any state, solid, liquid, or gas. The preferred dopants are pentavalent impurities or n-type, such as antimony, phosphorous pentoxide, and arsine (gas). The trivalent impurities or p-type are gallium, indium, boron, etc. • The diffusion cannot be used at the later stages. It is because the number of layers formed at the successive stages of the fabrication process might not be able to resist such high temperatures. For example, • The boron or indium (trivalent impurities) diffusion on the n-type substrate forms a p-n junction. • Diffusion is also a part of the process used to fill the lattice gap in the solids.
Etching – Remove Unnecessary Materials 10-10-2023 11 • Now it is time to remove unnecessary materials from the wafer surface so that only the design pattern remains. • This is done using a liquid or gas etching technique. All unnecessary materials are selectively removed to draw the desired design. • Wet Etching: When chemical solutions are used for etching, it is called wet etching. • Dry Etching: When gas or plasma is used, it is called dry etching.
Deposition and Ion Implementation (Ion implantation) 10-10-2023 12 • Coating the thin film at a desired molecular or atomic level onto a wafer is called deposition. Since the coating is so thin, precise and sophisticated technology is required to uniformly apply the thin film on a wafer to give the semiconductor electrical characteristics. Ion implementation / Ion implantation is also required. • A semiconductor made of silicon does not conduct electricity but adding impurities. It conducts current and has conductive properties.
Encapsulation 10-10-2023 13 • The “encapsulation process”, which encapsulates packages, is a step where a semiconductor chip is wrapped with a certain material to protect it from the external environment. • It is also a step that reveals the characteristics of “light, thin, short, and small”, which packages aim for.
Metallization(Metal Wiring) 10-10-2023 14 • Metallization is also used to interconnect various components that form an Integrated circuit. The components can be resistors, capacitors, transistors, relays, etc. The metal layer is first deposited on the surface of the silicon wafer, as discussed above. After that, the required pattern or area for interconnected is etched. • Metallization is defined as the process of coating a metal layer on the metallic surface or non-metallic surface. The coating can be of aluminum, zinc, or silver. The metal coating in CMOS fabrication is aluminum, which protects the surface from external environmental factors, as dust, air, water, etc.
Packaging 10-10-2023 15 • This is the last process, the packaging process. The wafer completed through the previous steps are cut into individual semiconductor chips that can be loaded on an electronic semiconductor device. • An individual chip must have a path to exchange electrical signals with the outside and have a form to protect it from various external elements. • The wafer is cut into individual chips and the diced or saw chips are placed on the PCB board. • In the bonding step, the contact point of the semiconductor chip placed on a substrate is connected with the contact point of the substrate. Then molding finishes the chip package to its desired shape. • After final test, sealing and labeling the product name, the semiconductor chip we commonly see is completed.
Semiconductor Manufacturing Process Flow Chart 10-10-2023 16
MOSFETs 10-10-2023 17 • MOSFETs have characteristics similar to JFETs and additional characteristics that make them very useful. • There are 2 types: 1. Depletion-Type MOSFET 2. Enhancement-Type MOSFET
Depletion-Type MOSFET Construction 10-10-2023 18 • The Drain (D) and Source (S) connect to the to n-doped regions. These N-doped regions are connected via an n-channel. • This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2. • The n-doped material lies on a p-doped substrate that may have an additional terminal connection called SS.
Basic Operation 10-10-2023 19
Basic Operation 10-10-2023 20
Enhancement-Type MOSFET Construction 10-10-2023 21 • The Drain (D) and Source (S) connect to the to n- doped regions. These n-doped regions are connected via an n-channel. • The Gate (G) connects to the p-doped substrate via a thin insulating layer of SiO2. There is no channel. • The n-doped material lies on a p-doped substrate that may have an additional terminal connection called SS.
Basic Operation and Characteristics 10-10-2023 22 • If VGS is set at 0 V and a voltage applied between the drain and source of the device, the absence of an n- channel (with its generous number of free carriers) will result in a current of effectively zero amperes— quite different from the depletion- type MOSFET and JFET where ID = IDSS. • It is not sufficient to have a large accumulation of carriers (electrons) at the drain and source (due to the n-doped regions) if a path fails to exist between the two. • If both VDS and VGS is set at some positive voltage greater than 0 V, then the positive potential at the gate will pressure the holes (since like charges repel) in the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p- substrate. • However, the electrons in the p-substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer. The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal.
Continued… 10-10-2023 23 • As VGS increases in magnitude, the concentration of electrons near the SiO2 surface increases until eventually the induced n-type region can support a measurable flow between drain and source. The level of VGS that results in the significant increase in drain current is called the threshold voltage and is given the symbol VT. • Since the channel is non existent with VGS=0 V and “enhanced” by the application of a positive gate-to- source • voltage, this type of MOSFET is called an enhancement- type MOSFET.
Continued… 10-10-2023 24 • As VGS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current. • However, if we hold VGS constant and increase the level of VDS, the drain current will eventually reach a saturation level The levelling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel • By applying KVL we get - • If VGS is held fixed at some value such as 8 V and VDS is increased from 2 to 5V, the voltage will drop from -6 to -3 V. This reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons) in this region of the induced channel, causing a reduction in the effective channel width. • Eventually, the channel will be reduced to the point of pinch-off and a saturation condition will be established.
Basic Operation 10-10-2023 25
MOSFET symbols 10-10-2023 26
Transistors as Switches 10-10-2023 27 • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
MOSFET vs BJT 10-10-2023 28
N-MOS Fabrication Process 10-10-2023 29 Fig. (1) Pure Si single crystal Si-substrate Fig. (2) P-type impurity is lightly doped - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Fig. (3) SiO2 Deposited over si surface Fig. (4) Photoresist is deposited over SiO2 layer Photoresist Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N-MOS Fabrication Process 10-10-2023 Mask-1 is used to expose the SiO2 where S, D and G is to be formed. Fig. (5) Photoresist layer is exposed to UV Light through a mask - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Mask-1 Photoresist Thick SiO2 (1 µm) UV Light
N-MOS Fabrication Process 10-10-2023 Fig. (6) Etching [HF acid is used] will remove SiO2 layer which is in direct contact with etching solution Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Fig. (7) unpolymerised photoresist is also etched away [using H2SO4] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm)
N-MOS Fabrication Process 10-10-2023 Fig. (8) A thin layer of SiO2 grown over the entire chip surface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thin SiO2 (0.1 µm) Thick SiO2 (1 µm) Fig. (9) A thin layer of polysilicon is grown over the entire chip surface to form GATE Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon layer (1 – 2 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N-MOS Fabrication Process 10-10-2023 Fig. (10) A layer of photoresist is grown over polysilicon layer Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon layer Photoresist - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N-MOS Fabrication Process 10-10-2023 Mask-2 is used to deposit Polysilicon to form gate. Fig. (11) Photoresist is exposed to UV Light UV Light Mask-2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N-MOS Fabrication Process 10-10-2023 Fig. (12) Etching will remove that portion of Thin SiO2 which is not exposed to UV light Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N-MOS Fabrication Process 10-10-2023 Fig. (13) Polymerised photoresist is also stripped away Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon used as GATE (1 – 2 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N-MOS Fabrication Process 10-10-2023 Fig. (14) n+ Doping to form SOURCE and DRAIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - GA TE - - - - - - n+ SOURCE DRAIN
N-MOS Fabrication Process 10-10-2023 Fig. (15) A thick layer of SiO2 (1 µm) is again grown. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Step - Metallization
N-MOS Fabrication Process 10-10-2023 Fig. (16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and DRAIN are exposed where contact cuts are to be made - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-3 Mask-3 is used to make contact cuts for S, D and G. Photoresist UV Light Step - Metallization
N-MOS Fabrication Process 10-10-2023 Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This unpolymerised photoresist and SiO2 below it are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-3 Photoresist
N-MOS Fabrication Process 10-10-2023 Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-3 Photoresist
N-MOS Fabrication Process 10-10-2023 Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 µm thickness). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) -- - - - - - - - - - - - n+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - n+ Thick SiO2 (1 µm) Metal (1µm)
N-MOS Fabrication Process 10-10-2023 Fig. (20) Photoresist is deposited over the metal. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Metal (1µm) Photoresist
N-MOS Fabrication Process 10-10-2023 Mask-4 is used to deposit metal in contact cuts of S, D and G. Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in contact-cuts). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-4 Photoresist Metal (1µm) UV Light
N-MOS Fabrication Process 10-10-2023 Fig. (22) Photoresist and metal which is not exposed to UV light are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-4 Photoresist Metal (1µm)
N-MOS Fabrication Process 10-10-2023 Fig. (23) Final n-MOS Transistor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ SOURCE DRAIN GA TE
N-MOS Fabrication Process 10-10-2023
P-MOS Fabrication Process 10-10-2023
CMOS Fabrication 10-10-2023 • CMOS transistors are fabricated on silicon wafer • Lithography process similar to printing press • On each step, different materials are deposited or etched • Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
Inverter Cross-section 10-10-2023 • Typically use p-type substrate for nMOS transistors • Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
Well and Substrate Taps 10-10-2023 • Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection called Shottky Diode • Use heavily doped well and substrate contacts / taps n+ p substrate p+ n well A Y GND VDD n+ p+ substrate tap well tap n+ p+
Inverter Mask Set 10-10-2023 • Transistors and wires are defined by masks • Cross-section taken along dashed line GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
Detailed Mask Views 10-10-2023 • Six masks • n-well • Polysilicon • n+ diffusion • p+ diffusion • Contact • Metal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
Fabrication Steps 10-10-2023 • Start with blank wafer • Build inverter from the bottom up • First step will be to form the n-well • Cover wafer with protective layer of SiO2 (oxide) • Remove layer where n-well should be built • Implant or diffuse n dopants into exposed wafer • Strip off SiO2 p substrate
Oxidation 10-10-2023 • Grow SiO2 on top of Si wafer • 900 – 1200 C with H2O or O2 in oxidation furnace p substrate SiO2
Photoresist 10-10-2023 • Spin on photoresist • Photoresist is a light-sensitive organic polymer • Softens where exposed to light p substrate SiO2 Photoresist
Lithography 10-10-2023 • Expose photoresist through n-well mask • Strip off exposed photoresist p substrate SiO2 Photoresist
Etch 10-10-2023 • Etch oxide with hydrofluoric acid (HF) • Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed p substrate SiO2 Photoresist
Strip Photoresist 10-10-2023 • Strip off remaining photoresist • Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step p substrate SiO2
n-well 10-10-2023 • n-well is formed with diffusion or ion implantation • Diffusion • Place wafer in furnace with arsenic gas • Heat until As atoms diffuse into exposed Si • Ion Implanatation • Blast wafer with beam of As ions • Ions blocked by SiO2, only enter exposed Si n well SiO2
Strip Oxide 10-10-2023 • Strip off the remaining oxide using HF • Back to bare wafer with n-well • Subsequent steps involve similar series of steps p substrate n well
Polysilicon 10-10-2023 • Deposit very thin layer of gate oxide • < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer • Place wafer in furnace with Silane gas (SiH4) • Forms many small crystals called polysilicon • Heavily doped to be good conductor Thin gate oxide Polysilicon p substrate n well
Polysilicon Patterning 10-10-2023 • Use same lithography process to pattern polysilicon Polysilicon p substrate Thin gate oxide Polysilicon n well
Self-Aligned Process 10-10-2023 • Use oxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact p substrate n well
N-diffusion 10-10-2023 • Pattern oxide and form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing p substrate n well n+ Diffusion
N-diffusion cont. 10-10-2023 • Historically dopants were diffused • Usually, ion implantation today • But regions are still called diffusion n well p substrate n+ n+ n+
N-diffusion cont. 10-10-2023 • Strip off oxide to complete patterning step n well p substrate n+ n+ n+
P-Diffusion 10-10-2023 • Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p substrate n well n+ n+ n+ p+ p+ p+
Contacts 10-10-2023 • Now we need to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed p substrate Thick field oxide n well n+ n+ n+ p+ p+ p+ Contact
Metalization 10-10-2023 • Sputter on aluminum over whole wafer • Pattern to remove excess metal, leaving wires p substrate Metal Thick field oxide n well n+ n+ n+ p+ p+ p+ Metal
Comparison of NMOS, CMOS & BiCMOS technologies 10-10-2023 NMOS (N-channel Metal-Oxide-Semiconductor), CMOS (Complementary Metal-Oxide- Semiconductor), and BiCMOS (Bipolar-CMOS) are three different semiconductor technologies used in integrated circuits. They each have their own characteristics, advantages, and disadvantages. Let's compare these technologies in various aspects: 1.Transistor Types: 1. NMOS: Uses only N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). 2. CMOS: Combines both N-channel and P-channel MOSFETs to achieve complementary logic. 3. BiCMOS: Integrates bipolar transistors (BJTs) along with CMOS transistors. 2.Power Consumption: 1. NMOS: Consumes more power when idle due to leakage current. 2. CMOS: Consumes less static power because it doesn't have a direct path from VDD to ground when idle. 3. BiCMOS: Consumes more power than pure CMOS due to the presence of bipolar transistors.
Comparison of NMOS, CMOS & BiCMOS technologies 10-10-2023 3.Speed: 1. NMOS: Faster switching compared to CMOS but slower than BiCMOS. 2. CMOS: Slower switching than NMOS but more power-efficient. 3. BiCMOS: Faster switching than both NMOS and CMOS. 4.Noise Margin: 1. NMOS: Lower noise margin due to its higher susceptibility to noise. 2. CMOS: Offers good noise immunity due to complementary operation. 3. BiCMOS: Similar noise immunity to CMOS. 5.Integration Density: 1. NMOS: Lower integration density due to larger transistor sizes and higher power consumption. 2. CMOS: Offers high integration density and is widely used in modern VLSI circuits. 3. BiCMOS: Has a moderate integration density.
Comparison of NMOS, CMOS & BiCMOS technologies 10-10-2023 6.Complexity and Cost: 1. NMOS: Simple to fabricate but consumes more power. 2. CMOS: Cost-effective due to its widespread use and low power consumption. 3. BiCMOS: More complex and costly to manufacture than pure CMOS. 7.Standby Power Consumption: 1. NMOS: High standby power consumption. 2. CMOS: Low standby power consumption. 3. BiCMOS: Moderate standby power consumption, better than NMOS but not as low as CMOS. 8.Applications: 1.NMOS: Older technology, less common today, used in some specific analog and mixed-signal applications. 2.CMOS: Ubiquitous in digital and mixed-signal ICs, such as microcontrollers, processors, and memory. 3.BiCMOS: Used in applications that require a combination of high-speed analog and digital circuitry, like RF and high-frequency mixed-signal designs.
10/10/2023 74

More Related Content

PPTX
Fabrication steps of IC
byGowri Kishore
 
PPTX
CMOS FABRICATION - VLSI NMOS, PMOS, CMOS FABRICATION
byprithivr1
 
PDF
a159022549632.pdfa159022549632.pdfa159022549632.pdfa159022549632.pdf
byAnbazhaganSelvanatha
 
PDF
VLSI-Design.pdf
byAcademicICECE
 
PDF
CMOS VLSI Fabrication Technology: From Lithography to Advanced CMOS Processes
byGS Virdi
 
PDF
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
byUsha Mehta
 
PPTX
IC design: Microelectronic Technology.pptx
bySarmistaSengupta1
 
PPTX
Fabrication process flow
bySudhanshu Janwadkar
 
Fabrication steps of IC
byGowri Kishore
 
CMOS FABRICATION - VLSI NMOS, PMOS, CMOS FABRICATION
byprithivr1
 
a159022549632.pdfa159022549632.pdfa159022549632.pdfa159022549632.pdf
byAnbazhaganSelvanatha
 
VLSI-Design.pdf
byAcademicICECE
 
CMOS VLSI Fabrication Technology: From Lithography to Advanced CMOS Processes
byGS Virdi
 
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
byUsha Mehta
 
IC design: Microelectronic Technology.pptx
bySarmistaSengupta1
 
Fabrication process flow
bySudhanshu Janwadkar
 

Similar to Module-1.pptx

PDF
Chapter 5 - IC Fabrication and Process Technology.pdf
byUmaa Devi
 
PDF
Very Large Scale Integration-UNIT-I-RECW.pdf
bySarankumarThoram
 
PPTX
Ue 1(v sem)
byAnkita Jaiswal
 
PPTX
Introduction To Microelectronics
byAnkita Jaiswal
 
PPT
CMOS Topic 2 -manufacturing_process
byIkhwan_Fakrudin
 
PPTX
VLSI_chapter1.pptx
byroyal sethi
 
PPT
Vlsi 2
byidris01111
 
PPTX
integrated circuit febrication
bysky lark
 
PDF
Vlsi design notes(1st unit) according to vtu syllabus.(BE)
byinstrumentation_vtu
 
PPTX
processes involved in the preparation of semiconductor wafers
byVijaySingh350104
 
PPTX
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptx
by8885684828
 
PDF
microfabrication-180118174836 (1).pdf
bySenguttuvan Nagarajan
 
PPTX
Chapter 1-IC Fabrication.pptx
byKarthik Prof.
 
PPTX
Fabrication of Semiconductors
byaman1312
 
PPTX
nmos_fabrication_process_20260130071314.pptx
byAchyuthGoud1
 
PDF
vlsi12312313123123123123123123123123123123.pdf
byvsrkrishna8303
 
PPTX
Unit-6 Semiconductor Manufacturing Process.pptx
bySatish Chandra
 
PPTX
unit-6semiconductormanufacturingprocess-230917101730-af41af44.pptx
byprofmkv
 
PPTX
nufacturingprocessinsemiconductorand processing.pptx
byprofmkv
 
PPTX
All_Processes_ftcycyjvydtctchchhchcycycy.pptx
byPiyushAade
 
Chapter 5 - IC Fabrication and Process Technology.pdf
byUmaa Devi
 
Very Large Scale Integration-UNIT-I-RECW.pdf
bySarankumarThoram
 
Ue 1(v sem)
byAnkita Jaiswal
 
Introduction To Microelectronics
byAnkita Jaiswal
 
CMOS Topic 2 -manufacturing_process
byIkhwan_Fakrudin
 
VLSI_chapter1.pptx
byroyal sethi
 
Vlsi 2
byidris01111
 
integrated circuit febrication
bysky lark
 
Vlsi design notes(1st unit) according to vtu syllabus.(BE)
byinstrumentation_vtu
 
processes involved in the preparation of semiconductor wafers
byVijaySingh350104
 
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptx
by8885684828
 
microfabrication-180118174836 (1).pdf
bySenguttuvan Nagarajan
 
Chapter 1-IC Fabrication.pptx
byKarthik Prof.
 
Fabrication of Semiconductors
byaman1312
 
nmos_fabrication_process_20260130071314.pptx
byAchyuthGoud1
 
vlsi12312313123123123123123123123123123123.pdf
byvsrkrishna8303
 
Unit-6 Semiconductor Manufacturing Process.pptx
bySatish Chandra
 
unit-6semiconductormanufacturingprocess-230917101730-af41af44.pptx
byprofmkv
 
nufacturingprocessinsemiconductorand processing.pptx
byprofmkv
 
All_Processes_ftcycyjvydtctchchhchcycycy.pptx
byPiyushAade
 

More from 8885684828

PPT
ASCIC.ppt
by8885684828
 
PDF
Module-4.pdf
by8885684828
 
PPTX
vlsi-unit-3-ppt.pptx
by8885684828
 
PPTX
mosfet ppt.pptx
by8885684828
 
PPTX
denoising.pptx
by8885684828
 
PPT
verilog basics.ppt
by8885684828
 
PPT
Basic VLSI.ppt
by8885684828
 
PPTX
literature.pptx
by8885684828
 
PDF
Module-5A.pdf
by8885684828
 
PPT
LPVLSI.ppt
by8885684828
 
PDF
water verflow.pdf
by8885684828
 
PPTX
PROJECT PPT (1).pptx
by8885684828
 
ASCIC.ppt
by8885684828
 
Module-4.pdf
by8885684828
 
vlsi-unit-3-ppt.pptx
by8885684828
 
mosfet ppt.pptx
by8885684828
 
denoising.pptx
by8885684828
 
verilog basics.ppt
by8885684828
 
Basic VLSI.ppt
by8885684828
 
literature.pptx
by8885684828
 
Module-5A.pdf
by8885684828
 
LPVLSI.ppt
by8885684828
 
water verflow.pdf
by8885684828
 
PROJECT PPT (1).pptx
by8885684828
 

Recently uploaded

PPTX
GET 211- Computing and Software Engineering (1).pptx
byfestusdaniel142
 
PPT
Ceramic Matrix Composites Slide from Composite Materials
byUsman635773
 
PDF
AWS Re:Invent 2025 Recap by FivexL - Guilherme, Vladimir, Andrey
byAndrey Devyatkin
 
PPTX
Why TPM Succeeds in Some Plants and Struggles in Others | MaintWiz
byMaintWiz Technologies Private Limited
 
PPTX
ISO 13485.2016 Awareness's Training material
byPrakashSivan
 
PDF
Shear Strength of Soil (Direct shear test).pdf
byMahmoodKhalid11
 
PPTX
Basic Volume Mass Relationship and unit weight as function of volumetric wate...
byMahmoodKhalid11
 
PDF
(en/zhTW) Heterogeneous System Architecture: Design & Performance
byDanny Jiang
 
PDF
Industrial Tools Manufacturers In India : Torso Tools
bytorsotools8
 
PDF
Module 4 python programming-1BPLCK105B-2025 by Dr.SV.pdf
bySURESHA V
 
PDF
Plasticity and Structure of Soil/Atterberg Limits.pdf
byMahmoodKhalid11
 
PPTX
Fitting Infiltration Models to Infiltration using Excel (1).pptx
byTomNickoRivera1
 
PPTX
Designing Work for Humans, Not Machines: Human-Centered Maintenance Excellence
byMaintWiz Technologies Private Limited
 
PPT
Integer , Goal and Non linear Programming Model
byOcheriCyril2
 
PPTX
Introduction to AI and Applications Module-4.pptx
byKalaiselviSubramania2
 
PDF
Basics of Electronics Task by Vivaan Jo Varghese.pdf
byVivaan Jo Varghese
 
PPTX
ME3592 - Metrology and Measurements - Unit - 1 - Lecture Notes
bypprakash21252
 
PPTX
operating_systems.pptx m,nm,nm,n,nm,n,nm,nikl
bykirthigaaiml
 
PDF
Infinite Sequence and Series: It Includes basic Sequence and Series
byDynamicDomain1
 
PPTX
How Does LNG Regasification Work | INOXCVA
byINOXCVA
 
GET 211- Computing and Software Engineering (1).pptx
byfestusdaniel142
 
Ceramic Matrix Composites Slide from Composite Materials
byUsman635773
 
AWS Re:Invent 2025 Recap by FivexL - Guilherme, Vladimir, Andrey
byAndrey Devyatkin
 
Why TPM Succeeds in Some Plants and Struggles in Others | MaintWiz
byMaintWiz Technologies Private Limited
 
ISO 13485.2016 Awareness's Training material
byPrakashSivan
 
Shear Strength of Soil (Direct shear test).pdf
byMahmoodKhalid11
 
Basic Volume Mass Relationship and unit weight as function of volumetric wate...
byMahmoodKhalid11
 
(en/zhTW) Heterogeneous System Architecture: Design & Performance
byDanny Jiang
 
Industrial Tools Manufacturers In India : Torso Tools
bytorsotools8
 
Module 4 python programming-1BPLCK105B-2025 by Dr.SV.pdf
bySURESHA V
 
Plasticity and Structure of Soil/Atterberg Limits.pdf
byMahmoodKhalid11
 
Fitting Infiltration Models to Infiltration using Excel (1).pptx
byTomNickoRivera1
 
Designing Work for Humans, Not Machines: Human-Centered Maintenance Excellence
byMaintWiz Technologies Private Limited
 
Integer , Goal and Non linear Programming Model
byOcheriCyril2
 
Introduction to AI and Applications Module-4.pptx
byKalaiselviSubramania2
 
Basics of Electronics Task by Vivaan Jo Varghese.pdf
byVivaan Jo Varghese
 
ME3592 - Metrology and Measurements - Unit - 1 - Lecture Notes
bypprakash21252
 
operating_systems.pptx m,nm,nm,n,nm,n,nm,nikl
bykirthigaaiml
 
Infinite Sequence and Series: It Includes basic Sequence and Series
byDynamicDomain1
 
How Does LNG Regasification Work | INOXCVA
byINOXCVA
 

Module-1.pptx

  • 1.
    IC Fabrication andTechnologies Presented by: Dr. Vasudeva Bevara Assistant Professor Department of ECE 10-10-2023 1
  • 2.
    Outline of ICFabrication and Technologies 1. IC Fabrication: • Steps in Fabrication-Oxidation • Lithography • Diffusion • Ion implantation • Encapsulation and Metallization. 2. IC Technologies • Review of Enhancement and Depletion MOS transistors, • NMOS, PMOS & CMOS fabrications • Comparison of NMOS, CMOS & BiCMOS technologies. 10-10-2023 2
  • 3.
  • 4.
  • 5.
    IC Fabrication Process-Video from Intel 10-10-2023 5
  • 6.
    Fabrication Processes The basicfabrication processes of the Integrated Circuits 10-10-2023 6 • Fabrication is the process of constructing an industrial product. We can also define it as a set of methods to manufacture an electronic device or product. • For example, silicon semiconductor chips, etc. In the case of metals, fabrication is a process used to convert the raw materials into the finished product.
  • 7.
    Wafer Preparation 10-10-2023 7 •The wafer preparation is the first step for IC fabrication. It involves cutting, shaping, and polishing the wafer material to make it suitable for further fabrication. Some wafers are modified because of their sharp edges, irregular surface, and shape to convert them to the required wafer. • A wafer is a thin material used for making various Integrated circuits and transistors. Wafer acts as a base for such devices. The material of a wafer is the semiconductor, especially crystalline silicon. The silicon crystals used for the wafer manufacturing are highly pure. The process of extracting pure metal from the melt is known as a boule. The impurities are further added to the molten state of the material in a specific amount to make it n-type or p- type.
  • 8.
    Oxidation – CreateOxide Film on Wafer Surface. 10-10-2023 8 • Oxidation is the process of adding oxygen. In a semiconductor, the oxygen and the silicon react to form silicon dioxide. The oxidation is carried out in furnaces at high temperatures up to 1250 degrees Celsius. Oxidation is classified as wet oxidation or dry oxidation. Both processes are widely used and have their own advantages and disadvantages. Wet oxidation is fast, while dry oxidation has good electrical properties. • Wet oxidation is also known as steam. Both types of oxidation have excellent electrical insulation properties. The deposition of silicon dioxide on the silicon wafer protects from many impurities. The dopants can be applied only to areas not covered with the SiO2.
  • 9.
    Photolithography – DrawCircuit Design on Wafer 10-10-2023 9 • Next step is to draw a circuit design onto a wafer which is called the photolithography process. It is also called “photo” for short because it is similar to developing a photo taken on a film camera with semiconductors. • A photo mask functions as the film. A photo mask is a glass substrate with a computer designed circuit pattern. • In order to draw the circuit on the wafer, the photoresist, a material that responds to light is applied thinly and evenly on the oxide film previously placed on the wafer. • Now, when light transfers the patterned photo mask, the circuit is drawn on the wafer surface. Just like developing a photo, a circuit pattern is imprinted on the wafer by spraying, developer and removing unlit areas from the areas that are exposed to light.
  • 10.
    Diffusion 10-10-2023 10 • Diffusionis a process of adding impurities atoms from a region with high concentration to a region of low concentration. The dopants or impurity atoms are added to the silicon (semiconductor material), which changes its resistivity. The process of diffusion is highly dependent on the temperature. The high doping concentration improves the conductivity of a metal. • The dopants can be of any state, solid, liquid, or gas. The preferred dopants are pentavalent impurities or n-type, such as antimony, phosphorous pentoxide, and arsine (gas). The trivalent impurities or p-type are gallium, indium, boron, etc. • The diffusion cannot be used at the later stages. It is because the number of layers formed at the successive stages of the fabrication process might not be able to resist such high temperatures. For example, • The boron or indium (trivalent impurities) diffusion on the n-type substrate forms a p-n junction. • Diffusion is also a part of the process used to fill the lattice gap in the solids.
  • 11.
    Etching – RemoveUnnecessary Materials 10-10-2023 11 • Now it is time to remove unnecessary materials from the wafer surface so that only the design pattern remains. • This is done using a liquid or gas etching technique. All unnecessary materials are selectively removed to draw the desired design. • Wet Etching: When chemical solutions are used for etching, it is called wet etching. • Dry Etching: When gas or plasma is used, it is called dry etching.
  • 12.
    Deposition and IonImplementation (Ion implantation) 10-10-2023 12 • Coating the thin film at a desired molecular or atomic level onto a wafer is called deposition. Since the coating is so thin, precise and sophisticated technology is required to uniformly apply the thin film on a wafer to give the semiconductor electrical characteristics. Ion implementation / Ion implantation is also required. • A semiconductor made of silicon does not conduct electricity but adding impurities. It conducts current and has conductive properties.
  • 13.
    Encapsulation 10-10-2023 13 • The“encapsulation process”, which encapsulates packages, is a step where a semiconductor chip is wrapped with a certain material to protect it from the external environment. • It is also a step that reveals the characteristics of “light, thin, short, and small”, which packages aim for.
  • 14.
    Metallization(Metal Wiring) 10-10-2023 14 •Metallization is also used to interconnect various components that form an Integrated circuit. The components can be resistors, capacitors, transistors, relays, etc. The metal layer is first deposited on the surface of the silicon wafer, as discussed above. After that, the required pattern or area for interconnected is etched. • Metallization is defined as the process of coating a metal layer on the metallic surface or non-metallic surface. The coating can be of aluminum, zinc, or silver. The metal coating in CMOS fabrication is aluminum, which protects the surface from external environmental factors, as dust, air, water, etc.
  • 15.
    Packaging 10-10-2023 15 • Thisis the last process, the packaging process. The wafer completed through the previous steps are cut into individual semiconductor chips that can be loaded on an electronic semiconductor device. • An individual chip must have a path to exchange electrical signals with the outside and have a form to protect it from various external elements. • The wafer is cut into individual chips and the diced or saw chips are placed on the PCB board. • In the bonding step, the contact point of the semiconductor chip placed on a substrate is connected with the contact point of the substrate. Then molding finishes the chip package to its desired shape. • After final test, sealing and labeling the product name, the semiconductor chip we commonly see is completed.
  • 16.
    Semiconductor Manufacturing ProcessFlow Chart 10-10-2023 16
  • 17.
    MOSFETs 10-10-2023 17 • MOSFETshave characteristics similar to JFETs and additional characteristics that make them very useful. • There are 2 types: 1. Depletion-Type MOSFET 2. Enhancement-Type MOSFET
  • 18.
    Depletion-Type MOSFET Construction 10-10-202318 • The Drain (D) and Source (S) connect to the to n-doped regions. These N-doped regions are connected via an n-channel. • This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2. • The n-doped material lies on a p-doped substrate that may have an additional terminal connection called SS.
  • 19.
  • 20.
  • 21.
    Enhancement-Type MOSFET Construction 10-10-202321 • The Drain (D) and Source (S) connect to the to n- doped regions. These n-doped regions are connected via an n-channel. • The Gate (G) connects to the p-doped substrate via a thin insulating layer of SiO2. There is no channel. • The n-doped material lies on a p-doped substrate that may have an additional terminal connection called SS.
  • 22.
    Basic Operation andCharacteristics 10-10-2023 22 • If VGS is set at 0 V and a voltage applied between the drain and source of the device, the absence of an n- channel (with its generous number of free carriers) will result in a current of effectively zero amperes— quite different from the depletion- type MOSFET and JFET where ID = IDSS. • It is not sufficient to have a large accumulation of carriers (electrons) at the drain and source (due to the n-doped regions) if a path fails to exist between the two. • If both VDS and VGS is set at some positive voltage greater than 0 V, then the positive potential at the gate will pressure the holes (since like charges repel) in the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p- substrate. • However, the electrons in the p-substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer. The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal.
  • 23.
    Continued… 10-10-2023 23 • AsVGS increases in magnitude, the concentration of electrons near the SiO2 surface increases until eventually the induced n-type region can support a measurable flow between drain and source. The level of VGS that results in the significant increase in drain current is called the threshold voltage and is given the symbol VT. • Since the channel is non existent with VGS=0 V and “enhanced” by the application of a positive gate-to- source • voltage, this type of MOSFET is called an enhancement- type MOSFET.
  • 24.
    Continued… 10-10-2023 24 • AsVGS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current. • However, if we hold VGS constant and increase the level of VDS, the drain current will eventually reach a saturation level The levelling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel • By applying KVL we get - • If VGS is held fixed at some value such as 8 V and VDS is increased from 2 to 5V, the voltage will drop from -6 to -3 V. This reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons) in this region of the induced channel, causing a reduction in the effective channel width. • Eventually, the channel will be reduced to the point of pinch-off and a saturation condition will be established.
  • 25.
  • 26.
  • 27.
    Transistors as Switches 10-10-202327 • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
  • 28.
  • 29.
    N-MOS Fabrication Process 10-10-202329 Fig. (1) Pure Si single crystal Si-substrate Fig. (2) P-type impurity is lightly doped - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Fig. (3) SiO2 Deposited over si surface Fig. (4) Photoresist is deposited over SiO2 layer Photoresist Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • 30.
    N-MOS Fabrication Process 10-10-2023 Mask-1is used to expose the SiO2 where S, D and G is to be formed. Fig. (5) Photoresist layer is exposed to UV Light through a mask - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Mask-1 Photoresist Thick SiO2 (1 µm) UV Light
  • 31.
    N-MOS Fabrication Process 10-10-2023 Fig.(6) Etching [HF acid is used] will remove SiO2 layer which is in direct contact with etching solution Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Fig. (7) unpolymerised photoresist is also etched away [using H2SO4] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm)
  • 32.
    N-MOS Fabrication Process 10-10-2023 Fig.(8) A thin layer of SiO2 grown over the entire chip surface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thin SiO2 (0.1 µm) Thick SiO2 (1 µm) Fig. (9) A thin layer of polysilicon is grown over the entire chip surface to form GATE Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon layer (1 – 2 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • 33.
    N-MOS Fabrication Process 10-10-2023 Fig.(10) A layer of photoresist is grown over polysilicon layer Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon layer Photoresist - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • 34.
    N-MOS Fabrication Process 10-10-2023 Mask-2is used to deposit Polysilicon to form gate. Fig. (11) Photoresist is exposed to UV Light UV Light Mask-2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • 35.
    N-MOS Fabrication Process 10-10-2023 Fig.(12) Etching will remove that portion of Thin SiO2 which is not exposed to UV light Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • 36.
    N-MOS Fabrication Process 10-10-2023 Fig.(13) Polymerised photoresist is also stripped away Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) Polysilicon used as GATE (1 – 2 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • 37.
    N-MOS Fabrication Process 10-10-2023 Fig.(14) n+ Doping to form SOURCE and DRAIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) Thin SiO2 (0.1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - GA TE - - - - - - n+ SOURCE DRAIN
  • 38.
    N-MOS Fabrication Process 10-10-2023 Fig.(15) A thick layer of SiO2 (1 µm) is again grown. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Step - Metallization
  • 39.
    N-MOS Fabrication Process 10-10-2023 Fig.(16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and DRAIN are exposed where contact cuts are to be made - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-3 Mask-3 is used to make contact cuts for S, D and G. Photoresist UV Light Step - Metallization
  • 40.
    N-MOS Fabrication Process 10-10-2023 Fig.(17) The region of photoresist which is not exposed by UV light will become soft. This unpolymerised photoresist and SiO2 below it are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-3 Photoresist
  • 41.
    N-MOS Fabrication Process 10-10-2023 Fig.(18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-3 Photoresist
  • 42.
    N-MOS Fabrication Process 10-10-2023 Fig.(19) Metal (aluminium) is deposited over the surface of whole chip (1 µm thickness). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) -- - - - - - - - - - - - n+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - n+ Thick SiO2 (1 µm) Metal (1µm)
  • 43.
    N-MOS Fabrication Process 10-10-2023 Fig.(20) Photoresist is deposited over the metal. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Metal (1µm) Photoresist
  • 44.
    N-MOS Fabrication Process 10-10-2023 Mask-4is used to deposit metal in contact cuts of S, D and G. Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in contact-cuts). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-4 Photoresist Metal (1µm) UV Light
  • 45.
    N-MOS Fabrication Process 10-10-2023 Fig.(22) Photoresist and metal which is not exposed to UV light are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Thick SiO2 (1 µm) Mask-4 Photoresist Metal (1µm)
  • 46.
    N-MOS Fabrication Process 10-10-2023 Fig.(23) Final n-MOS Transistor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ SOURCE DRAIN GA TE
  • 47.
  • 48.
  • 49.
    CMOS Fabrication 10-10-2023 • CMOStransistors are fabricated on silicon wafer • Lithography process similar to printing press • On each step, different materials are deposited or etched • Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
  • 50.
    Inverter Cross-section 10-10-2023 • Typicallyuse p-type substrate for nMOS transistors • Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
  • 51.
    Well and SubstrateTaps 10-10-2023 • Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection called Shottky Diode • Use heavily doped well and substrate contacts / taps n+ p substrate p+ n well A Y GND VDD n+ p+ substrate tap well tap n+ p+
  • 52.
    Inverter Mask Set 10-10-2023 •Transistors and wires are defined by masks • Cross-section taken along dashed line GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
  • 53.
    Detailed Mask Views 10-10-2023 •Six masks • n-well • Polysilicon • n+ diffusion • p+ diffusion • Contact • Metal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
  • 54.
    Fabrication Steps 10-10-2023 • Startwith blank wafer • Build inverter from the bottom up • First step will be to form the n-well • Cover wafer with protective layer of SiO2 (oxide) • Remove layer where n-well should be built • Implant or diffuse n dopants into exposed wafer • Strip off SiO2 p substrate
  • 55.
    Oxidation 10-10-2023 • Grow SiO2on top of Si wafer • 900 – 1200 C with H2O or O2 in oxidation furnace p substrate SiO2
  • 56.
    Photoresist 10-10-2023 • Spin onphotoresist • Photoresist is a light-sensitive organic polymer • Softens where exposed to light p substrate SiO2 Photoresist
  • 57.
    Lithography 10-10-2023 • Expose photoresistthrough n-well mask • Strip off exposed photoresist p substrate SiO2 Photoresist
  • 58.
    Etch 10-10-2023 • Etch oxidewith hydrofluoric acid (HF) • Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed p substrate SiO2 Photoresist
  • 59.
    Strip Photoresist 10-10-2023 • Stripoff remaining photoresist • Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step p substrate SiO2
  • 60.
    n-well 10-10-2023 • n-well isformed with diffusion or ion implantation • Diffusion • Place wafer in furnace with arsenic gas • Heat until As atoms diffuse into exposed Si • Ion Implanatation • Blast wafer with beam of As ions • Ions blocked by SiO2, only enter exposed Si n well SiO2
  • 61.
    Strip Oxide 10-10-2023 • Stripoff the remaining oxide using HF • Back to bare wafer with n-well • Subsequent steps involve similar series of steps p substrate n well
  • 62.
    Polysilicon 10-10-2023 • Deposit verythin layer of gate oxide • < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer • Place wafer in furnace with Silane gas (SiH4) • Forms many small crystals called polysilicon • Heavily doped to be good conductor Thin gate oxide Polysilicon p substrate n well
  • 63.
    Polysilicon Patterning 10-10-2023 • Usesame lithography process to pattern polysilicon Polysilicon p substrate Thin gate oxide Polysilicon n well
  • 64.
    Self-Aligned Process 10-10-2023 • Useoxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact p substrate n well
  • 65.
    N-diffusion 10-10-2023 • Pattern oxideand form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing p substrate n well n+ Diffusion
  • 66.
    N-diffusion cont. 10-10-2023 • Historicallydopants were diffused • Usually, ion implantation today • But regions are still called diffusion n well p substrate n+ n+ n+
  • 67.
    N-diffusion cont. 10-10-2023 • Stripoff oxide to complete patterning step n well p substrate n+ n+ n+
  • 68.
    P-Diffusion 10-10-2023 • Similar setof steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p substrate n well n+ n+ n+ p+ p+ p+
  • 69.
    Contacts 10-10-2023 • Now weneed to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed p substrate Thick field oxide n well n+ n+ n+ p+ p+ p+ Contact
  • 70.
    Metalization 10-10-2023 • Sputter onaluminum over whole wafer • Pattern to remove excess metal, leaving wires p substrate Metal Thick field oxide n well n+ n+ n+ p+ p+ p+ Metal
  • 71.
    Comparison of NMOS,CMOS & BiCMOS technologies 10-10-2023 NMOS (N-channel Metal-Oxide-Semiconductor), CMOS (Complementary Metal-Oxide- Semiconductor), and BiCMOS (Bipolar-CMOS) are three different semiconductor technologies used in integrated circuits. They each have their own characteristics, advantages, and disadvantages. Let's compare these technologies in various aspects: 1.Transistor Types: 1. NMOS: Uses only N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). 2. CMOS: Combines both N-channel and P-channel MOSFETs to achieve complementary logic. 3. BiCMOS: Integrates bipolar transistors (BJTs) along with CMOS transistors. 2.Power Consumption: 1. NMOS: Consumes more power when idle due to leakage current. 2. CMOS: Consumes less static power because it doesn't have a direct path from VDD to ground when idle. 3. BiCMOS: Consumes more power than pure CMOS due to the presence of bipolar transistors.
  • 72.
    Comparison of NMOS,CMOS & BiCMOS technologies 10-10-2023 3.Speed: 1. NMOS: Faster switching compared to CMOS but slower than BiCMOS. 2. CMOS: Slower switching than NMOS but more power-efficient. 3. BiCMOS: Faster switching than both NMOS and CMOS. 4.Noise Margin: 1. NMOS: Lower noise margin due to its higher susceptibility to noise. 2. CMOS: Offers good noise immunity due to complementary operation. 3. BiCMOS: Similar noise immunity to CMOS. 5.Integration Density: 1. NMOS: Lower integration density due to larger transistor sizes and higher power consumption. 2. CMOS: Offers high integration density and is widely used in modern VLSI circuits. 3. BiCMOS: Has a moderate integration density.
  • 73.
    Comparison of NMOS,CMOS & BiCMOS technologies 10-10-2023 6.Complexity and Cost: 1. NMOS: Simple to fabricate but consumes more power. 2. CMOS: Cost-effective due to its widespread use and low power consumption. 3. BiCMOS: More complex and costly to manufacture than pure CMOS. 7.Standby Power Consumption: 1. NMOS: High standby power consumption. 2. CMOS: Low standby power consumption. 3. BiCMOS: Moderate standby power consumption, better than NMOS but not as low as CMOS. 8.Applications: 1.NMOS: Older technology, less common today, used in some specific analog and mixed-signal applications. 2.CMOS: Ubiquitous in digital and mixed-signal ICs, such as microcontrollers, processors, and memory. 3.BiCMOS: Used in applications that require a combination of high-speed analog and digital circuitry, like RF and high-frequency mixed-signal designs.
  • 74.