1. The document discusses the basic concepts of diodes and MOS transistors, including their structures, operations, and issues related to submicron MOS transistors. It covers topics such as p-type and n-type semiconductors, the PN junction, biasing of diodes, ideal and real diode equations, MOS transistor structure and operation, and effects in submicron transistors like channel length modulation and velocity saturation. 2. Design abstraction levels are introduced to efficiently design complex ICs through successive simplification and representation of circuits from the system level down to the transistor and layout levels. 3. MOS transistor models like the switch model and SPICE models are presented to simulate and analyze

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EE603EE603 –– CMOS ICCMOS IC
DESIGNDESIGN
TOPIC 3TOPIC 3 –– THE DEVICETHE DEVICE
Faizah Amir
POLISAS
TE
KN
OLOG
I
TE
RAS
PEM
BAN
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NAN
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LESSON LEARNING OUTCOME
At the end of this session, you should be
able to:
1. explain the diode basic concept.
2. explain the design abstraction level.
3. explain MOS transistor theory.
4. explain the issues related to submicron
MOS transistor.
5. apply MOS transistor theory in MOS
switch model.
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Electrons and Holes
• Atoms with one extra
valence electron than silicon
are used to produce "n-type"
semiconductor material.
•Atoms with one less
valence electron result in
"p-type" material.
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• P-type material has large
amount of acceptor ions and
corresponding number of
holes.
• N-type material has large amount
of donor ions and corresponding
number of electrons.
Electrons and Holes
N-type (negative) P-type (positive)
Dopant
Group V
(e.g. Arsenic, Antimony and
Phosphorus)
Group III
(e.g. Indium, Gallium
and Boron)
Bonds Excess Electrons
Missing Electrons
(Holes)
Majority Carriers Electrons Hole
Minority Carriers Holes Electrons
Properties of extrinsic semiconductor in silicon
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N-Type & P-Type Semiconductor
• P-type material has majority of
holes and a few electrons.
• Holes are called majority carriers
and thermally generated electrons
are called minority carriers.
• N-type material has majority of
electrons and a few holes.
• Electrons are called majority
carriers and holes are called minority
carriers.
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P-N Junction Diode
• When the p-type and n-type semiconductors are joined , there will be a flow of electrons
from n-type material to the p-type material, due to the diffusion process.
• Some of the free electrons in the n-type that diffuse across the junction and combine
with holes to form negative ions in p-side and leaves behind positive ions on the n-side.
• The combining of electrons and holes depletes the holes in the p-type and electrons in the
n-type near the junction.
• The region near the junction acts as a barrier which blocks movement of carriers. This
region which blocks the movement of charge carriers, is called depletion region.
Formation of a P-N junction
Diode SymbolP-N Junction
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Biasing The P-N Junction Diode
If a reverse bias voltage is applied
across the P-N junction, the
depletion region expands, further
resisting any current through it.
If a forward bias voltage is applied
across the P-N junction, the
depletion region will collapse and
become thinner, so that the diode
becomes less resistive to current
through it.
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Diode in IC
p
n
n
p
A
B
Al
One-dimensional representation
Diode Symbol
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Ideal Diode Equation
φT - thermal voltage and is equal to
26 mV at room temperature.
IS - saturation current of the diode
(constant value) and determined
empirically
The ideal diode equation relates the current through the
diode (ID) to the diode bias voltage VD.
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Ideal Diode Equation
Simplification:
VD / φφφφT
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Ideal Diode Equation
An ideal diode would show an abrupt
transition from perfectly conducting (diode
is short circuit) to perfectly non-conducting
(diode is open circuit) states at 0V.
I
V
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Ideal Diode Equation
Diode acts as switch since:
In the ON state, diode is short circuit and
in the OFF state, diode is open circuit.
I
V
ONOFF
Symbol for ideal diode
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Real Diode
Diodes formed in different materials have
different cut-in voltages.
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MOS Transistor
• MOS transistor is known as MOSFET (metal
oxide semiconductor field-effect transistor).
• MOSFET that is widely used in integrated
circuit is the CMOS technology (combination
of NMOS and PMOS).
• MOSFET is widely used nowadays in
electronic equipment, e.g. mobile phone,
computer, medical electronic equipment, etc.
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MOSFET

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MOS Transistor
MOS Transistor Cross-Section :
MOS Transistor
Symbol :
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p-substratep-substrate
N-well
Or VG < VT
MOSFET Operation :
Cutoff
The channel is not established and the device is in a non-
conducting state (also called cutoff or sub-threshold).
Depletion region
VD Small
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Channel Existence
• At VGS = VT, the positive gate voltage causes positive charge to accumulate
on the gate electrode and negative charge on the substrate side.
• When VGS > VT and small VDS is applied, the semiconductor surface below
the gate inverts to n-type material.
• The n-type material that exist between source and drain regions is called n-
channel.
• At this point, current ID starts to flow from drain to source through the
channel.
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MOSFET Operation :
• Threshold Voltage (VT ) defines the voltage at which a
MOS transistor begins to conduct.
• The value of threshold voltage is in a range of 0.5
Volts.
• Factor that affects the threshold voltage:
i. Substrate doping
ii. Oxide thickness
iii. Gate material
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Threshold Voltage

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Resistive or Linear Operation
• VD is increased until VD < VG - VT, a continuous conductive channel
still exist between source and drain regions.
• The transistor is in the resistive or linear region.
• At that point, the conducting channel disappears or is pinched off near
the drain.
• In resistive or linear operation, the current ID increase proportionally to
VD.
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Saturation Region
• VDS is increased until VDS > VGS – VT, the channel
thickness gradually is reduced from source to drain until
pinch-off increased until the channel length is decreased.
• Under those circumstances, the transistor is in the
saturation region and consequently, the current remains
constant (or saturates).
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NMOS Transistor I-V Characteristics
I-V Characteristics of NMOS Transistor
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T
NMOS & PMOS Transistor I-V
Characteristics
I-V Characteristics of NMOS vs. PMOS
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NMOS Operation
For further references :
www.circuitstoday.com/mos-transistors-operation
claymore.engineer.gvsu.edu/~streiana/214/NMOS.pdf
www.doe.carleton.ca/~tjs/21-MOS
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Submicron MOS Transistor
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Channel Length
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Channel Length
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Issues Related to Submicron MOS
Transistor
i. Channel Length Modulation
ii. Velocity Saturation
iii. Sub-threshold Conduction
iv. Threshold variations
v. Parasitic Resistances
vi. Latch-up
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Channel Length Modulation
As VDS increases above
VDSAT, the length of the
depleted channel beyond
pinch-off point, ∆∆∆∆L,
increases and actual L
decreases.
ID increases slightly with
VDS instead of being
constant.
For long-channel transistors, the effect of channel length variation is
not prominent. With the decrease in channel length, however, the
variation matters.
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Velocity Saturation
The behaviour of short - channel transistors deviate considerably
from the resistive and saturated models. This deficiency is the
velocity saturation effect.
• The carrier mobility of semiconductor
is a constant. However, at high field
strengths, the carriers fail to follow this
linear model.
• When the electrical field along the
channel reaches a critical value, the
velocity of the carriers tends to saturate
due to scattering effects (collisions
suffered by the carriers).
• This means that in short-channel devices,
the saturation point is reached with only
a couple of volts between drain and
source.
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Sub-Threshold Conduction
In short-channel transistor, the current does not drop abruptly to 0
at VGS = VT , meaning that MOS transistor is already partially
conducting for voltages below the threshold voltage. This effect is
called sub-threshold or weak-inversion conduction. The transition
from the on- to the off-condition is thus not abrupt, but gradual.
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Threshold Variations
• Threshold voltage is only a function of the manufacturing
technology and the applied body bias VSB . The threshold can
therefore be considered as a constant over all NMOS (PMOS)
transistors in a design.
• As the device dimensions are reduced, this model becomes
inaccurate, and the threshold potential becomes a function of L,
W, and VDS.
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Parasitic Resistance
Parasitic resistance
– uninvited resistances in series with the drain and source regions in
scaled down transistors.
How? The junctions become shallower and smaller contact openings.
Effect: The resistances cause a deterioration in the device performance,
as it reduces the drain current for a given control voltage.
The resistance must be kept as small as possible.
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RC - the contact resistance
W - the width of the transistor
LS,D - the length of the source or drain region
R is the sheet resistance per square of the drain source diffusion, and ranges from 20 to 100 Ω/ .

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Latch-up
Definition
A type of short-circuit which can occur in an
improper designed circuit.
The existence of a low-impedance path between the
power supply rails of a MOSFET circuit will trigger
a parasitic structure which will disrupt the proper
functioning of the part, possibly even leading to its
destruction due to over current.
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Latch-up
• The MOS technology contains a number of intrinsic bipolar
transistors. The combination of wells and substrates results
in the formation of parasitic resistance.
• The n-p-n-p structure is formed by the source of the NMOS,
the p-substrate, the n-well and the source of the PMOS.
Origin of Latch- up
NMOS PMOS
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Latch-up
Latch-up Equivalent Circuit
• The n-p-n-p structure is formed by the
source of the NMOS, the p-substrate, the n-well
and the source of the PMOS. The equivalent circuit
form a thyristor-like devices.
• Triggering the thyristors leads to a shorting of the
VDD and VSS lines, usually resulting in a destruction
of the chip, or at best a system failure that can only
be resolved by power-down.
• When one of the two bipolar transistors gets
forward biased (e.g., due to current flowing through
the well, or substrate), it feeds the base of the other
transistor. This positive feedback increases the
current until the circuit fails or burns out.
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Latch-up
• Place numerous well and substrate contacts
close to the source connections of the
NMOS/PMOS devices ( to minimized the
resistances Rnwell and Rpsubs ) .
• Place guard rings around the transistors to
reduce the resistance.
How to avoid latch-up phenomenon?
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SPICE MODELS
Level 1 : Long Channel Equations – Very Simple
Level 2 : Physical Model – Includes Velocity Saturation
and Threshold Variations
Level 3 : The formulations are derived from the model 1
and take into account a set of physical
limitations in a semi-empirical way (based on
curve fitting to the measured devices.
Level 4 (BSIM) : Berkeley Short-channel IGFET Model
recommended for ultra-deep submicron
technology simulation
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MOS Switch Model
NMOS Transistor Switch Model
SYMBOL
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Switch is ON Switch is OFF

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MOS Switch Model
PMOS Transistor Switch Model
SYMBOL
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Switch is ON Switch is OFF
Design Abstraction Level
As the IC design becomes more complex, how
to design chips with more and more functions?
Efficient design method is needed:
different levels of abstraction.
Design abstraction :
The complexity of the circuit is reduced by
successively replacing detail with simplifications at
higher levels of abstraction.
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Design Abstraction Level
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Design Abstraction Level
Level Explanation
1. Specification/System The chip function and specification is stated clearly (as
stated in data books).
2. Module The function/specification identified is represented in
register form. The function blocks are divided into
smaller blocks such as counter, register and
combinational logic.
3. Logic Gate The blocks earlier are divided into logic gates such as
NAND gate, NOR gate, XOR gate, etc.
4. Transistor Circuit Logic gates are represented in transistor form such as
NMOS and PMOS.
5. Device/Layout The layout of each transistor is produced and sent to
the IC fabrication lab.
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