Integrated circuits have increased dramatically in complexity over time due to advances in fabrication technology allowing for higher densities of components on silicon chips. The fabrication process involves growing high purity silicon crystals, depositing layers, doping for conductivity, patterning circuits using photolithography, and packaging individual dies. Advances like shrinking transistor sizes and cleaner room environments have allowed integration to scale while maintaining reliability.

1. IC Fabrication – An Introduction

2. Integrated
circuit showing
memory blocks,
logic and
input/output
pads around
the periphery

4. 1. Development of Integrated Circuits
• The advent of revolution in electronics made possible
by the development of higher integration of density of
silicon integrated circuits, e.g. memories of 512M
• Advantages of increased density of integration:
- reducing system cost (IC cost mainly in packages),
- enhancing overall system function, and
- increasing reliability.
• Requires tremendous research in several areas:
semiconductor device physics, fabrication
technology and computer-aided-design tools.

5. •Increasing integration density on the wafer is achieved by
shrinking the dimensions of the semiconductor device. Small
geometry transistors also have much faster speed.
•In MOS IC, the channel length of the MOSFET has been
continuously decreased from an initial value of 10 m to deep
sub-micron (0.18m) in the present manufacturing state of the art.
In research labs, devices based on nanotechnology (65 nm and
less) are built.
• To fabricate small geometry devices requires the definition of very
fine patterns on the wafer during the photolithographic process.
Other physical problems in small size structures urges the
development of new fabrication process, such as
photolithography, plasma etching .
• The fabrication environment has also become more stringent
because of the yield problem in large area wafers. Class 10 or
even lower clean room has to be used to control the amount of dust
particles.

6. 1975 1980 1985 1990 1995
10
4
10
5
10
6
10
7
10
8
10
9
2um
0.8um
0.5um
5um
0.35um
Components
per
chip
Year

7. Monolithic and Hybrid Circuits
• ICs that are placed entirely on a single chip of semiconductor (usually Si) are
called monolithic circuits. Monolithic circuits have the advantage that mass
production by batch processing is possible. Many identical circuits are
fabricated simultaneously on a Si wafer (up to 12” diameter), which is then
sawed into many chips. Each chip is finally enclosed in plastic or ceramic
packages to become an IC.
•A hybrid circuit contains one or more monolithic circuits or individual
transistors bonded to an insulating substrate with other resistors, capacitors
and interconnections. Hybrid circuits allow the use of more precise resistors
and capacitors, and are less expensive to build in small numbers.

10. drain
IC device

11. Silicon chip High lead solder die attach
Tin/lead plated copper
leadframe

12. Types of Chips
• Dynamic Random Access Memory chips
(DRAMs) - serve as the primary memory for
computers
• Microprocessors (MPUs) - act as the brains of
computers.
• Application Specific Integrated Circuits (ASICs)
- are custom semiconductors designed for very specific
functions
• Digital Signal Processors (DSPs) - process signals,
such as image and sound signals or radar pulses.
• Programmable memory chips (EPROMs,
EEPROMs, and Flash) - are used to perform
functions that require programming on the chip.

13. Complete Stages

14. Steps involved in Fabrication
Processes
1. Crystal Growth
2. Epitaxial Growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion Implantation
7. Isolation techniques
8. Metallization
9. Assembly processing & Packaging.

15. Crystal Growth
• Czochralski method
• Silicon crystal growth
from the Melt
• > 90 % of the the
semiconductor
industry use this
option.
• Starting Material :
Quartzite – Pure form
of Sand (SiO2)

16. Czochralski Method
• Three main parts
• A furnace – which
includes a fused-silicon
(SiO2) Quartz crucible ,
a rotation mechanism ,
a heating element and
power supply
• A high-purity, single-
crystal silicon
"99.999999999%
(eleven-nine)" is grown
from a seed to an ingot.
The wafers are generally available in diameters of 150 mm, 200 mm, or 300 mm,
and are mirror-polished and rinsed before shipment from the wafer
manufacturer.

17. Wafer Fabrication
the two ends are removed
the surface is grinded to to give the required diameter
one or more flat regions grounded along the length of the
ingot
ingots are diamond sawed to give wafers
the damaged and contaminated regions are removed
using chemical etching
 polished – to provide a smooth and specular surface

18. Epitaxial Growth
• Epitaxy comes from Greek words:
• Epi: upon
• Taxis: arranged
• Epitaxial growth: single crystal growth of a material
in which a substrate serve as a seed
• 2 types of epitaxy:
• Homoepitaxy – material is grown epitaxially on a
substrate of the same material. E.g. grow of Si on Si
substrate
• Heteroepitaxy – a layer grown on a chemically
different substrate. E.g. Si growth on sapphire.

19. Chemical-Vapor Deposition ( CVD)
• Silicon Tetrachloride (SiCl4), Dichlorosilane
(SiH2Cl2), trichlorosilane (SiHCl3) and Silane (SiH4)
are used
SiCl4 + 2H2 Si + 4HCl
• Diborane (B2H6) is used as p-type dopant
• Phospine (PH3) or Arsine (AsH3) is used for n-type.

20. Thermal Oxidation
• the wafer is placed in a high-temperature
furnace to make the silicon react with oxygen or
water vapor, and to develop oxide films on the
wafer surface (thermal oxidation).
• Oxidation temperature is generally 900oc – 1200oc
• Dry Oxidation Si + O2 SiO2
• Wet Oxidation Si + 2H2O SiO2 +2H2
• Thickness of Oxide layer is of 0.02 to 2 µm.

21. Photolithography
• It involves two process
1. making a photographic mask
2. Photo Etching
Methods
• UV – line width = 2µm
• X-ray or electron beam. < 1µm

22. Photomask Creation
• The photomask is a copy of
the circuit pattern, drawn on
a magnified scale by a factor
of 500.
• Initial layout ->several mask
layers.
• Mask – alternate clear and
opaque regions.
•Clear Mylar & red photographically opaque mylar are
used.
•The red layer can be peeled off to expose regions.
•Coordinatograph – cuts the pattern on red mylar.
•This pattern – photographed & reduced many times.

23. The
photomask
of a RF IC
Chip

24. Photoresist Coating
• A resin called "photoresist" is coated over the
entire wafer. (~1μm thick coating.)
• Photoresist is a special resin similar in
behavior to photography films that changes
properties when exposed to light.

25. Masking/Exposure
• Placed over the photoresist-coated wafer, which is
then irradiated to have the circuit diagram
transcribed onto it.
• An irradiation device called the "stepper" is used to
irradiate the wafer through the mask with ultraviolet
(UV) light.

26. Lithography area in clean room

27. Photolithography

28. Patterning: Development
• The photoresist chemically reacts and dissolves in the
developing solution, only on the parts that were not
masked during exposure (positive method).
• Development is performed with an alkaline
developing solution.
• After the development, photoresist is left on the
wafer surface in the shape of the mask pattern.

29. Etching
• "Etching" refers to the physical or chemical etching
of oxide films and metallic films using the resist
pattern as a mask.
• Etching with liquid chemicals is called "wet
etching" and etching with gas is called "dry
etching".

31. Photoresist Stripping
• The photoresist remaining on the wafer surface
is no longer necessary after etching is complete.
Ashing by oxygen plasma or the likes is
performed to remove the residual photoresist.

32. Diffusion
• High temp furnace at 1000 oc
• BCl3 for Boron, P2O5 for Phosphor, & carrier gas.
• Depth of diffusion depends on time of diffusion.

33. Ion Implantation
• Ion implantation used to intorduce impurities in to
silicon wafer.
• Wafers are placed in a vacuum chamber and scanned
by a beam of high energy dopant ions. ( p/n).
• Ions are accelerated by 20KV to 250KV. Depth of
penitration depends on ion velocity.
• Its performed at low temp. preventing any difusion.

34. Isolation techniques
• To provide electrical isolation between different
components and connections.
• P-N Junction Isolation – it has transitition
capacitance at the pn junctions. - commonly used.
• Dielectric Isolation
• mostly used in professional
• grade ICs.

35. Metallization
• Interconnecting the devices, such as transistors,
formed on the silicon wafer completes the circuit.
• the wafer is first covered with a thick and flat
interlayer insulation film (oxide film). Next, contact
holes are drilled by lithograph and etching, through
the interlayer insulation film, above the devices to
be connected.
Nine-layer Copper Interconnect Architecture

36. Vacuum evaporation of Al

37. Wafer Inspection
• Each IC on the completed wafer is electronically
tested by the tester.
• After this inspection, the front-end processing is
complete.

38. Wafer Inspection

39. Dicing
• In back end processing, a wafer completed in
front end processing is cut into individual IC
chips and encapsulated into packages.

40. Mounting – DIP
• After the IC chips are cut apart, they
are sealed into packages. The IC
chips must first be attached to a
platform called the "lead frame“.

41. Wire bonding
• The mounted IC chips are connected to the
lead frames.

42. Encapsulation
• The IC chips and the lead frame islands are
encapsulated with molding resin for
protection.

43. Exploded view of TO package

44. Characteristic Selection
• The packaged IC chips are tested and
selected.

46. Printing and Lead Finish
• The final step of IC chip manufacturing is the
printing onto the package surface and the
finishing of leads. After this step, the IC
chips are complete.