Charged pump plls

Presented to :-
Ravitesh Mishra
04/03/13 Kamlesh Keswani
A.P. B.C.E. 1
Mandideep

04/03/13 Kamlesh Keswani 2

Charge pump plls

The pll is one of the key building blocks in many communication systems ; providing a
means for maintaining timing integrity and clock synchronization. The Pll can be used in
various applications such as timing extraction from data streams. Jitter mitigation and
frequency synthesis

The CP-PLL derives its name from the fact that the phase detectors (PD) output is a
current source as opposed to a voltage source and “pumps” current into and out of the
loop filter. This form of pll is popular because it is adaptable to integration in
microcircuit devices.


Charge pump plls

The basic Pll consist of four fundamental
components :

•Phase detector, PD
• loop filter, z(s)
• Voltage controller Oscillator, VCO
• Divider, (1/n)

The phase detector (PD) compares the input
signal fi with a reference, or feedback signal fr,
to produce an error signal error signal Øe that
is proportional to the phase difference
between fi and fr.


The loop-filter extracts the low frequency
content Øz of the phase error signal Øe, which
is fed to a voltage-controlled oscillator (VCO).
The VCO produces an output
frequency ƒv proportional to the low
frequency error signal Øz. The output
signal ƒv is typically divided by a 1/n counter
producing the reference signal ƒr.


Charge pump plls

The reference signal fr is fed back to
the phase detector, forming a
closed-loop system. Using negative
feedback, the loop ensures that the
input frequency fiequals the
reference frequency ƒr and also that
the phase of ƒi and ƒr are fixed with
respect to each other. However, the
absolute phase difference between
ƒiand ƒr need not be zero. Note the
divider inside the loop serves as a
frequency multiplier


One implementation of the VCO (Fig. 3.1)
suitable for ASIC design consists of a series
connected Voltage to Current Converter
(V2CC) and a Current Controlled
Oscillator (CCO).

The V2CC takes the control voltage vc and
converts it to a proportional bias current ibias.
The bias current is fed to the CCO which
generates an output frequency proportional
to the bias current.


A representative implementation of a V2CC is
shown in Fig. 3-2. The operational amplifier
adjusts the gate voltage of Q1 such that the
current flowing through Q1 is

The current mirror consisting of Q2 and
Q3 develops the Pbias and Nbias voltages
respectively. These bias voltages are
used to set the bias current in the CCO.


The charge-pump (Fig 3-8) consists of a set of
current sources with magnitudes
of IP1 and IP2 amps respectively. In most cases
the current sources are symmetrical
thus IP1 = IP2 = IP.

One source is connected to the
positive supply rail while the other is
connected to the negative supply rail.
The sources are separated by two
switches S1 andS2. The output of the
phase detector provides the gating
signals U (up) and D(down) which
turn on S1 and S2 respectively.


The phase detector is designed such
that switches are never on
simultaneously.When U is high and D is
low then S1 is on and S2 is off which
causes current to flow out of the pump
and into the loop-filter. When U is low
and D is high then Q1 is off and Q2 is on
which causes current to flow out of
loop-filter and into the pump.


A representative CMOS charge-pump circuit is
shown in Fig. 3-9 and is similar to the output
stage of the current starved inverter (Fig 3-
5). The VPBIAS andVNBIAS voltages set the
positive and negative charge-pump currents
respectively.


The charge-pump PLL (CP-PLL) is an
extension of the basic PLL requiring the
addition of a charge-pump between the
phase detector and loop-filter. A specific
embodiment (Fig 2-3) uses a three-state
phase detector (3PD) which is used for
the analysis going forward. Each of the
blocks is discussed in the following
sections.


In the PLL the phase diffrence between the
refrence signal often from a crystal
oscillator and the output signal is tranlated
into two signals- Up and DN.

The two signal control switches to steer
current into or out of the capacitor, causing
a voltage across the capacitor to increase
or decrrease.

In each cycle the time during which the
switch is turned on is proportional to the
phase diffrence, hence the charge
delivered is dependend on the phase
diffrence also.


The voltage on the capacitor is used to
tune a voltage control oscillator (VCO)
generating a desired output signal
frequency.

The use of the charge pump naturally
adds a pole at the origin in the loop
transfer function of PLL, since the
charge pump current is driven into
capacitor to generate a voltage (V=I/
(sC)).


The additional pole at the origin is
desirable because when considering
the close loop transfer function of pll ,
this pole at the origin integrate the
error signal and cause the system to
track the input with one more order.

The charge pump in the pll design is
constructed in integrated circuit IC
technology, consisting of pull up, pull
down transistors and on chip
capacitors.

A resistor is also adder to stablise the
close loop pll


Phase-locked loops are widely used for synchronization purposes; in
space communications for coherent demodulation and threshold extension, bit
synchronization, and symbol synchronization. Phase-locked loops can also be used
to demodulate frequency-modulated signals. In radio transmitters, a PLL is used to
synthesize new frequencies which are a multiple of a reference frequency, with the
same stability as the reference frequency.

Other applications include:
*Demodulation of both FM and AM signals
*Recovery of small signals that otherwise would be lost in noise (lock-in amplifier)
*Recovery of clock timing information from a data stream such as from a disk drive
*Clock multipliers in microprocessors that allow internal processor elements to run
faster than external connections, while maintaining precise timing relationships
DTMF decoders, modems, and other tone decoders, for remote
control and telecommunications


Clock recovery
Some data streams, especially high-speed serial data streams (such as the
raw stream of data from the magnetic head of a disk drive), are sent
without an accompanying clock. The receiver generates a clock from an
approximate frequency reference, and then phase-aligns to the transitions
in the data stream with a PLL. This process is referred to as clock recovery.
In order for this scheme to work, the data stream must have a transition
frequently enough to correct any drift in the PLL's oscillator. Typically,
some sort of redundant encoding is used, such as 8b/10b encoding


Clock generation
Many electronic systems include processors of various sorts that operate at
hundreds of megahertz. Typically, the clocks supplied to these processors come
from clock generator PLLs, which multiply a lower-frequency reference clock
(usually 50 or 100 MHz) up to the operating frequency of the processor. The
multiplication factor can be quite large in cases where the operating frequency is
multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.


Spread spectrum
All electronic systems emit some unwanted radio frequency energy. Various regulatory
agencies (such as the FCC in the United States) put limits on the emitted energy and
any interference caused by it. The emitted noise generally appears at sharp spectral
peaks (usually at the operating frequency of the device, and a few harmonics). A
system designer can use a spread-spectrum PLL to reduce interference with


Charged pump plls

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