This document provides an overview and introduction to phase-locked loop (PLL) design. It covers PLL fundamentals including basic feedback loop theory, components such as phase detectors, charge pumps, loop filters, voltage controlled oscillators, and level shifters. It discusses important PLL design considerations like stability, bandwidth, and damping factor. Examples of PLL transfer functions and Bode plots are provided. Finally, it describes common PLL circuit blocks. The intended audience is those who specify, design, test or review PLL circuits.
This document provides an overview and introduction to phase-locked loop (PLL) design. It begins with an outline and introduction section. It then discusses basic PLL theory including feedback loop theory, jitter, phase noise, and common circuit implementations such as phase-frequency detectors and charge pumps. The document covers PLL analysis in both the time and frequency domains. It discusses concepts such as natural frequency, damping factor, stability, phase margin and bandwidth. The document also covers PLL response to reference modulation and phase tracking versus damping considerations. Overall it serves as a practical guide to PLL design, providing explanations of key concepts and circuits.
This document provides an overview and practical tips for phase-locked loop (PLL) design. It discusses PLL components like phase detectors, charge pumps, loop filters, and voltage-controlled oscillators. It covers PLL fundamentals including feedback loop theory, bandwidth, stability, and damping. Design tradeoffs between parameters like operating speed range, phase margin, and peaking are addressed. Sources of jitter and phase noise are also explained. The document is intended to help with first-time PLL design.
This document discusses the analysis and optimization of a PLL loop for USB3 and DisplayPort applications. It provides the block diagram and describes simulations performed to analyze stability, phase step response, reference clock noise, VCO noise, fractional-N effects, and charge pump mismatch. Equations for loop filter components like C1, R1, and C2 are derived based on parameters like reference clock frequency, VCO gain, and charge pump current. Optimization results targeting bandwidth, peaking, drift, and area are presented for different configurations including integer and fractional-N modes with 240MHz and 24MHz reference clocks.
The document summarizes the Phase-Locked Loop (PLL) system. It discusses the basic components of a PLL including the phase detector, loop filter, and voltage-controlled oscillator. It provides examples of PLL applications for frequency synthesis, modulation/demodulation, data recovery, and tracking filters. It also describes integer-N and fractional-N PLL architectures and provides examples of calculating output frequencies for each.
The document provides an overview of phase-locked loops (PLLs). It discusses the basic components of a PLL including the phase detector, voltage controlled oscillator (VCO), and loop filter. It explains how PLLs are used for applications like frequency synthesis, modulation/demodulation, data recovery, and tracking filters. The document also provides a brief history of PLLs and examples of their use in technologies like televisions, radios, computers and more. It includes diagrams of analog and digital PLL systems and examples of designing integer-N PLL frequency synthesizers.
The document discusses active filters and provides information on different types of filters including:
- Butterworth filters which have a flat frequency response in the passband and stopband.
- Classification of filters such as low-pass, high-pass, and band-pass.
- Advantages of active filters over passive filters such as greater gain and flexibility.
- Design procedures for first and second order low-pass Butterworth filters including calculating cutoff frequencies from RC values.
This document provides an overview and introduction to phase-locked loop (PLL) design. It begins with an outline and introduction section. It then discusses basic PLL theory including feedback loop theory, jitter, phase noise, and common circuit implementations such as phase-frequency detectors and charge pumps. The document covers PLL analysis in both the time and frequency domains. It discusses concepts such as natural frequency, damping factor, stability, phase margin and bandwidth. The document also covers PLL response to reference modulation and phase tracking versus damping considerations. Overall it serves as a practical guide to PLL design, providing explanations of key concepts and circuits.
This document provides an overview and practical tips for phase-locked loop (PLL) design. It discusses PLL components like phase detectors, charge pumps, loop filters, and voltage-controlled oscillators. It covers PLL fundamentals including feedback loop theory, bandwidth, stability, and damping. Design tradeoffs between parameters like operating speed range, phase margin, and peaking are addressed. Sources of jitter and phase noise are also explained. The document is intended to help with first-time PLL design.
This document discusses the analysis and optimization of a PLL loop for USB3 and DisplayPort applications. It provides the block diagram and describes simulations performed to analyze stability, phase step response, reference clock noise, VCO noise, fractional-N effects, and charge pump mismatch. Equations for loop filter components like C1, R1, and C2 are derived based on parameters like reference clock frequency, VCO gain, and charge pump current. Optimization results targeting bandwidth, peaking, drift, and area are presented for different configurations including integer and fractional-N modes with 240MHz and 24MHz reference clocks.
The document summarizes the Phase-Locked Loop (PLL) system. It discusses the basic components of a PLL including the phase detector, loop filter, and voltage-controlled oscillator. It provides examples of PLL applications for frequency synthesis, modulation/demodulation, data recovery, and tracking filters. It also describes integer-N and fractional-N PLL architectures and provides examples of calculating output frequencies for each.
The document provides an overview of phase-locked loops (PLLs). It discusses the basic components of a PLL including the phase detector, voltage controlled oscillator (VCO), and loop filter. It explains how PLLs are used for applications like frequency synthesis, modulation/demodulation, data recovery, and tracking filters. The document also provides a brief history of PLLs and examples of their use in technologies like televisions, radios, computers and more. It includes diagrams of analog and digital PLL systems and examples of designing integer-N PLL frequency synthesizers.
The document discusses active filters and provides information on different types of filters including:
- Butterworth filters which have a flat frequency response in the passband and stopband.
- Classification of filters such as low-pass, high-pass, and band-pass.
- Advantages of active filters over passive filters such as greater gain and flexibility.
- Design procedures for first and second order low-pass Butterworth filters including calculating cutoff frequencies from RC values.
This document discusses active filters and provides information on different types of filters including:
- Butterworth, Chebyshev, and Cauer filters and their magnitude responses.
- Classification of filters as low pass, high pass, band pass and band reject based on their frequency responses.
- Advantages of active filters over passive filters such as greater gain and flexibility in design.
- Key concepts such as poles, zeros and order of filters and how they determine the frequency response.
- Design procedures for first and second order low pass Butterworth filters using op-amps.
The document discusses various types of active filters including first-order and second-order low-pass and high-pass Butterworth filters. It provides expressions for calculating the gain of these filters based on the resistor and capacitor values used. The key aspects covered are:
- First-order filters use a single RC circuit to determine the cutoff frequency, while resistors set the gain.
- Second-order filters use two cascaded RC sections, with resistors and capacitors determining the high cutoff frequency.
- Active filters offer advantages over passive filters like adjustable gain and no loading effects.
This document discusses inter-symbol interference (ISI) caused by frequency dependent loss in transmission channels. ISI results in data-dependent jitter and attenuation of high frequency signal components more than low frequencies. This causes signals to take longer to reach their transmitted voltage levels. The document then discusses how equalization techniques can counteract ISI by boosting high frequency components to restore signal shape. It provides examples of transmitter pre-emphasis, receiver equalization, and discrete-time linear equalization using multiple taps with varying coefficients to approximate the inverse channel response.
This document describes an experiment on passive low-pass and high-pass filters. The objectives are to analyze the gain-frequency and phase-frequency responses of first-order R-C filters, determine cutoff frequencies, and observe how component values affect cutoff frequencies. The experiment involves using a function generator and oscilloscope to obtain Bode plots of R-C filter circuits. For a low-pass filter, the gain drops by about 20dB per decade above the cutoff frequency as expected. For both low-pass and high-pass filters, the cutoff frequencies calculated from component values match closely with measured values from Bode plots.
This document describes an experiment to analyze the frequency response characteristics of passive first-order low-pass and high-pass filters by plotting the gain and phase response of RC filter circuits. The objectives are to determine the cutoff frequency and roll-off points of the filters by varying the resistor and capacitor component values and observing how this affects the frequency response. The results show that changing the resistor or capacitor values changes the cutoff frequency as expected, while maintaining a roll-off of approximately 20dB per decade above/below cutoff for the low-pass and high-pass filters respectively.
This document describes an experiment to analyze the frequency response characteristics of passive first-order low-pass and high-pass filters. The objectives are to plot the gain and phase responses of RC filters, determine cutoff frequencies, and observe how component values affect cutoff. Procedures are provided to simulate low-pass and high-pass RC filters, measure their gain and phase curves, and calculate cutoff frequencies. The results show that the simulated and calculated cutoff frequencies match closely, and that changing resistor or capacitor values only affects cutoff frequency as expected, without changing the -20dB/decade roll-off behavior of a single-pole filter.
This document describes an experiment to analyze the frequency response of passive low-pass and high-pass filters. The objectives are to plot the gain, phase, and cutoff frequency of first-order RC filters and determine how component values affect cutoff frequency. For the low-pass filter, the cutoff frequency decreases as resistance or capacitance increases. For the high-pass filter, cutoff frequency also decreases with increasing resistance or capacitance. Both filters exhibit a roll-off of approximately 20 dB per decade of frequency change above or below the cutoff frequency, as expected for a single-pole filter.
This document discusses phase locked loops (PLLs) and their applications. It describes the basic components and principles of operation of a PLL, including the phase detector/comparator, low pass filter, error amplifier, and voltage controlled oscillator (VCO). It explains how a PLL locks onto and tracks an input signal frequency. Common applications of PLLs mentioned include frequency multiplication/division, frequency translation, AM detection, and FM demodulation.
The document discusses delay modeling in digital VLSI circuits. It notes that circuit delay depends on many factors like charge, discharge, parasitics, transistor width-to-length ratio, fan-in, fan-out and topology. Existing delay models do not clearly indicate the contribution of each factor. This wastes circuit designers' time in simulation and tweaking. The document then presents a delay model based on logical effort that estimates delay based on the topology of the gate and relative sizes of its transistors. It shows how to compute logical effort values and parasitic delays for different gates. Applying this model helps optimize circuit design parameters like transistor sizes, number of stages in a path and topology for minimum delay.
This document discusses the design and implementation of a virtual analog phaser effect. It begins with a brief history of phaser pedals and their use by artists like Rush and Pink Floyd. It then explains the underlying signal processing components of a phaser, including allpass filters and feedback. The document presents the design of a 10-stage phaser with modulated allpass filter coefficients and feedback. It includes sound examples and discusses how feedback and filter stages affect the tone. In conclusion, it notes that the implemented phaser design offers customizability and resonance through the use of feedback.
This document discusses active filters and their design using operational amplifiers (op-amps). It describes the four main types of active filters - low-pass, high-pass, band-pass and band-reject - and how each can be built by combining op-amps with passive RC or RLC circuits. It also covers filter characteristics, multi-pole filter design through cascading, and common filter configurations including the Sallen-Key filter.
Fourier Transform : Its power and Limitations – Short Time Fourier Transform – The Gabor Transform - Discrete Time Fourier Transform and filter banks – Continuous Wavelet Transform – Wavelet Transform Ideal Case – Perfect Reconstruction Filter Banks and wavelets – Recursive multi-resolution decomposition – Haar Wavelet – Daubechies Wavelet.
This document summarizes key concepts from Chapter 15 of the 9th edition of the textbook "Electronic Devices" by Thomas L. Floyd. It describes different types of basic filter responses including low-pass, high-pass, band-pass, and band-stop. It provides examples of simple passive RC filter circuits for each type and discusses their voltage gain characteristics. It also covers active filter designs using operational amplifiers that can achieve improved responses and discusses Butterworth, Chebyshev, and Bessel filter responses.
This document appears to be an experiment report for a college-level electronics course. It includes:
1. Objectives to plot gain-frequency responses of passive band-pass and band-stop filters, determine their center frequencies and bandwidths, and how circuit resistance affects bandwidth.
2. Sample computations showing solutions to steps in the experiment involving passive filter circuit analysis.
3. A data sheet listing materials used and theoretical background on passive band-pass, band-stop, low-pass, and high-pass filters. It describes how to analyze L-C series and parallel resonant filters.
4. A procedure outlining steps to simulate band-pass and band-stop filters and analyze their responses
This document describes an experiment on passive low-pass and high-pass filters. The objectives are to analyze the gain-frequency and phase-frequency responses of first-order RC filters and determine how component values affect cutoff frequency. Low-pass and high-pass RC filters are modeled in simulation software. For both filters, the cutoff frequency, gain, and phase responses are measured from Bode plots and compared to theoretical values. The results show the cutoff frequency changes as expected when resistance or capacitance values are altered.
This document discusses sampling theory and digitizing sound. It explains:
- How sound can be represented in the time and frequency domains.
- The Nyquist-Shannon sampling theorem, which states that a signal must be sampled at least twice the highest frequency to avoid aliasing.
- Key parameters for digitizing sound like sampling frequency, bit depth, and their effects on quality and file size.
- Common digital audio standards and transmission speeds like CD, telephone, ISDN, T1, and how they relate to sampling theory.
This document discusses measuring jitter using phase noise techniques. It begins with an overview of jitter and phase noise concepts. It then describes how jitter can be measured in the time domain using an oscilloscope and in the frequency domain using a phase noise analyzer. It explains how phase noise measurements can be used to derive random and deterministic jitter. The document provides examples of measuring very low jitter signals and calculating jitter contributions from phase noise spurs. It concludes with a discussion of calculating peak-to-peak jitter from RMS jitter measurements and references for further information.
This document describes an experiment on low-pass and high-pass filters. It includes the theoretical background of different filter types and how to analyze them using Bode plots. The experiment uses resistor-capacitor filters to study low-pass and high-pass behavior. For the low-pass filter, the cutoff frequency is measured from the Bode plot and matches the calculated value based on the component values. Changing the resistor changes the cutoff frequency as expected, while maintaining the same roll-off rate.
This document describes an experiment to analyze the frequency response of passive low-pass and high-pass filters. The objectives are to plot the gain and phase responses of first-order RC filters, determine cutoff frequencies, and observe how component values affect cutoff frequency. Simulation results show that low-pass filters pass low frequencies and attenuate high frequencies above the cutoff frequency. High-pass filters do the opposite, passing high frequencies and attenuating low frequencies below the cutoff. For both filters, the cutoff frequency is determined by the RC time constant, and increasing or decreasing resistance and capacitance values lowers the cutoff frequency as expected. The phase response also shifts as expected, with about a 45 degree phase shift at the cutoff frequency for both single
The document discusses fundamentals of electronic communications including filters, oscillators, equalizers, and crossovers. It provides details on different types of filters including high pass, low pass, and band pass filters. It also covers topics such as quality factor, bandwidth, cutoff frequency, slope, resonance frequency, and applications of oscillators in receivers, transmitters, and other systems.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
This document discusses active filters and provides information on different types of filters including:
- Butterworth, Chebyshev, and Cauer filters and their magnitude responses.
- Classification of filters as low pass, high pass, band pass and band reject based on their frequency responses.
- Advantages of active filters over passive filters such as greater gain and flexibility in design.
- Key concepts such as poles, zeros and order of filters and how they determine the frequency response.
- Design procedures for first and second order low pass Butterworth filters using op-amps.
The document discusses various types of active filters including first-order and second-order low-pass and high-pass Butterworth filters. It provides expressions for calculating the gain of these filters based on the resistor and capacitor values used. The key aspects covered are:
- First-order filters use a single RC circuit to determine the cutoff frequency, while resistors set the gain.
- Second-order filters use two cascaded RC sections, with resistors and capacitors determining the high cutoff frequency.
- Active filters offer advantages over passive filters like adjustable gain and no loading effects.
This document discusses inter-symbol interference (ISI) caused by frequency dependent loss in transmission channels. ISI results in data-dependent jitter and attenuation of high frequency signal components more than low frequencies. This causes signals to take longer to reach their transmitted voltage levels. The document then discusses how equalization techniques can counteract ISI by boosting high frequency components to restore signal shape. It provides examples of transmitter pre-emphasis, receiver equalization, and discrete-time linear equalization using multiple taps with varying coefficients to approximate the inverse channel response.
This document describes an experiment on passive low-pass and high-pass filters. The objectives are to analyze the gain-frequency and phase-frequency responses of first-order R-C filters, determine cutoff frequencies, and observe how component values affect cutoff frequencies. The experiment involves using a function generator and oscilloscope to obtain Bode plots of R-C filter circuits. For a low-pass filter, the gain drops by about 20dB per decade above the cutoff frequency as expected. For both low-pass and high-pass filters, the cutoff frequencies calculated from component values match closely with measured values from Bode plots.
This document describes an experiment to analyze the frequency response characteristics of passive first-order low-pass and high-pass filters by plotting the gain and phase response of RC filter circuits. The objectives are to determine the cutoff frequency and roll-off points of the filters by varying the resistor and capacitor component values and observing how this affects the frequency response. The results show that changing the resistor or capacitor values changes the cutoff frequency as expected, while maintaining a roll-off of approximately 20dB per decade above/below cutoff for the low-pass and high-pass filters respectively.
This document describes an experiment to analyze the frequency response characteristics of passive first-order low-pass and high-pass filters. The objectives are to plot the gain and phase responses of RC filters, determine cutoff frequencies, and observe how component values affect cutoff. Procedures are provided to simulate low-pass and high-pass RC filters, measure their gain and phase curves, and calculate cutoff frequencies. The results show that the simulated and calculated cutoff frequencies match closely, and that changing resistor or capacitor values only affects cutoff frequency as expected, without changing the -20dB/decade roll-off behavior of a single-pole filter.
This document describes an experiment to analyze the frequency response of passive low-pass and high-pass filters. The objectives are to plot the gain, phase, and cutoff frequency of first-order RC filters and determine how component values affect cutoff frequency. For the low-pass filter, the cutoff frequency decreases as resistance or capacitance increases. For the high-pass filter, cutoff frequency also decreases with increasing resistance or capacitance. Both filters exhibit a roll-off of approximately 20 dB per decade of frequency change above or below the cutoff frequency, as expected for a single-pole filter.
This document discusses phase locked loops (PLLs) and their applications. It describes the basic components and principles of operation of a PLL, including the phase detector/comparator, low pass filter, error amplifier, and voltage controlled oscillator (VCO). It explains how a PLL locks onto and tracks an input signal frequency. Common applications of PLLs mentioned include frequency multiplication/division, frequency translation, AM detection, and FM demodulation.
The document discusses delay modeling in digital VLSI circuits. It notes that circuit delay depends on many factors like charge, discharge, parasitics, transistor width-to-length ratio, fan-in, fan-out and topology. Existing delay models do not clearly indicate the contribution of each factor. This wastes circuit designers' time in simulation and tweaking. The document then presents a delay model based on logical effort that estimates delay based on the topology of the gate and relative sizes of its transistors. It shows how to compute logical effort values and parasitic delays for different gates. Applying this model helps optimize circuit design parameters like transistor sizes, number of stages in a path and topology for minimum delay.
This document discusses the design and implementation of a virtual analog phaser effect. It begins with a brief history of phaser pedals and their use by artists like Rush and Pink Floyd. It then explains the underlying signal processing components of a phaser, including allpass filters and feedback. The document presents the design of a 10-stage phaser with modulated allpass filter coefficients and feedback. It includes sound examples and discusses how feedback and filter stages affect the tone. In conclusion, it notes that the implemented phaser design offers customizability and resonance through the use of feedback.
This document discusses active filters and their design using operational amplifiers (op-amps). It describes the four main types of active filters - low-pass, high-pass, band-pass and band-reject - and how each can be built by combining op-amps with passive RC or RLC circuits. It also covers filter characteristics, multi-pole filter design through cascading, and common filter configurations including the Sallen-Key filter.
Fourier Transform : Its power and Limitations – Short Time Fourier Transform – The Gabor Transform - Discrete Time Fourier Transform and filter banks – Continuous Wavelet Transform – Wavelet Transform Ideal Case – Perfect Reconstruction Filter Banks and wavelets – Recursive multi-resolution decomposition – Haar Wavelet – Daubechies Wavelet.
This document summarizes key concepts from Chapter 15 of the 9th edition of the textbook "Electronic Devices" by Thomas L. Floyd. It describes different types of basic filter responses including low-pass, high-pass, band-pass, and band-stop. It provides examples of simple passive RC filter circuits for each type and discusses their voltage gain characteristics. It also covers active filter designs using operational amplifiers that can achieve improved responses and discusses Butterworth, Chebyshev, and Bessel filter responses.
This document appears to be an experiment report for a college-level electronics course. It includes:
1. Objectives to plot gain-frequency responses of passive band-pass and band-stop filters, determine their center frequencies and bandwidths, and how circuit resistance affects bandwidth.
2. Sample computations showing solutions to steps in the experiment involving passive filter circuit analysis.
3. A data sheet listing materials used and theoretical background on passive band-pass, band-stop, low-pass, and high-pass filters. It describes how to analyze L-C series and parallel resonant filters.
4. A procedure outlining steps to simulate band-pass and band-stop filters and analyze their responses
This document describes an experiment on passive low-pass and high-pass filters. The objectives are to analyze the gain-frequency and phase-frequency responses of first-order RC filters and determine how component values affect cutoff frequency. Low-pass and high-pass RC filters are modeled in simulation software. For both filters, the cutoff frequency, gain, and phase responses are measured from Bode plots and compared to theoretical values. The results show the cutoff frequency changes as expected when resistance or capacitance values are altered.
This document discusses sampling theory and digitizing sound. It explains:
- How sound can be represented in the time and frequency domains.
- The Nyquist-Shannon sampling theorem, which states that a signal must be sampled at least twice the highest frequency to avoid aliasing.
- Key parameters for digitizing sound like sampling frequency, bit depth, and their effects on quality and file size.
- Common digital audio standards and transmission speeds like CD, telephone, ISDN, T1, and how they relate to sampling theory.
This document discusses measuring jitter using phase noise techniques. It begins with an overview of jitter and phase noise concepts. It then describes how jitter can be measured in the time domain using an oscilloscope and in the frequency domain using a phase noise analyzer. It explains how phase noise measurements can be used to derive random and deterministic jitter. The document provides examples of measuring very low jitter signals and calculating jitter contributions from phase noise spurs. It concludes with a discussion of calculating peak-to-peak jitter from RMS jitter measurements and references for further information.
This document describes an experiment on low-pass and high-pass filters. It includes the theoretical background of different filter types and how to analyze them using Bode plots. The experiment uses resistor-capacitor filters to study low-pass and high-pass behavior. For the low-pass filter, the cutoff frequency is measured from the Bode plot and matches the calculated value based on the component values. Changing the resistor changes the cutoff frequency as expected, while maintaining the same roll-off rate.
This document describes an experiment to analyze the frequency response of passive low-pass and high-pass filters. The objectives are to plot the gain and phase responses of first-order RC filters, determine cutoff frequencies, and observe how component values affect cutoff frequency. Simulation results show that low-pass filters pass low frequencies and attenuate high frequencies above the cutoff frequency. High-pass filters do the opposite, passing high frequencies and attenuating low frequencies below the cutoff. For both filters, the cutoff frequency is determined by the RC time constant, and increasing or decreasing resistance and capacitance values lowers the cutoff frequency as expected. The phase response also shifts as expected, with about a 45 degree phase shift at the cutoff frequency for both single
The document discusses fundamentals of electronic communications including filters, oscillators, equalizers, and crossovers. It provides details on different types of filters including high pass, low pass, and band pass filters. It also covers topics such as quality factor, bandwidth, cutoff frequency, slope, resonance frequency, and applications of oscillators in receivers, transmitters, and other systems.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
2. Copyright, Dennis Fischette,
2004
2
Outline
• Introduction
• Basic Feedback Loop Theory
• Circuits
• “Spectacular” Failures
• Appendices:
– design for test
– writing a PLL Spec
– references
• Sorry: no DLL’s in this tutorial
3. Copyright, Dennis Fischette,
2004
3
Intended Audience
• If you…
• Are a novice PLL designer
• Specify PLL requirements
• Integrate PLL’s on-chip
• Test/debug PLL’s
• Review PLL designs
5. Copyright, Dennis Fischette,
2004
5
What is a PLL?
• A PLL is a negative feedback system where an
oscillator-generated signal is phase and frequency
locked to a reference signal.
• Analogous to a car’s “cruise control”
6. Copyright, Dennis Fischette,
2004
6
How are PLL’s Used?
• Frequency Synthesis (e.g. generating a 1 GHz
clock from a 100 MHz reference)
• Skew Cancellation (e.g. phase-aligning an internal
clock to the IO clock) (May use a DLL instead)
• Extracting a clock from a random data stream
(e.g. serial-link receiver)
• Frequency Synthesis is the focus of this tutorial.
9. Copyright, Dennis Fischette,
2004
9
Components in a Nutshell
• PFD: outputs digital pulse whose width is
proportional to phase error
• CP: converts digital error pulse to analog error
current
• LPF: integrates (and low-pass filters) error current
to generate VCO control voltage
• VCO: low-swing oscillator with frequency
proportional to control voltage
• LS: amplifies VCO levels to full-swing
• DIV: divides VCO clock to generate FBCLK clock
11. Copyright, Dennis Fischette,
2004
11
Is My PLL Stable?
• PLL is 2nd-order system similar to mass-spring-
dashpot or RLC circuit.
• PLL may be stable or unstable depending on
phase margin (or damping factor).
• Phase margin is determined from linear model of
PLL in frequency-domain.
• Find phase margin/damping using MATLAB, loop
equations, or simulations.
• Stability affects phase error, settling, jitter.
12. Copyright, Dennis Fischette,
2004
12
What Does PLL Bandwidth Mean?
• PLL acts as a low-pass filter with respect to the
reference.
• Low-frequency reference modulation (e.g.spread-
spectrum clocking) is passed to the VCO clock.
• High-frequency reference jitter is rejected.
• “Bandwidth” is the frequency at which the PLL
begins to lose lock with the reference (-3dB).
• PLL acts as a high-pass filter wrt VCO noise.
• Bandwidth affects phase error, settling, jitter.
13. Copyright, Dennis Fischette,
2004
13
Closed-loop PLL Transfer Function
• Analyze PLL feedback in frequency-domain
• Assumes continuous-time behavior
• H(s) = fb/ ref = G(s)/(1+G(s)) closed-loop
gain
• G(s) = (Kvco/s)IcpF(s)/M open-loop gain
where
Kvco = VCO gain in Hz/V
Icp = charge pump current in Amps
F(s) = loop filter transfer function
M = feedback divisor
C1 = large loop-filter capacitor
14. Copyright, Dennis Fischette,
2004
14
Closed-loop PLL Transfer Function
• General Form (ignoring C2):
H(s) = n
2 (1+ s/z) / (s2+2sn + n
2)
where
n = natural freq = sqrt(KvcoIcp/MC1)
z = stabilizing zero = 1 /RC1
= damping =
(RC1/2)*sqrt(KvcoIcp/MC1)
• If < 1, complex poles at -n ± jn*sqrt(1- 2)
– Real exponential delay
– Imag oscillation
15. Copyright, Dennis Fischette,
2004
15
What Determines Stability and
Bandwidth?
• Damping Factor (measure of stability)
• Natural Frequency (measure of bandwidth)
• Damping and natural frequency can be set
independently by LPF resistor
16. Copyright, Dennis Fischette,
2004
16
PLL Loop Equations
• Undamped Natural Frequency:
n = sqrt(Kvco*Icp/( M*C1)) in rad/sec
where
Kvco = VCO gain in Hz/V
Icp = charge pump current in Amps
M = feedback divisor
C1 = large LPF capacitor
• For stability: n/2 < ~1/20 reference frequency
• Typical value: 1 MHz < n/2 < 10MHz.
17. Copyright, Dennis Fischette,
2004
17
PLL Loop Equations
• Damping Factor: usually 0.45 < < ~1.5
= Rlpf * C1 * n /2
• Useful Relation:
Phase margin ~ 100 * (for < 0.65)
• Loop Decay Time Constant = 1/( * n)
- used to estimate settling time
- 98% settling in 4 time constants
Decay ~ 1- exp(-t* * n)
18. Copyright, Dennis Fischette,
2004
18
PLL Loop Eqns: Limits on Rlpf
• PFD must sample faster than loop can respond to
act like continuous-time system
• Discrete Time Stability Limit (Gardner,1980):
n
2 < ref
2 / (*(RlpfC1* ref + ))
• E.g. ref = 2*125MHz, C1=75pF,n=2*2MHz
Rmax < 21 kOhm
• Rlpf < 1/5 Rmax for good phase margin
• For details: see Gardner (1980), Fig. 4
19. Copyright, Dennis Fischette,
2004
19
PLL Loop Eqns: Limits on Rlpf
• Parasitic LPF Pole: Rlpf*C2 ~ Tref/
if we want V(C1) ~ V(C2) by end of Tref (goal)
(Maneatis ISSCC ’03)
I = (Vc2 –Vc1)/R
= RC2
C2
C1
Vctl
I
20. Copyright, Dennis Fischette,
2004
20
Bode Plot Primer
• Used to analyze frequency domain behavior
• Y-axis: gain in dB. E.g. 20dB=10X gain. 3dB=1.4X
• X-axis: frequency. Log scale
• Assuming “left-hand-plane” location:
– Pole: -20db/dec magnitude loss and -90°
phase shift. Capacitor pole.
– Zero: +20db/dec magnitude and +90° phase
shift. Resistor zero.
22. Copyright, Dennis Fischette,
2004
22
Phase Tracking vs. Damping
• Peaking at low and high damping factors bad
• Damping ~ 1 good compromise
• Phase Tracking think “accumulated” jitter or
phase error
• VCO frequency peaking (aka period jitter) similar
to phase peaking
25. Copyright, Dennis Fischette,
2004
25
Transient: Phase Error vs.Damping
• Less ringing and overshoot as 1
• Severe overdamping ringing and overshoot
• Ringing at high damping due to low oversampling
(large R) – Gardner limit.
38. Copyright, Dennis Fischette,
2004
38
PFD Block Diagram
• Edge-triggered - Input duty-cycle doesn’t matter
• Pulse-widths proportional to phase error
GoFaster
D
CK
Q
DFF
DLY
GoSlower
Ref
Vdd
Vdd
FB
D
CK
Q
DFF
Q
CK
D
R
R
39. Copyright, Dennis Fischette,
2004
39
PFD Logic States
• 3 and “1/2” Output states
• States:
GoFaster GoSlower Effect:
0 0 No Change
0 1 Slow Down
1 0 Speed Up
1 1 Avoid Dead-Zone
41. Copyright, Dennis Fischette,
2004
41
Avoiding the Dead-Zone
• “Dead-zone” occurs when the loop doesn’t
respond to small phase errors - e.g. 10 pS phase
error at PFD inputs:
– PFD cannot generate 10 pS wide GoFaster and
GoSlower pulses
– Charge-pump switches cannot turn on and off
in 10 pS
– Solution: delay reset to guarantee min. pulse
width (typically > 150 pS)
45. Copyright, Dennis Fischette,
2004
45
Charge-Pump Wish List
• Equal UP/DOWN currents over entire control
voltage range - reduce phase error.
• Minimal coupling to control voltage during
switching - reduce jitter.
• Insensitive to power-supply noise and process
variations – loop stability.
• Easy-to-design, PVT-insensitive reference current.
• Programmable currents to maintain loop dynamics
(vs. M, fref)?
• Typical: 1A (mismatch)< Icp < 50 A (Vctl)
46. Copyright, Dennis Fischette,
2004
46
Static Phase Error and CP
Up/Down Mismatches
• Static Phase Error: in lock, net UP and DOWN
currents must integrate to zero
– If UP current is 2X larger, then DOWN current
source must be on 2X as long to compensate
– Feedback clock must lead reference for DOWN
to be on longer
– Terr = Tdn - Tup = Treset * (Iup/Idn – 1)
47. Copyright, Dennis Fischette,
2004
47
Static Phase Error and CP
Up/Down Mismatches
• Phase error can be extremely large at low VCO
frequencies (esp. if self-biased) due to mismatch
in current mirrors (low Vgs-Vt)
• Increase Vgs or decrease Vt (large W*L)
• Typical static phase error < 100 pS
48. Copyright, Dennis Fischette,
2004
48
VCO Jitter and CP Up/Down
Mismatches
• PFD-CP correct at rate of reference (e.g. 10nS).
• Most phase error correction occurs near reference
rising edge and lasts < 200 pS, causing a control
voltage ripple.
• This ripple affects the VCO cycles near the
reference more than VCO cycles later in the ref
cycle, causing VCO jitter.
• Typ. Jitter << 1% due to Up/Down Mismatches
• Avoid ripple by spreading correction over entire
ref cycle. (Maneatis JSSC ’03)
49. Copyright, Dennis Fischette,
2004
49
Simple Charge Pump
• R(switches) varies with Vctl due to body-effect
• Use CMOS pass-gate switches for less Vctl
sensitivity
• Long-channel current sources for matching and
higher Rout
Up_n
Down
Vctl
Ibias
m1
m2
m3 m4
m5
m6
m7
50. Copyright, Dennis Fischette,
2004
50
Charge Pump: const I with amp
• Amp keeps Vds of current sources constant (Young
’92)
• Amp sinks “waste” current when UP, DOWN off
Up
Down
Down
Vctl
Vbn
Vbp
+
-
Up_n
Down_n
Up
VirtVctl
Add cap to VirtVctl for volt. stability
Amp Ibias should track Icp
51. Copyright, Dennis Fischette,
2004
51
Charge Pump – switches reversed
• Switches closer to power rails reduce noise and
Vctl dependence Icp not constant with up/down
m1,m4,m5,m8,m9: long L
Up_n
Down
Vctl
Ibias
m1
m3
m6 m7
m8
m9
m10
m2
m4
m5
52. Copyright, Dennis Fischette,
2004
52
Charge Pump: switches reversed
with fast turn-off (Ingino ‘01)
m1,m4,m5,m8,m9: long L
Up_n
Down
Vctl
Ibias
m1
m3
m6
m7
m8
m9
m10
m2
m4
m5
m11
m12
Up
Down_n
m11, m12: faster turn-off
53. Copyright, Dennis Fischette,
2004
53
Simple Charge-Pump Bias
• Ib ~ (Vdd – Vt)/R
• Ib dependent on PVT
• Prefer low-Vt, moderate-to-long L for process
insensitivity, large W/L for low gate-overdrive
• Pro: Simple, stable. Con: Vdd dependence
Ibias
m2
m1
57. Copyright, Dennis Fischette,
2004
57
Low-Pass Filter
• Integrates charge-pump current onto C1 cap to
set average VCO frequency (“integral” path).
• Resistor provides instantaneous phase correction
w/o affecting avg. freq. (“proportional” path).
• C2 cap smoothes large IR ripple on Vctl
• Typical value: 0.5k < Rlpf < 20kOhm
Res
C1 C2
Vctl
58. Copyright, Dennis Fischette,
2004
58
Feed-Forward Zero: eliminate R
• Resistor provides an instantaneous IR on the
control voltage causing the VCO V2I to generate a
current bump on the oscillator input
• Eliminate R Add parallel CP path into V2I
• See Maneatis JSSC ’96 or ’03 for example
CP1
Vintegral
Virtual Vctl
CP2
“Res”
Vproportional
V2I
RO
IVCO
59. Copyright, Dennis Fischette,
2004
59
Low-Pass Filter Smoothing
Cap(C2)
• “Smoothing” capacitor on control voltage filters CP
ripple, but may make loop unstable
• Creates parasitic pole: p = 1/(R C2)
• C2 < 1/10*C1 for stability
• C2 > 1/50*C1 for low jitter
• Smoothing cap reduces “IR”-induced VCO jitter to
< 0.5% from 5-10%
• fvco = KvcoIcpTerr/C2
• Larger C2/C1 increases phase error slightly
61. Copyright, Dennis Fischette,
2004
61
Low-Pass Filter Capacitors
• At <= 130nm, thin-gate oxide leakage is huge:
– Ileak ~ Vgate 4.5
– NMOS leakier than PMOS
– Weak temperature dependence
– Ileak vs. tox ~2-3X per Angstrom
• Use metal caps or thick-gate oxide caps to reduce
leakage
• Metal caps use 10X more area than thin gate caps
– Use minimum width/spacing parallel lines
– Hard to LVS - Check extracted layout for
correct connectivity
62. Copyright, Dennis Fischette,
2004
62
Low-Pass Filter Capacitors
• Even thick gate oxide may still leak too much
• Large filter cap (C1) typically ranges from 50pF to
400 pF
• C1 cap BW may be low as ~10X PLL BW for nearly
ideal behavior
• Min C2 BW set by Tref
• Cap BW ~ 1/RC ~ 1/L2
• Gate cap not constant with Vgs
64. Copyright, Dennis Fischette,
2004
64
Voltage-Controlled Oscillator
• VCO usually consists of two parts: control voltage-
to-control current (V2I) circuit and current-
controlled ring oscillator (ICO)
• VCO may be single-ended or differential
• Differential design allows for even number of
oscillator stages if differential-pair amps used for
delay cells
• V2V may be used instead to generate bias
voltages for diff-pair amps
65. Copyright, Dennis Fischette,
2004
65
PLL Suppression of VCO Noise
• PLL acts like a high-pass filter in allowing VCO
noise to reach PLL output
• Need noise-immune VCO to minimize jitter
– Feedback loop cannot react quickly.
• Power-supply noise is largest source of VCO noise
66. Copyright, Dennis Fischette,
2004
66
VCO Design Concerns
• Min low-frequency power-supply sensitivity
< 0.05% per %dVDD reduce phase error
• Min high-frequency power-supply sensitivity
< 0.1% per %dVDD reduce period jitter
Note: this is 10X better than normal INV
• Low substrate-noise sensitivity reduce Vt
– unnecessary in SOI
• Thermal noise (kT)
– typically < 1% VCO period at high frequency
67. Copyright, Dennis Fischette,
2004
67
VCO Design Concerns
• Large frequency range to cover PVT variation:
3-5X typical
• Single-ended or differential?
– use differential for 50% duty-cycle
• Vco gain (fvco = Kvco* Vctl) affects loop stability
• Typical VCO gain: Kvco ~ 1-3X * fmax
• More delay stages easier to initiate oscillation
– Gain(DC) > 2 for 3 stages
– Gain(DC) > sqrt(2) for 4 stages
68. Copyright, Dennis Fischette,
2004
68
VCO w/“pseudo-differential”
current-starved inverters
• Need odd # of stages
• Feedback INV usually weaker by ~4X
• “Vdd” for inverters is regulated output of V2I
weak
weak
weak
69. Copyright, Dennis Fischette,
2004
69
VCO V-to-I Circuits
• Converts Vctl to Ictl
• May generate additional Vbias for oscillator
• May use internal feedback to set VCO swing
• Provides power-supply rejection fets in deep
saturation or amp-based internal feedback
• Filters high-frequency Vctl ripple w/another cap
• Adds parasitic pole BW(V2I) >> BW(PLL)
• Digital Range settings allow for control of VCO
gain and Vctl range must overlap ranges
70. Copyright, Dennis Fischette,
2004
70
Simple V2I
• Minimal filtering of Vctl ripple
• Keep long-channel current source in saturation
• Cap adds parasitic pole p = 1/(Rvco*C)
• Typical Cap Size: 0.5 pF < C < 5 pF
• Reference Vctl to same potential as LPF caps
Vctl
71. Copyright, Dennis Fischette,
2004
71
V2I w/Feedback (V. von Kaenel (JSCC ’96)
• Feedback amp provides good low-freq power-
supply rejection
• Cap to Vdd provides good high-freq rejection
• Start-up needed
• Stability concern?
Vctl
_
+ m1
Ivco
m2
Vfb
73. Copyright, Dennis Fischette,
2004
73
VCO: simple differential delay
• DC gain ~ gm1*R
• Hard to get enough gain w/o large resistor
• Tail current controls delay – V2I needed?
Vbn
m1 m2
ip in
zn zp
m3
74. Copyright, Dennis Fischette,
2004
74
VCO: differential delay
w/symmetric load (Maneatis ’96)
• Loads acts like resistor over entire voltage swing
• Widely used but requires two bias voltages
zn zp
Vbn
m1 m2
ip in
m5
m3 m4
m6 m7
Vbp
75. Copyright, Dennis Fischette,
2004
75
V2I: replica bias - symmetric load
• Vswing = Vctl (Maneatis ’96)
• Amp provides DC power-supply rejection
• Stable, but getting high BW and good PSRR tricky
+
-
Vfb
Vbn
m1 m2
m5
m3 m4
m6 m7
Vctl
Vctl
Dummy delay cell
76. Copyright, Dennis Fischette,
2004
76
VCO Level-Shifter
• Amplify limited-swing VCO signals to full-rail
– typically from 0.4-0.7V to VDD
• Maintain 50% duty-cycle
– usually +/- 3%
– difficult to do over PVT and frequency
• Insensitive to power-supply noise
< 0.5 % per % dVDD
• Which power-supply? Analog or digital?
– usually digital
77. Copyright, Dennis Fischette,
2004
77
VCO: Level-Shifter
• Need sufficient gain at low VCO frequency
• Use NMOS input pair if VCO swing referenced to
VSS for better power-supply rejection
• Net “zn” should swing almost full-rail to switch
output inverter
in
z
m1 m2
ip
m3 m4
zn
79. Copyright, Dennis Fischette,
2004
79
Feedback Divider (FBDIV)
• Divide VCO by N fref = fvco/N
• Divider may be internal to PLL or after CPU clock
tree
• Max FBDIV frequency should be greater than max
VCO frequency to avoid “run-away”
• Minimize FBDIV latency to reduce VDD-induced
jitter seen at phase detector
• Loop Phase Margin Degradation ~ nTdly
– usually insignificant
81. Copyright, Dennis Fischette,
2004
81
Asynchronous Divide-by-2
• Pro: fast, simple
• Pro: small area
• Con: long latency for large divisors
• Con: divide by powers of 2 only
• Can be used as front-end to synchronous counter
divider to reduce speed requirements
83. Copyright, Dennis Fischette,
2004
83
Counter-Based Divider
• Pro: divide by any integer N
• Pro: constant latency vs. N
• Pro: low latency
• Pro: small area Binary-encoded.
• Con: slow if using ripple counter don’t
• Con: output may glitch delay (re-sample)
output by one cycle to clean up glitch
85. Copyright, Dennis Fischette,
2004
85
Voltage Regulator/Filter
• Used to filter power-supply noise
– typically > 20 dB (10x) PSRR over entire
frequency range
– desire 30+ dB
• Secondary purpose is to set precise voltage level
for PLL power supply
– usually set by bandgap reference
86. Copyright, Dennis Fischette,
2004
86
Voltage Regulator
• Bandgap reference generates a voltage reference
(~1.2V) that is independent of PVT
– relies on parasitic diodes (vertical PNP)
• Regulator output stage may be source-follower
(NFET) or common-source amp (PFET)
– source-follower requires more headroom (and
area?) but is more stable
– common-source amp may be unstable without
Miller capacitor or other compensation
• Beware of large, fast current spikes in PLL load
(i.e. when changing PLL frequency range)
87. Copyright, Dennis Fischette,
2004
87
Bandgap Reference w/Miller Cap
• Stability and PSRR may be poor w/o Miller cap
• Miller cap splits poles. Can also add R in series
w/Cc for more stability (Razavi ’00)
Vbg
-
+
m1
10k 5k
1k
m=8 m=1
Cc
89. Copyright, Dennis Fischette,
2004
89
Advanced Concepts:
Self-Biased PLL
• Conventional PLL: loop dynamics depends on Icp,
Rlpf, Clpf, Kvco and FBDiv. These do not necessarily
track.
• Why not generate all bias currents from the I(vco)
and use a feed-forward zero to eliminate the
resistor. Everything tracks. (Maneatis JSCC ‘03)
• Con: start-up, stability
• Pro: reduces PVT sensitivity
92. Copyright, Dennis Fischette,
2004
92
PLL Problem
• Problem: 3-stage PMOS diff-pair VCO wouldn’t
oscillate at low frequencies. When VCO finally
started up at high Vctl, it outran FBDIV.
• Cause: leaky, mis-manufactured loads in delay
cell reduced gain of delay element < 2
• Solutions:
– increase L of load devices for higher gain
– add more VCO stages to reduce gain
requirements
93. Copyright, Dennis Fischette,
2004
93
PLL Problem
• Problem: VCO stuck at max frequency at power-
on.
• Cause: PLL tried to lock before VDD was stable.
Because VCO couldn’t run fast enough to lock at
low VDD, Vctl saturated. When VDD finally
stabilized, Vctl = VDD, causing a maxed-out VCO
to outrun FBDIV.
• Solution: maintain PLL RESET high until VDD is
stable to keep Vctl at 0V.
94. Copyright, Dennis Fischette,
2004
94
PLL Problem
• Problem: VCO stuck at max frequency after
changing power-modes.
• Cause: Feedback DIV could not run fast enough to
handle VCO overshoot when locking to a new
frequency or facing a reference phase step.
• Solutions:
– limit size of frequency steps
– increase speed of Feedback DIV
95. Copyright, Dennis Fischette,
2004
95
PLL Problem
• Problem: PLL would not lock.
• Cause: Feedback DIV generated glitches causing
PFD to get confused.
• Solution: add re-sampling flop to output of
feedback DIV to remove glitches.
96. Copyright, Dennis Fischette,
2004
96
PLL Problem
• Problem: PLL output clock occasionally skipped
edges at low VCO frequencies
• Cause: VCO level-shifter had insufficient gain
when VCO swing was close to Vt.
• Solutions:
– increase W of diff-pair inputs
– use low-Vt devices
97. Copyright, Dennis Fischette,
2004
97
PLL Problem
• Problem: VCO jitter was huge at some divider
settings and fine at others.
• Cause: Integration team connected programmable
current sources backward.
• Solution: write accurate verilog model that
complains when inputs are out-of-range.
98. Copyright, Dennis Fischette,
2004
98
PLL Problem
• Problem: PLL jitter was poor at low freq and good
at high freq.
• Cause: Vctl was too close to Vt at low frequency.
• Solution: Run VCO at 2X and divide it down to
generate slow clocks.
99. Copyright, Dennis Fischette,
2004
99
PLL Problem
• Problem: RAMDAC PLL had large accumulated
phase error which showed up as jitter on CRT
screen.
• Cause: PLL bandwidth was too low, allowing
random VCO jitter to accumulate.
• Solution: increase bandwidth so that loop corrects
before VCO jitter accumulates.
100. Copyright, Dennis Fischette,
2004
100
PLL Problem
• Problem: PLL had poor peak-peak jitter, but good
RMS jitter.
• Cause: digital VDD pin in package adjacent to
PLL’s analog VDD coupled digital VDD noise to
analog VDD during certain test patterns.
• Solution: Remove wirebond for adjacent digital
VDD pin.
101. Copyright, Dennis Fischette,
2004
101
PLL Problem
• Problem: large static offset.
• Cause: designer did not account for gate leakage
in LPF caps.
• Solutions:
– switch to thick-gate oxide caps
– switch to metal caps
102. Copyright, Dennis Fischette,
2004
102
PLL Problem
• Problem: VCO period jitter = +/- 20%, modulated
at a fixed frequency.
• Cause: Unstable V2I internal feedback loop
caused by incorrect processing of stabilizing caps.
• Solutions:
– correct manufacturing of capacitors
– add more caps
103. Copyright, Dennis Fischette,
2004
103
PLL Problem
• Problem: bandgap reference was stable in one
process but oscillated in a different process with
similar feature sizes.
• Cause: compensation caps for 2-pole feedback
system with self-bias were too small.
• Solution: make compensation caps 3X larger.
104. Copyright, Dennis Fischette,
2004
104
Uncle D’s PLL Top 5 List
• 5. Maintain damping factor ~ 1
• 4. VDD-induced VCO noise – loop can’t do the
work for you
• 3. Leaky gate caps will cost you your job
• 2. Make FBDIV run faster than VCO
• 1. Observe VCO,FBCLK,REF,clkTree on differential
I/O pins – you can’t fix what you can’t see!
109. Copyright, Dennis Fischette,
2004
109
Measuring Jitter: Power-Supply
Noise Sensitivity
• Induce noise on-chip with VDD-VSS short
– need off-chip frequency source or on-chip FSM
to control noise generator
– How to measure induced noise magnitude?
• Induce noise on board
– capacitively couple to VDDA
– hard to get it past filtering and attenuation
– how much makes it to PLL?
– VDDA inductance? – wire-bond, flip-chip
110. Copyright, Dennis Fischette,
2004
110
Routing: From PLL to Board
• Differential IO outputs highly desirable
• Types of IO – use highest-speed available
• Divide VCO to reduce board attenuation only if
necessary make divider programmable
• Measuring duty-cycle
- Divide-by-odd-integer
- Mux to select either true or inverted clock
• Minimize delay on-chip from PLL to IO
• Ability to disable neighboring IO when measuring
jitter
• Avoid coupling in package and board
111. Copyright, Dennis Fischette,
2004
111
General Test Hardware
• High-bandwidth scope:
– 4-6 GHz real-time
– $50-60k
– e.g. Agilent, Tektronix, LeCroy
• Differential high-speed probes:
– 3-6 GHz BW
– $3-6k
• Active pico-probes and passive (DC) probes for
micro-probing PLL
• Avoid large GND loops on probes
113. Copyright, Dennis Fischette,
2004
113
Miscellaneous Jitter Measurements
• Open-loop vs. Closed-loop Jitter
– disable loop-filter does PLL jitter change?
• Mux Ref into PLL observation path for jitter
calibration
– Is Ref jitter worse after coming from PLL
compared to before it enters the chip?
• Observe “end-of-clock tree” for jitter and duty-
cycle distortion
• Observe Fbclk for jitter and missing edges
114. Copyright, Dennis Fischette,
2004
114
Measuring PLL Loop Dynamics
• Modulate reference frequency, measuring long-
term PLL jitter. Sweep modulation frequency to
determine bandwidth and damping.
– e.g. Wavecrest
• Spectrum analyzer
– look for noise suppression in frequency range
close to signal peak
– difficult if noisy setup
115. Copyright, Dennis Fischette,
2004
115
Measuring Phase Error
• Hard to do!
• Fbclk available for observation?
• Need to acct. for Fbclk delay from PLL to IO –
depends on PVT.
• Solutions:
– route Fbclk off-chip to pkg and match input
delay with Ref. Fbclk/Ref skew at pins ~ Terr
at PFD.
– measure Terr on-chip – send out narrow pulses
– narrow pulses disappear.
– measure Terr on-chip with A/D. Complex.
– mux Fbclk and ref into same path. Compare
both to external reference.
116. Copyright, Dennis Fischette,
2004
116
Analog Observation
• Analog observation IO pins for debug and
characterization
– may force internal analog nets as well if bi-
directional pin
– low-bandwidth requirements low MHz or kHz
– isolate analog nets with unity-gain buffer or
resistor and pass-gates w/solid pull-down
– drive analog pins to known value when not in
use
– tri-state analog pin for ESD leakage testing
– ESD protection (CDM and HBM) may cause IO
leakage
117. Copyright, Dennis Fischette,
2004
117
Probing On-chip
• If not flip-chip, then put probe pads on top-layer
metal.
• Probe pad size >1um x 1um. Prefer > 2um x
2um.
• Place probe pad on a side-branch of the analog
signal to avoid breaking wire with probe.
• Separate probe pads to allow room for multiple
probes.
• FIB: can add probe pad, add or remove wires.
– need room and luck
• FIB: can FIB SOI flip-chip from back of wafer if
enough room around lower-level wires.
120. Copyright, Dennis Fischette,
2004
120
Physical Integration
• Area, aspect ratio?
• What metal layers are available?
• Digital signal routing allowed over PLL?
• Where is PLL located on chip?
• Wire-bond or flip-chip?
121. Copyright, Dennis Fischette,
2004
121
Semiconductor Process
• 90nm, 130nm, 180nm?
• Bulk vs. SOI? SOI body-ties?
• Nwell vs. twin-well?
• Epi substrate?
• Accumulation-mode capacitors?
• Gate-oxide thickness? Capacitance density and
leakage.
• Dual-gate oxide available? Leakage.
• Poly density requirements?
• Low-Vt available?
• Resistor types? Poly? Diffusion?
122. Copyright, Dennis Fischette,
2004
122
Power-Supply
• Separate analog VDDA? What voltage? 1.8V?
2.5V? Higher than core voltage?
• Separate analog VSSA?
• Wire-bond or flip-chip? Package Type?
• What type of VDDA filtering on board? Ferrite
bead? What cap sizes?
• Min, max VDDA? DC variation? AC variation?
Natural frequency (1/LC) of VDDA?
123. Copyright, Dennis Fischette,
2004
123
Performance
• Reference clock frequency? Range?
• Min/Max VCO Frequency?
• Duty cycle?
• Period Jitter?
• Fixed jitter spec or pct of period?
• Cycle-to-adjacent cycle jitter spec?
• Half-cycle jitter spec?
124. Copyright, Dennis Fischette,
2004
124
Performance
• Max Frequency overshoot while settling?
• Static phase error?
• Dynamic phase error?
• Loop bandwidth?
• Time to acquire initial lock?
• Time to re-acquire lock after frequency change?
• Power Dissipation?
125. Copyright, Dennis Fischette,
2004
125
Logic Interface
• Reset available?
• PowerOK available?
• VCO/CP/R range settings allowed?
• Clock glitching allowed when switching VCO
frequency ranges?
• Level-shift and buffer PLL inputs/outputs?
• Different power domains?
128. Copyright, Dennis Fischette,
2004
128
Paper References
[1] B. Razavi, Monolithic Phase-Locked Loops and Clock-Recovery Circuits,
IEEE Press, 1996. – collection of IEEE PLL papers.
[2] I. Young et al., “A PLL clock generator with 5 to 110 MHz of lock range for
microprocessors,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1599-
1607, Nov. 1992.
[3] J. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-
Biased Techniques”, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-
1732. Nov. 1996.
[4] J. Maneatis, “Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier
Clock Generator PLL”, IEEE J. Solid-State Circuits, vol. 38, no.11, pp. 1795-
1803. Nov. 2003.
[5] F. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Commun., vol
COM-28, no. 11, pp 1849-1858, Nov. 1980.
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