The document provides an overview of phase-locked loops (PLLs), explaining their components such as voltage-controlled oscillators (VCOs) and phase detectors (PDs), as well as their functionality in synchronizing and tracking frequency signals. It discusses issues like stability, phase noise, and the importance of components like charge pumps and phase/frequency detectors in improving performance. Additionally, it outlines design strategies and considerations for achieving optimal bandwidth and minimizing ripple effects in PLLs.

1. Phase Locked Loops (PLL)
Note
Jay Chang
1

2. 2
Outline
• Simple PLL
• VCO, PD
• PLL transfer function
• Phase Margin
• Type-I PLL
• Type-II PLL
• PFD
• Charge Pump
• CP PLL transfer function
• CP PLL stability
• Open loop bandwidth
• Design strategy
• Higher order PLL transfer function
• Higher order PLL design rule of thumb

3. 3
Local Oscillator
• Local oscillator (LO) is an electronic oscillator used with a mixer to change the
frequency of a signal.
• LO is used to up convert signal (BB or IF to RF) and down convert it (RF to IF or BB).
LO Problems
• Output signal frequency is affected by noise, temperature and process variations.
• Therefore we need a system to stabilize LO’s frequency.
• Typical LO has phase noise and with using PLL we can decrease the phase noise.
Why We Need PLL

4. 4
What is PLL
• A phase-locked loop or PLL is a control system that generates an output signal whose phase is
related to the phase of an input signal.
• Keeping the input and output phase in lock means keeping the input and output frequencies
the same. (If phase difference varies with time, the frequencies of two signals are not equal).
• Consequently, in addition to synchronizing signals, a PLL can track an input frequency, or it can
generate a frequency that is a multiple of the input frequency.

5. 5
Simple PLL

6. 6
Simple PLL
• In its simplest form, a PLL is a negative feedback loop consisting of a VCO and a
“phase detector” (PD).
• PD converts phase difference to voltage which changes the frequency and
phase of VCO and pushes it to follow the ideal reference.

7. 7
Simple PLL Problem
• If the control voltage (Vctrl) has ripple it modulates the VCO and produces side bands.
• Assuming only the first harmonic of Vctrl.

8. 8
Fixing Voltage Ripple

9. 9
VCO Test
w/o LPF
w/ LPF
w/o LPF
w/ LPF

10. 10
PD (1)

11. 11
PD (2)

12. 12
PLL Transfer Function (1)

13. 13
PLL Transfer Function (2)

14. 14
Phase Margin (1)

15. 15
Bode plots of type-I PLL showing the effect of higher KVCO
Phase Margin (2)

16. 16
Phase Margin (3)
KVCO PM
Summary:
• Increasing KVCO or KPD will cause stability problems.
• Decreasing ߱LPF for having less ripple will cause stability problems.
• Damping factor expression confirms these.

17. 17
Example (1)
߱u ߱LPF

18. 18
Practical PLL
• We have an ideal reference crystal oscillator (low phase noise compared to VCO) which operates
at low frequency.
• Then with using a frequency divider we translate VCO output to lower frequencies.
߱‫ݐݑ݋‬ = ‫ܯ‬ × ߱݅݊
CMOS VCTCXO
1 GHz

19. 19
Example (2)
ߚ = 1/‫ܯ‬
߱u ߱LPF

20. 20
Derivation

21. 21
Type-I PLL
߱LPF ↓, less ripple, but instability

22. 22
• Solving problem of limited acquisition range.
• Phase detectors produce little information if they sense unequal frequencies at their inputs.
• Solution? the acquisition range can be widened if a frequency detector (FD) is added to the loop.
• Thus, it is desirable to seek a circuit that operates as an FD if its input frequencies are not equal
and as a PD if they are. Such a circuit is called a “phase/frequency detector” (PFD).
Type-II PLL

23. 23
PFD
߱A ≠ ߱B ߱A = ߱B
PFD Circuit
Flip-flop
AND gate

24. 24
Charge Pump (CP)

25. 25
Charge Pump on PLL
• We need additional block to smoothen pulses
߱A = ߱B
PFD
output
A
B

26. 26
VCO Control Voltage
• What happens when we connect CP to VCO ?
Assume ߱A ≠ ߱B
߱in
߱VCO
or
߱VCO
ܰ

27. 27
Locked PLL
• In PLL type-II (unlike type-I) input pulse should overlap. Otherwise, charge pump output
rises to infinite voltage.

28. 28
PFD
CP
Overview Type-II PLL
Vc transient and steady state

29. 29
PFD/CP ADS Simulation

30. 30
CP PLL Transfer Function - Review

31. 31
CP PLL Transfer Function (1)

32. 32
CP PLL Transfer Function (2)
• Another simple method to find transfer function
1. Find impedance
2. Multiply it by ‫ܫ‬ܿ‫݌‬/2ߨ

33. 33
Review
It must satisfy a certain condition or it
cannot be stable.

34. 34
CP PLL Stability (1)

35. 35
CP PLL Stability (2)
Solution:

36. 36
CP PLL Stability (3)

37. 37
Derivation

38. 38
Open Loop Bandwidth
Wu provides us with valuable information about PLL system:
• System stability.
• How is the system response for slow and fast phase variations ?
• How much phase noise could be suppressed by PLL ?
• Wu will be used for PLL system design.

39. 39
Calculating ࢛ and Phase Margin

40. 40
Summary
A special case:
Independent to ‫ܥ‬1 so
ܴ1 ↑, Stability ↑, BW ↑

41. 41
Some Design Strategy
• Review Type-I PLL: Lower BW has instability problem

42. 42
Some Example and Design Rule (1)
BW
Step1. fix ߞ reach desirable stability
Step2. ߱݊
So M , BW
M , loop gain

43. 43
Change BW still maintain stability (same PM) that we want !
Some Example and Design Rule (2)

44. 44
Close Loop Transfer Function (1)
Goal: find 3dB BW
Why do we need to calculate close loop transfer function ?
• We can find the poles and 3dB bandwidth of system.
• ߱3dB will be used for phase noise calculation.
• With tuning ߱3dB we can adjust the bandwidth (spur cancellation).

45. 45
Close Loop Transfer Function (2)

46. 46
Close Loop Transfer Function (3)
Special Cases
roughly equal

47. 47
Close Loop Transfer Function (4)
Special Cases
ଵ
ோଵ஼ଵ

48. 48
Close Loop Transfer Function (4)

49. 49
High Order PLL
• Why do we need high order PLL ?
• Do to same non-ideal effects in PLL circuit analysis, Vcontrol will have some ripple
and this ripple causes side bands (spur) at the output of VCO.
• In order to suppress Vcontrol ripple and therefore suppress spurs we need to have
higher order filters.

50. 50
Derivation High Order PLL
CP

51. 51
High Order PLL Stability (1)
This pole suppress spurs but degrade the PM.
Solve: put this pole to higher frequency so C2 should be small.

52. 52
High Order PLL Stability (2)

53. 53
How to Choose C2
Rule of thumb

54. 54
How to Choose C2

55. 55
How to Choose C2

56. 56
The Root Cause Why We Need High Order PLL
1st order PLL
2nd order PLL
Higher attenuation at spurs

57. 57
Happy moon festival
and have a good holidays

58. 58
Thank you for your attention