International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Capacitor Voltage Control Strategy for Half-Bridge Three-Level DC/DC Converterகார்த்திகேயன் கிட்டுசாமி
Three-level (TL) dc–dc converters are widely used in
high-voltage input applications for the reason that the voltage stress on the power switches is only half of the input voltage. For the halfbridge TL dc–dc converter, the asymmetry of the main circuit and drive circuit result in voltage unbalance among the input divided capacitors and blocking capacitor, which will cause higher voltage stress on the power switches and the rectifier diodes. This paper
proposes a novel capacitor voltage control strategy to adjust duty cycle and phase shift of the positive and negative half-cycles so that the voltage of the input-divided capacitors and blocking capacitor are corrected and the reliability of the converter can be guaranteed. An 800-V input 28-V/2-kW output prototype has been built and
tested in the lab. The experimental results are shown to verify the theoretical analysis and the proposed control strategy.
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
Capacitor Voltage Control Strategy for Half-Bridge Three-Level DC/DC Converterகார்த்திகேயன் கிட்டுசாமி
Three-level (TL) dc–dc converters are widely used in
high-voltage input applications for the reason that the voltage stress on the power switches is only half of the input voltage. For the halfbridge TL dc–dc converter, the asymmetry of the main circuit and drive circuit result in voltage unbalance among the input divided capacitors and blocking capacitor, which will cause higher voltage stress on the power switches and the rectifier diodes. This paper
proposes a novel capacitor voltage control strategy to adjust duty cycle and phase shift of the positive and negative half-cycles so that the voltage of the input-divided capacitors and blocking capacitor are corrected and the reliability of the converter can be guaranteed. An 800-V input 28-V/2-kW output prototype has been built and
tested in the lab. The experimental results are shown to verify the theoretical analysis and the proposed control strategy.
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
IC Design of Power Management Circuits (I)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
The second edition of this well-received text continues to provide a coherent and comprehensive coverage of Pulse and Digital Circuits, suitable as a textbook for use by undergraduate students pursuing courses in Electrical and Electronics Engineering, Electronics and Communication Engineering, Electronics and Instrumentation Engineering, and Telecommunication Engineering. It presents clear explanations of the operation and analysis of semiconductor pulse circuits. Practical pulse circuit design methods are investigated in detail.
The book provides numerous fully worked-out, laboratory-tested examples to give students a solid grounding in the related design concepts. It includes a number of classroom-tested problems to encourage students to apply theory in a logical fashion. Review questions, fill in the blanks, and multiple choice questions offer the students the opportunity to test their understanding of the text material.
This text will be also appropriate for self-study by AMIE and IETE students.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications.
Harmonic comparisons of various PWM techniques for basic MLISaquib Maqsood
Cascaded inverters are ideal for connecting renewable energy sources with an AC grid, because of the need for separate dc sources, which is the case in applications such as photovoltaic or fuel cells. The inverter could be controlled to either regulate the power factor of the current drawn from the source or the bus voltage of the electrical system where the inverter was connected. The modulation techniques are crucial in operating any inverter at desired conditions. In this work different PWM techniques are implemented for five level cascaded multilevel inverter and THD variation is analyzed.
Tuned Amplifiers : Introduction, Q-Factor, small signal tuned amplifier, capacitance single tuned amplifier, double
tuned amplifiers, effect of cascading single tuned amplifiers on band width, effect of cascading double tuned
amplifiers on band width, staggered tuned amplifiers, stability of tuned amplifiers, wideband amplifiers
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
IC Design of Power Management Circuits (I)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
The second edition of this well-received text continues to provide a coherent and comprehensive coverage of Pulse and Digital Circuits, suitable as a textbook for use by undergraduate students pursuing courses in Electrical and Electronics Engineering, Electronics and Communication Engineering, Electronics and Instrumentation Engineering, and Telecommunication Engineering. It presents clear explanations of the operation and analysis of semiconductor pulse circuits. Practical pulse circuit design methods are investigated in detail.
The book provides numerous fully worked-out, laboratory-tested examples to give students a solid grounding in the related design concepts. It includes a number of classroom-tested problems to encourage students to apply theory in a logical fashion. Review questions, fill in the blanks, and multiple choice questions offer the students the opportunity to test their understanding of the text material.
This text will be also appropriate for self-study by AMIE and IETE students.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications.
Harmonic comparisons of various PWM techniques for basic MLISaquib Maqsood
Cascaded inverters are ideal for connecting renewable energy sources with an AC grid, because of the need for separate dc sources, which is the case in applications such as photovoltaic or fuel cells. The inverter could be controlled to either regulate the power factor of the current drawn from the source or the bus voltage of the electrical system where the inverter was connected. The modulation techniques are crucial in operating any inverter at desired conditions. In this work different PWM techniques are implemented for five level cascaded multilevel inverter and THD variation is analyzed.
Tuned Amplifiers : Introduction, Q-Factor, small signal tuned amplifier, capacitance single tuned amplifier, double
tuned amplifiers, effect of cascading single tuned amplifiers on band width, effect of cascading double tuned
amplifiers on band width, staggered tuned amplifiers, stability of tuned amplifiers, wideband amplifiers
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
أهمية العمل الجماعي تكمن في القدرة على تحقيق الهدف المنوط به للفريق باستخدام كل أفراد الفريق لمهاراتهم و تكاملها لمصلحة الفريق باستخدام الخطة التي تصل بهم للهدف، القائد دوره استكشاف ما هو كامن في أفراد فريقه و صقله عبر مراحل متعددة تدريباً و ارشاداً و الهاماً
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
Transformerless DC-DC Converter Using Cockcroft-Walton Voltage Multiplier to ...IJERA Editor
In the present scenario the use of transformer for high voltages in converter circuit reduces the overall operating
efficiency due to leakage inductance and use of transformer also increases the operational cost. . Therefore the
proposed system is implemented with transformer less DC-DC converter so as to obtain high DC voltage with
the use of nine stage Cockcroft-Walton (CW) voltage multiplier. The proposed converter operates in CCM
(continuous conduction mode), so that the converter switch stress, the switching losses are reduced. The DC
voltage at the input of the proposed model is low and is boosted up by boost inductor (Ls) in DC-DC converter
stage and performs inverter operation. The number of stages in CW-voltage multiplier circuit is applied with
low input pulsating DC (AC Voltage) voltage where it is getting converted to high DC output voltage. The
proposed converter switches operates at two independent frequencies, modulating (fsm) andalternating (fsc)
frequency. The fsm operates at higher frequency of the output while the fsc operates at lower frequency of the
desired output voltage ripple and the output ripples can be adjusted by the switch Sc1 and Sc2. The regulation of
the output voltage is achieved by controlling the Duty ratio.The simulation is carried over by the MATLABSIMULINK.
This paper presents a new single switched inductor-capacitor coupled transformer-less high gain DC-DC converter which can be used in renewable energy sources like PV, fuelcell in which the low DC output voltage is to be converted into high dc output voltage. With the varying low input voltages, the output of DC-DC converter remains same and does not change. A state space model of the converter is also presented in the paper. This constant output voltage is obtained by close loop control of converter using PID controller. High voltage gain of 10 is obtained without use of transformer. All the simulations are done in MATLAB-SIMULINK environment.
Frequency dependency analysis for differential capacitive sensorjournalBEEI
A differential capacitive sensing technique is discussed in this paper.
The differential capacitive sensing circuit is making use of a single power supply. The design focus for this paper is on the excitation frequency dependency analysis to the circuit. Theory of the differential capacitive sensor under test is discussed and derivation is elaborated. Simulation results are shown and discussed. Next, results improvement has also been shown in this paper for comparison. Test was carried out using frequency from 40 kHz up to 400 kHz. Results have shown output voltage of Vout=0.07927 Cx+1.25205 and good linearity of R-squared value 0.99957 at 200 kHz. Potential application for this capacitive sensor is to be used for energy harvesting for its potential power supply.
Fuzzy Logic Controller Based High Frequency Link AC-AC Converter For Voltage ...IJTET Journal
Abstract—In this paper, an advanced high frequency link AC-AC Push-pull cycloconverter for the voltage compensation is proposed in order to maintain the power quality in electric grid. The proposed methodology can be achieve arbitrary output voltage without using large energy storage elements. So that the system is more steadfast and less costly compared with the conventional inverter topology. Additionally, the proposed converter does not contain any line frequency transformer, which reduces the cost further. The control scheme for the push pull cycloconverter employs the fuzzy logic controller based sinusoidal pulse width modulation (SPWM) to accomplish better performance on voltage compensation, like unbalanced voltage harmonics elimination. The simulation results are given to show the effectiveness of the proposed high frequency link AC-AC converter and fuzzy logic controller based SPWM technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Comparators are basic building elements for designing modern analog and mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents a design for an on chip high-speed dynamic latched comparator for high frequency signal digitization. The dynamic latched comparator consists of two cross coupled inverters comprising a total of 9 MOS transistors. The measured and simulation results show that the dynamic latched comparator design has higher speed, low power dissipation and occupying less active area compared to double tail latched and preamplifier based clocked comparators. A new fully dynamic latched comparator which shows lower offset voltage and higher load drivability than the conventional dynamic latched comparators has been designed. With two additional inverters inserted between the input-stage and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area, was implemented.
A 20 gbs injection locked clock and data recovery circuitVLSICS Design
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode
applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to
higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and
temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in
this circuit. The circuit is designed in 0.18 μm CMOS and the simulations for 27-1 pseudo random bit
sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter
is 1.1 ps
This paper proposed a new sparce matrix converter with Z-source network to provide unity voltage transfer ratio. It is an ac-to-ac converter with diode-IGBT bidirectional switches. The limitations of existing matrix converter like higher current THD and less voltage transfer ratio issues are overcome by this proposed matrix converter by inserting a Z-source. Due to this Z-source current harmonics are totally removed. The simulation is performed for different frequencies. The simulation results are presented to verify the THD and voltage transfer ratio and compared with the existing virtual AC/DC/AC matrix converter. The experimental output voltage amplitude can be varied with the variable frequencies.
Method Of Compensation Instability Of Frequency Modulators In The Absence Of ...theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
To overcome the problem of mismatched voltage levels between parallel-connected low voltage photovoltaic (PV)
arrays and the higher grid voltage, a hybrid boost three level dc-dc converter is developed based on three level inverter with
the traditional single phase diode clamping. Only one inductor, two capacitors in series, and those power switches and diodes,
which are easy to be integrated, are used for establish the topology with transformerless high voltage gain. The operation
principle of the topology is analyzed, and then the pulse width modulation (PWM) control method is obtained according to
the switching functions about the output pulse voltages of both half-bridges. Therefore, the converter can not only operate
with high voltage gain, but also make the duty cycles of power switches closer to 0.5. A feedforward closed loop control
operation is proposed such that even in varying input the converter is capable of giving a constant output. Finally an
experimental is set up in the laboratory for open loop control operation. All experimental results verify the feasibility of the
circuit and validity of the PWM control method.
IC555 Timer, Monostable and Astable modes of operation; voltage regulators - fixed voltage regulators, adjustable voltage regulators - switching regulators.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Search and Society: Reimagining Information Access for Radical FuturesBhaskar Mitra
The field of Information retrieval (IR) is currently undergoing a transformative shift, at least partly due to the emerging applications of generative AI to information access. In this talk, we will deliberate on the sociotechnical implications of generative AI for information access. We will argue that there is both a critical necessity and an exciting opportunity for the IR community to re-center our research agendas on societal needs while dismantling the artificial separation between the work on fairness, accountability, transparency, and ethics in IR and the rest of IR research. Instead of adopting a reactionary strategy of trying to mitigate potential social harms from emerging technologies, the community should aim to proactively set the research agenda for the kinds of systems we should build inspired by diverse explicitly stated sociotechnical imaginaries. The sociotechnical imaginaries that underpin the design and development of information access technologies needs to be explicitly articulated, and we need to develop theories of change in context of these diverse perspectives. Our guiding future imaginaries must be informed by other academic fields, such as democratic theory and critical theory, and should be co-developed with social science scholars, legal scholars, civil rights and social justice activists, and artists, among others.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...
Fx3410861090
1. Gayathri M G, Vidhya V S / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1086-1090
1086 | P a g e
A High Speed Wide Range Frequency Synthesizer
Gayathri M G*, Vidhya V S**
*(MTech. VLSI Design, Amrita School Of Engineering, Amrita University, Amritapuri
** (MTech. VLSI Design, Amrita School Of Engineering, Amrita University, Amritapuri
ABSTRACT
Present days the Frequency Synthesizer
is used for the wireless communication in the GHz
range to correct the phase and frequency error as
well as to provide synchronization. As time passes
the frequency of operation increases and the
requirement of fast loop locking is required. This
paper presents the design of a wide range voltage
controlled oscillator, a wide range high speed fully
programmable integer N prescaler, a phase
frequency detector (PFD), an accurate charge
pump and a loop filter which entails an entire
48MHz to 992MHz frequency synthesizer.
Keywords—Blind zone, CML Logic, Cycle Slip,
Dead zone, Prescalar
I. Introduction
The Frequency synthesizer was first
invented during the reduction of the noise in the
radio received signal in the year 1932 and it was
observed that the signal coming from the distance
source is producing some noise if it is not properly
tuned. Later it was observed that the noise is
produced due to the mismatch of phase and
frequency at the receiver input and a circuit was
designed to reduce the phase and frequency error at
the receiver side .When the time passes the
frequency of operation increases and the
requirement of fast loop locking is required.
Fig. 1 shows a generic PLL-based
synthesizer. The Frequency synthesizer contains five
block phase frequency detector (PFD), charge pump
(CP), low pass loop filter (LPF), Voltage controlled
oscillator (VCO) and frequency divider [1]-[2].
Fig. 1. Frequency Synthesizer
The operation of the PLL and the
programmable counter in the feedback path allow
generation of accurate high frequencies from a pure
low frequency signal. The programmable divider D2
is preceded by a divider D1 that scales down the
high output frequencies to a range at which standard
CMOS dividers can be implemented. The design of
a Frequency synthesizer which operates for a wide
frequency range with a good frequency precision
and a very low locking time is really challenging.
II. Phase Detector
The three-state PFD circuit employs
sequential logic to create three states and respond to
falling edges of the two inputs, ‘REF’ and ‘DIV’ [2].
During State-0 falling edge of REF triggers the first
DFF to which it is connected. Data (D) inputs of
DFF’s are connected to “1” thus UP switches to “1”.
Depending on the phase difference of REF and DIV,
falling edge of DIV triggers the second DFF after a
certain amount of time. Then DOWN (DN) switches
from “0” to “1”. At this point both inputs of the
AND gate is “1” and its output turns to “1” which
activates reset signal for DFF’s. Reset signal
generated by PFD resets the DFF’s and outputs of
both DFF’s return to “0”. The same sequence is
valid if DIV is faster than REF but in the opposite
direction.
Fig. 2. Phase Frequency Detector
A dead zone [2] is a certain range of phase
input difference to the PFD in which the PLL fails to
lock. That means the VCO is allowed to accumulate
as much random phase error proportional to the
width of the dead zone while receiving no corrective
feedback.
The dead zone exists because the charge
pump switches are not ideal. They need a certain
amount of time to turn on. So for example, when the
UP signal pulse width is below 1 ns, the switch is still
not closed properly because the pulse width is not
enough to turn on the charge pump (to make its gate
to source voltage greater than the threshold voltage)
and thus, as a result, there will be no charging
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
1
1
Fref
Fdiv
UP
DN
Delay
2. Gayathri M G, Vidhya V S / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1086-1090
1087 | P a g e
current. Hence no corrective action. In other words, if
the input phase difference, ∆
n the output voltage of phase frequency
detector/charge pump/LPF combination is no longer
a function of ∆ ∆ o the charge pump
injects no current. The loop gain falls to zero and the
output phase is not locked.
The dead zone vanishes if the width of error
pulse is long enough to allow UP and DN to reach a
valid logical level and turn on the switches in the
charge pump. So we add delay blocks in the reset
path. Thereby producing coincident pulses on UP and
DN and elliminating the dead zone.The reset path
should have much delay to properly switch the
charge pump but it should not be much high leading
to cycle slipping.
III. Charge Pump And Loop Filter
A charge pump is a three position electronic
switch which is controlled by the three states of
PFD. The three states are charging current (+Icp),
discharging current (-Icn) and zero current [2]. When
the VCO output frequency is lagging behind the
reference frequency, the PFD will activate the UP
signal and deactivate DN signal. Hence, switch S1
will be closed and switch S2 will be opened. Since
switch S1 is close, current Icp will flow into the filter
and increase the control voltage, Vcrl. The increase in
the control voltage, Vcrl, will consequently increase
the VCO output frequency. The same sequence is
valid if VCO is faster than REF but in the opposite
direction.
DC
DC
vdd
Icp = 3mA
Icn = 3mA
UP
DOWN
R1=31.09
KW
C1=16.6pF
C2=5pF
Vcrl
W=120nm
L=100nm
W=300nm
L=100nm
R2=10KW
C3=15pF
Fig. 3. Charge Pump and Loop Filter
The lock condition of the PLL is
established when the VCO output frequency is the
same as the reference frequency. During this period,
the PFD will deactivate both UP and DN signals.
Hence switches S1 and S2 will be opened until the
VCO output frequency changes. Since switches are
open, there is no current path formation, hence no
current will flow into or out from the filter. Control
voltage remains a constant.
IV. Voltage Controlled Oscillator
In order to vary the frequency of an LC
oscillator [3], the resonance frequency of its tank(s)
must be varied. Since it is difficult to vary the
inductance by means of a varactor, MOS varactors
are more commonly used than pn junctions. The
VCO using MOS varactor is shown in fig. 4. The
varactor MV1 and MV2 appear in parallel with the
tanks. The gates of the varactors are tied to the
oscillator nodes and the source/drain/n-well
terminals to Vcrl. The oscillation frequency can thus
be expressed as:
(1)
Where Cvar denotes the average value of each
varactors capacitance.
Fig. 4. VCO using MOS varactor.
In applications where a substantially wider
tuning range is necessary discrete tuning may be
added to the VCO so as to achieve a capacitance
range well beyond Cmax/Cmin of varactors. Fig: 5
shows such an arrangement. The idea is to place a
bank of small capacitors each having a value of Cu,
in parallel with the tank and switch them in or out to
adjust the resonant frequency.
The Vcrl is known as fine control and the digital
input to the capacitor bank is coarse control. The
fine control provides a continuous but narrow range
whereas the coarse control shifts the continuous
characteristic. With ideal switches and unit
capacitors, the lowest frequency is obtained if all of
the capacitors are switched in and the varactor is at
its maximum value, Cmax:
(2)
DCVcrl Vcrl
1mA
W=12um
L=100nm
W=12um
L=100nm
W=16um
L=1um
W=16um
L=1um
5 KW 1fF 5nH 1fF 5nH5 KW
25f50f100f200f400f800f1.6p3.2p
b0b1b2b3b4b5b6b7
25f 50f 100f 200f 400f 800f 1.6p 3.2p
b7b6b5b4b3b2b1b0
vdd
Fig. 5. Final LC VCO
DC
Vcrl
Iss
M1 M2
Mv1 Mv2
Rp C1 L1 C1 L2Rp
b0
vdd
X Y
3. Gayathri M G, Vidhya V S / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1086-1090
1088 | P a g e
The highest frequency occurs if the unit
capacitors are switched out and the varactor is at its
minimum value, Cmin:
(3)
To avoid blind zones, each two consecutive tuning
characteristics must have some overlap.
V. Programmable Prescalar
VCO output frequency ranges from 1GHz
to 4GHz.So the programmable divider connecting to
the output of the VCO should operate at high speed.
Current mode logic is the choice for high speed
mixed signal devices.
The divider configuration using CML [3]
latches provides quadrature phases at X and Y only
if CK and CKBAR are precisely complementary and
the two latches match perfectly.
Fig. 6. Divider1
In the divider1(D1) we require divide by4,
divide by 16 and divide by 32.So a control logic is
implemented with three selection bits C0, C1 and C2
to select the required frequency.
Fig. 7. Divider1 Control
CML buffers are used at the output of
divider1 and the output from the buffer should be
taken through inverter chain in order to shape and
sharpen the waveform edges. In the output port of
divider D1 also there must be inverter chain to shape
and sharpen the output waveform edges and to
produce rail to rail swing.
Divider 2 has to divide from 3 to 62 which is
implemented with an up counter which count from 0
to 63.
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
FOUT
Q0 Q1 Q2 Q3 Q4 Q5
RST
Fig. 8. Divider2
A control circuit is made with exor gates
for comparing the selection bits (C3 to C8) and the
output of the up counter. Whenever the selection bits
are found equal to the output of the counter the up
counter is reseted and thus the reset pulse will be
divide by n of input clock fed to the up counter
where n is the decimal equivalent of the selection
bits C3 to C8.
Fig. 9. Divider2 Control
Output of the divider2 counter is fed to the
input of PFD.The whole divider circuit including
the 2 dividers, inverter chains and buffers. The
total delay of the circuit is found to be 106.35pS.
VI. Simulation Results
6.1 PFD Outputs
The output of the PFD when Fref signal
falling edge leads Fdiv signal falling edge and
vice versa is shown in the Fig. 10 and Fig. 11
respectively.
Fig. 10. When Fref falling edge leads Fdiv rising edge
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
FVCO
FVCO/4FVCO/2 FVCO/8 FVCO/16 FVCO/32 FVCO/64
C0
C1
C2
CLK1
CLK0
CLK2
FOUT
Q0
C3
Q1
C4
Q2
Q3
Q4
Q5
C5
C6
C7
C8
O1
O2
O3
O4
O5
O6
RST
4. Gayathri M G, Vidhya V S / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1086-1090
1089 | P a g e
Fig. 11.When Fref falling edge legs Fdiv rising edge
6.2 Loop Filter Outputs
The simulation result of the output of the
loop filter circuit is shown in the Fig. 12 and Fig.
13.
Fig. 12. When Fref falling edge leads Fdiv rising edge
Fig. 13. When Fref falling edge leads Fdiv rising edge
6.3 VCO Outputs
The heart of the PLL circuit is the voltage
controlled oscillator. The circuit is designed to give
a frequency of oscillation from 1 GHz to 4
GHz.The output signal of the VCO is shown in
the Fig 14.
Fig. 14. VCO Output
Fig. 15. VCO Characteristics
TABLE: 1 Phase noise measured.
Fig. 16. VCO Phase Noise
Frequency(Hz) Phase Noise, L(f)
(dBc/Hz)
1000 -44.7276
10000 -71.99
100000 -100.324
1000000 -122.355
5. Gayathri M G, Vidhya V S / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1086-1090
1090 | P a g e
RMS JPER =8.1396 pS at3.86GHz [4].
6.4 Prescalar
The simulation result of the divider 1,
divider2 are shown in Fig.17. The divider 1
divides the input by 4 and divider 2 is
programmed as divide by 24 counter. Figure
shows the whole divider circuit including the 2
dividers, inverter chains and buffers. The total
delay of the circuit is found to be 106.35pS.
Fig. 17 Prescalar Output
6.5 Overall PLL Output
Fig. 18 PLL Output
The Fig: 17 shows the plot of output
frequency verses time of the frequency synthesizer
for an output frequency of 448MHz. From the figure
it is clear that the output frequency (FOUT) maintains
constant after a time o f 5μS which is the lock
time of PLL.
VII. Conclusion
The phase frequency detector will decide
the linearity and the pull-in range of the frequency
synthesizer therefore the selection of PFD is very
important in the design. The loop filter is very
important for dynamic behaviour of the frequency
synthesizer. Therefore the selection of proper value
of resistor and capacitor will decide the speed and
behaviour of the frequency synthesizer circuit. The
self-generated rms jitter of VCO at 3.86GHz, RMS
JPER= is 8.1396 ps. The phase noise analysis results
in some general design guidelines for the
optimization of phase noise performance: The
quality factor QL of the tank inductor should be as
high as possible. The gain of the VCO has to be as
small as possible in order to minimize flicker noise
up-conversion. The flicker noise in the tail transistor
is the main contributor to the close-in phase noise.
For frequency synthesizers the design of divider
circuit is very important and it will decide the range
of frequency which can be applied in the frequency
synthesizer .A wide range high speed programmable
divider has been designed in 90nm GPDK
technology. The design uses CML when necessary
for high frequency operation. A 48 to 992MHz
Frequency Synthesizer has been designed. The lock
acquisition time is around 5μs for the system.
REFERENCES
Books:
[1] R Jakob Baker, Harry W Li, David E
Boyce, “CMOS Circuit Design Layout and
Simulation”, (Prentice Hall if India, 2003),
Ch. 19, pp. 383-386.
[2] Behzad Razavi, “Design of Analog CMOS
Integrated Circuits”, (Tata-McGraw Hill
2002), Ch. 14, pp. 482-525 & Ch. 15, pp.
532-576.
[3] Behzad Razavi, “RF Microelectronics” ,
(Pearson Education, Inc., 2012), Ch. 8 pp.
497-539, 577 , Ch. 9 pp. 597-646 , Ch. 10
pp. 683-688 & Ch.13 pp. 869-886.
Proceedings Papers:
[4] www.maximintegrated.com / Application
Note 3359/ Clock (CLK) Jitter and Phase
Noise Conversion, Dec 10, 2004