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18. memory interfacing iv
This document discusses the opcode fetch cycle of the 8085 microprocessor. It contains timing diagrams and explanations of how the microprocessor generates control signals to fetch opcodes from memory. It shows how the 8085 demultiplexes the address and data buses to access specific memory locations and place the fetched opcode on the data bus. Control signals like IO/M, RD, ALE are generated and used to latch the lower order address and retrieve the opcode byte from the addressed memory location during fetch.
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18. memory interfacing iv
- 1. MICROPROCESSOR 8085 LECTURE 21 MEMORYINTERFACING-IV PROF. SANDIP DAS
- 2. OPCODE FETCH CYCLE(TIMING DIAGRAM) CLOCK 𝑇1 𝑇2 𝑇3 𝑇4 𝐴15- 𝐴8 𝐴𝐷0 − 𝐴𝐷7 ALE 𝐼𝑂/ 𝑀 𝑆1, 𝑆0 𝑅𝐷 20H HIGHER ORDER MEMORY ADDRESS 05H 4FH OPCODE UNSPECIFIE D LOWER ORDER MEMORY ADDRESS FETC H ENABLE MEMORY CHIP MEMORY LOCATION PLACED ON DATA BUS TASK PERFORMED TO FETCH THE BYTE 4FH FROM MEMORY LOCATION 2005H MEMORY ADDRESS
- 3. DEMULTIPLEXING OF AD7-AD0 8085 MICROPROCESSOR ALE AD7 AD0 A15 A8 0 0 1 0 0 0 0 0 20HHIGHER ORDER ADDRESS D 𝑄 0 0 0 0 0 1 0 1 05H LOW ORDER ADDRESS 0 1 0 0 1 1 1 1 4FH DATA FROM MEMORY LOCATION 2005 IS PLACED IN DATA BUS 74LS373 A8- A15 A0-A7 D0-D7
- 4. GENERATING CONTROL SIGNALS 8085 𝐼𝑂/𝑀 𝑅𝐷 𝑊𝑅 𝑀𝐸𝑀𝑅 𝑀𝐸𝑀𝑊 𝐼𝑂𝑊 𝐼𝑂𝑅
- 5. 8085 DEMULTIPLEXED ADDRESSAND DATA BUS WITH CONTROL SIGNALS A15 A8 ALE 8085𝐼𝑂/ 𝑀 𝑅𝐷 𝑊𝑅 𝑀𝐸𝑀𝑅 𝑀𝐸𝑀𝑊 𝐼𝑂𝑊 𝐼𝑂𝑅 EN LATCH 𝐴𝐷0-AD7 D7 D0 A7 A0 A8 A15 ADDRESS BUS DATA BUS CONTTROL SIGNALS