This document discusses microprocessor architecture and memory interfacing. It provides an overview of the basic parts and operations of a microprocessor-based system including the CPU, memory, and I/O devices. It describes the different types of buses (address bus, data bus, control bus) and how they transfer data and signals. It also explains memory interfacing and addressing, different types of memory (RAM, ROM), and how microprocessors access memory using an address bus.

1. 1. General overview of microprocessor
2. Memory interfacing

2. What Microprocessor is ?
Multipurpose, Programmable, Clock driven
Electronics device or IC

3. Fetch: Microprocessor first brings the
instruction from Memory to CPU
Basic Operations of Microprocessor
Decode: Understands that instruction
Execution: Performs the required task

4. Basic parts of a μP Based System
• CPU (μP)
• Memory
• I/O devices

5. According to computer architecture, a bus is defined as a single
or set of wires that transfers data between hardware
components of a computer or between two separate computers.
Types of Buses
Bus
Types of Buses
Address Bus
Data Bus
Control Bus

6. Control Bus
 Generally contains one wire
 Generates control signals
 Some control signals are Read, Write and
Opcode fetch etc.

7. Data Bus
A set of bidirectional wires
Sends or receives data or information
Number of wires used in a data bus is known as its
widthwidth
A microprocessor is generally known with its data bus
width
There are two types of data transfer; Serial data
transfer and Parallel data transfer

8. Address Bus
 A set of unidirectional wires are used to
select a device
 With nn – digit numbering system we can With nn – digit numbering system we can
addressed maximum 22nn number of houses
 Microprocessor having 16 bit address bus
can communicate with 221616 or 65,53665,536
numbers of devices

9. Microprocessor Architecture
ALU
Register
Array
Contains various
registers that store
data temporarily
during program
execution.
It performs various
arithmetic and
Control Unit
It provides necessary timing and control
signals during program execution
arithmetic and
logical functions

10. First Generation
Between 1971 – 1973
PMOS technology, non compatible with TTL
4 bit processors  16 pins
8 and 16 bit processors  40 pins
Due to limitations of pins, signals are
multiplexed
Second Generation
During 1973
NMOS technology  Faster speed, Higher
density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
Ability to address large memory spaces
and I/O ports
Greater number of levels of subroutine
nesting
Better interrupt handling capabilities
Intel 8085 (8 bit processor)
Third Generation
During 1978
HMOS technology  Faster speed, Higher
packing density
16 bit processors  40/ 48/ 64 pins
Historical Background
16 bit processors  40/ 48/ 64 pins
Easier to program
Dynamically relatable programs
Processor has multiply/ divide arithmetic
hardware
More powerful interrupt handling
capabilities
Flexible I/O port addressing
Intel 8086 (16 bit processor)
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
32 bit processors
Physical memory space 224 bytes = 16 Mb
Virtual memory space 240 bytes = 1 Tb
Floating point hardware
Supports increased number of addressing
modes
Intel 80386
Fifth Generation Pentium

11. MEMORY

12. A single Flip-Flop / Capacitor can store one
bit – 0 or 1
8 Flip-Flops together will form an 8-bit
RegisterRegister
An 8-bit register can stores 8-bit or 1 Byte
data

13. A set of 8-bit register will form a
Memory
Ten 8-bit registers
i.e. 10 bytes of
memorymemory
can store 10 bytes
of data
10 x 8 bit memory
Or
10 byte memory

14. 11 Register 3
10 Register 2
01 Register 1
00 Register 0
Accessing Memory or Memory Interfacing
2 to 4 Decoder
00
01
10
11
A0
A1

15. Calculate the address lines required for 10 K Byte
memory chip
1 K Byte = 1024 Byte of memory
Then 10 K Byte = 10 x 1024 Byte of memory
i.e. this memory chip has 10240 number of 8-bit registers
(default register size is 8-bit)(default register size is 8-bit)
Consider n number of address lines required
Then 2n = 10240
Or n = 13.32 ≈ 14
So 14 number of address lines required

16. Consider the number of address lines are 13. Calculate
the number of memory chips required to access total
address space if each memory chip is 1024 x 8 bit
Total addressable space using 13 address line is
213 Byte = 23 x 210 Byte = 8 x 1024 Byte = 8 K Byte
Each memory chip is 1024 x 8 bit
= 1024 Byte
Number of memory chip required
(8 x 1024)
1024
= 8

17. Accessing memory can be summarized into the following
three steps:
 Select the chip.
 Identify the memory register.
 Enable the appropriate buffer.
The microprocessor having N number of wires in its
address bus; uses part of the address bus to select the
The microprocessor having N number of wires in its
address bus; uses part of the address bus to select the
chip and the remaining part goes through the address
decoder to select the register.
The control signals IO/M (to select I/O device or
memory), WR (enable writing) and RD (enable reading)
are used to activate the operation.

18. Consider a microprocessor having 16 bit Address Bus
 Maximum addressable memory space
216 Byte = 210. 26 Byte = 26 KByte = 64 KByte
 Starting address will be
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 And last address will be And last address will be
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
 It is more convenient to use Hexadecimal number
 In Hex code starting and last address will be
0000 H and FFFF H

19. Explain the memory address range
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH

20. A15
A14
A13
A12
A11
A10
A9
Draw the memory map to access 256 Byte
memory using 16 bit address line
256 Byte
A7
A6
A5
CS
A9
A8
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 7F00H
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFH
256 Byte
Memory
A4
A3
A2
A1
A0
For addressing 256 Byte memory we
required only 8 address line (A0 to A7).
Remaining 8 address lines (A8 to A15) is
used of chip selection

21. Memory
Primary
Memory
RAM ROM
Secondary
Memory
Hard Disk,
Memory
Classification
RAM
Static RAM
Dynamic
RAM
ROM
Erasable
EPROM EEPROM
Flash
Memory
Permanent
Masked
ROM
PROM
Hard Disk,
Floppy, CD

22. Random Access Memory (RAM)
• Stores bit as voltage
• High speed
• More expensive
• High power consumption
Static RAM (SRAM)
• High power consumption
• Stores bit as charge
• Low speed
• Less expensive
• Low power consumption
• Requires frequent refreshing
Dynamic RAM (DRAM)

23. Read Only Memory (ROM)
Masked ROM
• Bit pattern is permanently masked
Programmable ROM (PROM)
• Program is burnt into the memory only once
Erasable PROM (EPROM)
• Program can be erased using UV ray
Electrically EPROM (EEPROM)
• Program can be erased using electrical signals
Flash Memory
• It can be erased and reprogrammed a million times