Microprocessor 8085

1. MICROPROCESSOR 8085
LECTURE 19
MEMORY INTERFACING-II
PROF. SANDIP DAS

2. TO WRITE INTO OR READ FROM ANY ONE OF THE
REGISTERS: SPECIFIC REGISTER SHOULD BE
ENABLED
Register 3
Register 2
Register 1
Register 0
Output Buffer
Input Buffer
2-t0-4
Decoder𝑊𝑅
𝑅𝐷
A1
A0
• Thus, 2-to-4 decoder can
perform the required function
with the use of two input lines A0
and A1.
• These two input lines can have
four different bit combinations
(00,01,10,11) and each
combination can enable one of
the registers namely Register 0 to
Register 3.
• Thus, the Enable signal of the
flip-flops is replaced by two
address lines.
outputs
inputs

3. 4X8 BIT REGISTER
Register 3
Register 2
Register 1
Register 0
Output Buffer
Input Buffer
2-t0-4
Decoder𝑊𝑅
𝑅𝐷
A1
A0
outputs
inputs
4x4 4x4
A1
A0
𝑊𝑅
𝑅𝐷
A1
A0
inputs inputs
outputs outputs

4. HOW TO SELECT BETWEEN TWO CHIPS
111 Register 7
110 Register 6
101 Register 5
100 Register 4
011 Register 3
010 Register 2
001 Register 1
000 Register 0
A1
A0
A2
𝑊𝑅𝑅𝐷
𝑊𝑅𝑅𝐷
Register 3
Register 2
Register 1
Register 0
Register 7
Register 6
Register 5
Register 4
011
010
001
000
11
1
11
0
10
1
10
0
A1
A0
A1
A0
𝑅𝐷 𝑊𝑅𝐶𝑆 𝑅𝐷 𝑊𝑅𝐶𝑆
A2
I/O lines I/O lines
I/O lines

5. Suppose, we have four address lines and two memory chips with four registers
each. How to design?
Register 3
Register 2
Register 1
Register 0
0011
0010
0001
0000
A1
A0
𝑅𝐷 𝑊𝑅𝐶𝑆
I/O lines
A3
A2
Register 11
Register 10
Register 9
Register 8
1011
1010
1001
1000
A1
A0
𝑅𝐷 𝑊𝑅𝐶𝑆
I/O lines
A3
A2

6. SUMMARY
• A memory chip requires address lines to identify a memory register. The
number of address lines required is determined by the number of registers
in a chip (2 𝑛=Number of registers, n is the number of address lines).
• A memory chip requires a chip select 𝐶𝑆 signal to enable the chip. The
remaining address lines of the microprocessor can be connected to the 𝐶𝑆
signal through an interfacing logic.
• The address lines connected to 𝐶𝑆 select the chip and the address lines
connected to the address lines of the memory chip select the register. Thus
the memory address of a register is determined by the logic levels (0/1) of
all the address lines)
• The control signal read 𝑅𝐷 enables the output buffer and data from the
selected register are made available on the output lines. Similarly, the
control signal 𝑊𝑅 enables the input buffer and data on the input lines are
written into the memory cells.

7. TYPICAL MEMORY MODEL
R/W
memory
Or
RAM
An
A0
Data
lines
𝑅𝐷 𝑊𝑅𝐶𝑆
Address
lines
ROM
A0
Data
lines
Address
lines
An
𝐶𝑆 𝑅𝐷