MICROPROCESSOR 8086
LECTURE 32
8086 MICROPROCESSOR PIPELINED ARCHITECTURE
PROF. SANDIP DAS
ARCHITECTURE OF 8086-INTRODUCTION
• 8086 Contains two independent
functional units: Bus Interface Unit (BIU)
and Execution Unit (EU)
• The BIU handles transfer of data and
addresses between the processor and
memory I/O devices.
• The EU receives opcode of an
instrument from the queue, decodes it
and then executes it.
• While EU is decoding an instruction or
executing an instruction, the BIU
fetches instruction codes from the
memory and stores them in the queue.
• The BIU and EU thus operate in parallel
independently and this type of
BIU
EU
MEMORY
PIPELINING IN 8086
Non-pipelined 8085
Pipelined 8086
Fetch 1 Execute 1 Fetch 2 Execute 2
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
T1 T2 T3 T4
T1 T2 T3 T4
ARCHITECTURE OF
8086
The Execution
Unit executes
instructions for
the processor
ARCHITECTURE OF
8086
Can be
addressed
either as 8 bit
register or 16
bit register
When
addressed as
8-bit register
AL-
Accumulator
low
AH-
Accumulator
High
When
addressed as
16-bit register
AX
BX
CX
DX
ARCHITECTURE OF
8086
Segment registers are used
to address memory space-
either RAM,ROM or the I/O
space
The address compute
engine converts the logical
address that is held by the
segment registers into
physical address
Internal memory holds the
Instruction queue
BUS INTERFACE UNIT
CODE SEGMENT
EXTRA SEGMENT
STACK SEGMENT
DATA SEGMENT
1 MB
SEGMENTED
MEMORY

30. 8086 microprocessor pipelined architecture

  • 1.
    MICROPROCESSOR 8086 LECTURE 32 8086MICROPROCESSOR PIPELINED ARCHITECTURE PROF. SANDIP DAS
  • 2.
    ARCHITECTURE OF 8086-INTRODUCTION •8086 Contains two independent functional units: Bus Interface Unit (BIU) and Execution Unit (EU) • The BIU handles transfer of data and addresses between the processor and memory I/O devices. • The EU receives opcode of an instrument from the queue, decodes it and then executes it. • While EU is decoding an instruction or executing an instruction, the BIU fetches instruction codes from the memory and stores them in the queue. • The BIU and EU thus operate in parallel independently and this type of BIU EU MEMORY
  • 3.
    PIPELINING IN 8086 Non-pipelined8085 Pipelined 8086 Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 T1 T2 T3 T4 T1 T2 T3 T4
  • 4.
    ARCHITECTURE OF 8086 The Execution Unitexecutes instructions for the processor
  • 5.
    ARCHITECTURE OF 8086 Can be addressed eitheras 8 bit register or 16 bit register When addressed as 8-bit register AL- Accumulator low AH- Accumulator High When addressed as 16-bit register AX BX CX DX
  • 6.
    ARCHITECTURE OF 8086 Segment registersare used to address memory space- either RAM,ROM or the I/O space The address compute engine converts the logical address that is held by the segment registers into physical address Internal memory holds the Instruction queue
  • 7.
    BUS INTERFACE UNIT CODESEGMENT EXTRA SEGMENT STACK SEGMENT DATA SEGMENT 1 MB SEGMENTED MEMORY