The document discusses the 8259 Programmable Interrupt Controller (PIC), which supports up to eight hardware interrupting devices and interrupts the processor when a device delivers a signal. The PIC is required for systems with more than four I/O devices since the 8085 processor can only handle four interrupt requests. The PIC architecture allows multiple PICs to be cascaded in a master-slave configuration so that the slave PIC interrupts the master which then interrupts the processor, and the master and slave work together to provide the interrupt service routine address to the processor.

1. MICROPROCESSOR 8085
LECTURE 29
8259 PROGRAMMABLE INTERRUPT CONTROLLER
PROF. SANDIP DAS

2. WHY PROGRAMMABLE INTERRUPT
CONTROLLER?
• 8085 can handle up to four
interrupt request from I/O
device.
• So, if more than four I/O device
requests to communicate using
interrupt lines then it won’t be
possible.
• Thus, to design a more
complex system with many I/O
devices PIC is required.

3. 8259 PIC
• Supports up to eight hardware interrupting
device
• The processor is interrupted whenever the
interrupting device delivers a signal to the
8259

4. ARCHITECTURE OF 8259

5. CASCADING 8259 USING MASTER SLAVE
CONFIGURATION
Master Slave
To
Processor

6. HOW DOES MASTER-SLAVE WORK?
• The slave 8259 creates an interrupt trigger on the Master as
soon as it receives an interrupt trigger at one of its eight input
lines.
• The master in turn interrupts the processor.
• The processor reads the Interrupt Service Routine Address.
• The master 8259 informs the corresponding Slave 8259 to
release the ISR address onto the data bus.
• The processor reads this information and executes the
appropriate Interrupt Service Routine.