Control unit-implementation

Control Unit ImplementationControl Unit Implementation
Control Unit Implementation CS510 Computer Architectures Lecture 5- 1

6-Step Instruction Cycle
Memory
Access time
Memory
Access time
… . . .
[1] MAR PC(address), M R(control)
[3] Decode instruction
Control Signal Generator IR,
Address Processor MBR(address)
[4] MAR Effective Address, M R/W
… . . .
[2] IR MBR(OP-code)
[6] Decide final PC by this time,
go to [1] for the next instruction
[5] Data path activation to do
operation

Micro-Operation
Micro-operation
Rd: Destination Register
Rs1, Rs2: Source Register
ALU
f
Register
File
CPU data path
A Micro-operation generates a finite set of Control Signals at the
proper time according to the Machine State and the Control Data to
activate the Micro-actions and to update the Control Data Structure.
Simple data move: Rd fI(Rs1, φ)
Unary operations: Rd fu(Rs1, φ)
Binary operations: Rd fb(Rs1, Rs2)
Rd f(Rs1, Rs2)

Micro-Action/Micro-Operation
Micro-action
- An Activation of a part of data path
Bus Register Output
Register Input Bus
- Selection of a function of the Functional Unit(ALU), Memory
ALU: ADD, OR, SHR, etc
Memory: R(read), W(write)
Rd fADD(Rs1, Rs2)
Input Bus 1 Rs1
Input Bus 2 Rs2
ADD
Rd Output Bus
ALU
f
Register
File
Micro-operation
- A micro-operation can be described in terms of a sequence of
micro-actions

Activation of Micro-action:
An Example
Rd fADD(Rs1, Rs2)
ALU . . .
Rs1 Rs2
Rd
ADD
SUB
AND
Input Bus 1
Input Bus 2
Output Bus
Input Bus 1 Rs1
Input Bus 2 Rs2
ADD
Rd Output Bus

Control Point
Control Point:
Hardware locations(gates) to which control signals
are applied to achieve the intended set of functions
(a sequence of micro-operations, each of which
may also be a sequence of micro-actions)
• Register In-Gates
• Register Out-Gates
• ALU function selection terminals
• Memory read/write control signal terminal

Control Points:
Register In-Gate and Out-Gate
Register In-GatesRegister Out Gates
… Q . . . Send R1
R1
Send R2
R2
Send R3
R3
R1
Load R1
R2
Load R2
R3
Load R3
… Q . . .
… Q . . .
… D . . .
… D . . .
… D . . .Bus

Control Points:
ALU Function Selection Points
X Y
Cc
A
C
DI
C0
Cm
Cr
Ri
Li
Ro
Lo
PS
AN
AO
NS
LS
RS
SE
Z
Adder
Logic
Unit
Shifter

Independent Control Point
Example:
32-bit machine with 8 registers
ALU has 4 different functions in 32-bit data in parallel
Memory has 1 terminal for R/W
No. of Control Points:
(32 x 8 x 2) + (32 x 4) + 1 = 641
During an instruction execution, usually a group of bits
are transferred together as an information
Instruction: OP-code, Register Address, Memory Address
Floating point numbers: Sign bit, Exponent, Mantissa
Others: A number, A character or a character string
Each of these groups actually need an identical control
signal for each bit within the group
-> Each group is associated
with one Independent Control Point
No. of Independent Control Points
(8 x 2) + 4 + 1 = 21

Independent Control Points:
Around MBR
MBR M
BUS MBR(O)
BUS MBR(A)
From ALU
...
To ALU
... ...
Memory Bus
M
......
M MBR
BUS
MBR M
MBR
0...56...15
0...5...15
M MBR
MBR BUS
M MBR
BUS MBR(OP )
BUS MBR(A)
BUS MBR
BUS MBR(O)
BUS MBR(A)

Micro-Operation Timing
• Execution Time of a Micro-Operation - Micro-Cycle Time
required to change the information in a set of registers
• CPU Clock is the most basic timing signal used for the reliable operation of
CPU and CPU Clock Cycle is equal to the Micro-Cycle
• Information need to be stored in a register at the end of each micro-cycle,
otherwise, information will be lost
• Micro-Cycle is determined by the characteristics of FF’s(setup time, hold time,
delay) used in registers and the propagation delay of the circuits (ALU) in
between the source and destination registers
– Micro-Cycle may vary depending on the micro-operation
• Signal path, Type of ALU operation

Micro-Cycle
• Synchronous Fixed: There is only one Micro-Cycle, i.e., all micro-operations’
execution times are assumed to be identical
• Synchronous Variable: Certain long micro-operations are allowed to take multiple
cycles without causing a state transition, i.e., different micro-cycle lengths are
allowed
– e.g. Consider the different time requirements by R <- fI(R) and R <- fb(R, R)
• Asynchronous: No clock or external mechanism that determines a state transition.
Hardly used to control the execution of instructions
Micro-Cycle Time
It can be broken down into Control Time and Data Path Time
– Control Time
• Time to decode control data and generate control signals
– Data Path Time
• Time to transmit control signals and transfer data
– Control Time and Data Path Time are partially overlapped in some
high performance machines

Generation of Control Signals
Control Data
Machine State
Timing
Control SignalControl Rule
Microprogram or
Combinational logic circuit
E.g. In state(Machine Cycle) S1, at time(timing state) t1: R1 f(R2, R3)
Clock
IBus1 R2, IBus2 R3
f
R1 OBus
S1
t1
Machine Cycle
Timing State

Intra-Instruction Sequencing
Instruction
Fetch
Instruction
Address
Decision
Instruction
OP-code
Decode
Operand
Address
Compute
Operand
Address
compute
Operand
Fetch
Operation
Specified
Operand
Store

RISC-S ArchitectureRISC-S ArchitectureRISC-S ArchitectureRISC-S Architecture
Rd fu(Rs1) Rd fb(Rs1, Rs2)
Rd Rs1 Rd Rs1, Rs2 f
PC MBR MAR (R, R) Numerical Calculation
MBR PC PC (R, IR(addr)) Logical Calculation
MAR R R (PC, IR(addr)) Shifts
IR +4
R
Instruction =4 bytes
IBus1
Memory
IBus2
OBus
MAR
MBR
IR
PC
+4
Register
File
ALU

Instruction Set - RISC-S
Instruction Operand Operation
ADD Rs1, Rs2(S2), Rd Rd Rs1 + Rs2
SUB Rs1, Rs2(S2), Rd Rd Rs1 - Rs2
AND Rs1, Rs2(S2), Rd Rd Rs1 ^ Rs2
OR Rs1, Rs2(S2), Rd Rd Rs1 v Rs2
SLL Rs1, Rd Rd logical Shift Left(Rs1)
LD S2(Rs1), Rd Rd M[Rs1 + S2]
ST S2(Rs1), Rd M[Rs1 + S2] Rd
JMP COND, S2(Rs1) (COND=1): PC Rs1 + S2
CALL Rd, S2(Rs1) Rd PC, next PC Rs1 + S2
RET S2(Rs1) PC Rs1 + S2
Representative Instructions
ADD Rs1, Rs2, Rd Integer Addition
SLL Rs1, Rd Logical Shift Left 1 bit
LD S2(Rs1), Rd Load a word
JMP COND, S2(Rs1) Conditional Branch

Micro-Operations for RISC-S
ADD SLL LD JMP
[1]
[2]
[3]
[4]
[5]
[6]
[7]
MAR PC, R;
PC PC + 4;
IR MBR;
Decode IR;
Rd Rs1 + Rs2;
MAR PC, R;
PC PC + 4;
IR MBR;
Decode IR;
T/F(test condition),
T: PC Ts1 + S2;
MAR PC, R;
PC PC + 4;
IR MBR;
Decode IR;
MAR Rs1 + S2, R;
MAR PC, R;
PC PC + 4;
IR MBR;
Decode IR;
Rd shl Rs1;
. . .
Rd MBR;

Major State - Machine Cycle
During a Major State, a memory reference is made, i.e. a Machine Cycle
includes a Memory Cycle
FETCH: Read an instruction from memory specified by the address in
PC, and whatever left to do before making transition to FETCH,
EXECUTE, or INDIRECT machine cycle
EXECUTE: For the instructions with an operand in memory, read operand
to perform operation specified in the instruction, and make a
transition to FETCH machine cycle
INDIRECT: Read effective address from memory, and make a transition to
FETCH or EXECUTE machine cycle - not happen in RISC
2g-address instruction:
R f(R, R) When does the operation(f) take place ?
(1+X)- or (1+g+X)-address instruction:
When does the address calculation take place?

Machine Cycles
FETCH
INTERRUPT
R-to-R, JMP(direct address)
INDIRECT
Memory Reference(Indirect address)
JMP Indirect
EXECUTE
Memory Reference
Interrupt
RISC-S does not have
Indirect Machine Cycle

Machine State Register
(Major State Register)
Major State Q1 Q0
FETCH 0 0
INDIRECT 0 1
EXECUTE 1 0
INTERRUPT 1 1
FET←INT
INT←FET EXE←FET
INT←EXE INT←FET
FET←INT
FET←FET FET←EXE
FET←EXE
EXE←FET INT←EXE
FET←FET
J Q0 J Q1 FET
FF0 FF1
K Q0' K Q1' IND
Clock
EXE
INT
Q0 Q1
t3

Timing State
Timing State Counter - A counter that advances for each CPU clock pulse
- Counter advances in the period of Micro-cycle
- Counter resets at the maximum count, i.e., at the
beginning of each Machine Cycle
CPU Clock
Machine Cycle
t0
t1
t2
t3
Memory Cycle
(Memory Active)
Memory Access time
(Read Data available)
A timing state counter counts from 0 to 3

Machine Cycle:
Various Addressing Modes in AC Machines
Immediate Address PC Relative Address Direct Address Indirect Address
ADD #X ADD $X ADD X ADD @X
[1] t0
[2] t1
[3] t2
[4] t3
[5] t0
[6] t1
[7] t2
[8] t3
[9] t0
[10] t1
[11] t2
[12] t3
Notice that memory cycle is 4 times slower than the micro-cycle(3 micro-cycle Access
Time), and that 4 micro-cycle machine cycle is possible with a faster memory.
MAR MBR, R;
-
-
-
MAR MBR, R;
-
AC AC + MBR;
-
MAR MBR, R;
PC PC + 4;
IR MBR, Decode;
MBR MBR(A);
MAR MBR, R;
PC PC + 4;
IR MBR, Decode;
MBR PC+MBR(A);
MAR MBR, R;
-
AC AC + MBR;
-
MAR MBR, R;
-
AC AC + MBR;
-
MAR MBR, R;
PC PC + 4;
IR MBR, Decode;
MBR MBR(A);
MAR MBR, R;
PC PC + 4;
IR MBR, Decode;
MBR AC+MBR(A);
FETCH; INDIRECT; EXECUTE

Machine Cycle - RISC-S
ALU Control
ADD SLL LD JMP
t0 MAR PC, R; MAR PC, R; MAR PC, R; MAR PC, R;
t1 PC PC + 4; PC PC + 4; PC PC + 4; PC PC + 4;
t2 IR MBR, Decode; IR MBR, Decode; IR MBR, Decode; IR MBR, Decode;
t3 Rd Rs1 + Rs2, Rd shl Rs1, MAR Rs1 + S2, T/F(test condition),
T: PC Rs1 + S2,
RI: INTERRUPT, RI: INTERRUPT, RI: INTERRUPT,
RI’: FETCH; RI’: FETCH; RI’: FETCH;
t0 R;
t1 -
t2 Rd MBR;
t3 RI: INTERRUPT,
RI’: FETCH;
FETCH; EXECUTE

ALU Control
X Y
Cc
A
C
DI
C0
Cm
Cr
Ri
Li
Ro
Lo
PS
AN
AO
NS
LS
RS
SE
Z
Adder
Logic
Unit
Shifter

ALU Control Micro-Actions
ICPs C0 Cm A DI Cc Cr AN AO PS NS LS RS SE
Add 0 0 1 0 0 0 d 0 0 1 0 0 1
Increment 1 0 1 1 0 0 d 0 0 1 0 0 1
1’s Compl Add 0 1 1 0 0 0 d 0 0 1 0 0 1
2’s Compl Add 1 1 1 0 0 0 d 0 0 1 0 0 1
AND d d 0 d 0 0 1 1 0 1 0 0 1
OR d d 0 d 0 0 0 1 0 1 0 0 1
Compl AC 0 1 1 1 0 0 d 0 0 1 0 0 1
Left Shift 0 d 0 d 0 0 d 0 1 0 1 0 1
Right Shift 0 d 0 d 0 0 d 0 1 0 0 0 1
Pass d d 0 d 0 0 d 0 1 1 0 0 1
Clear AC d d 0 d 0 0 d 0 0 0 0 0 0
Clear C d d 0 d 0 1 d 0 0 0 0 0 0
Compl C d d 0 d 1 0 d 0 0 0 0 0 0

Constraints on Concurrency
Micro-operation concurrency
– Hardware resource conflict
Bus conflict
MAR MBR(addr) AC AC’
AC AC + MBR MAR MBR(addr) + IX
– Register dependency
– However, multiple fan-out of registers may be OK
These are concurrent micro-operations if Adder
and shifter are independent units.
R2 SHL(R1)
R4 R1 + R3
These are not concurrent micro-operations
even if Adder and shifter are independent units.
R2 SHL(R1)
R1 R2 + R3

Instruction and Machine Cycles
Number of Instruction
Machine Cycles
1 Stack Computer: Functional
AC Computer: Unary Functional, Control not with Indirect Addr
GPR Computer: R-R instructions, Control not with Indirect Addr
2 Transfer and Control Instructions not with Indirect Address
AC Computer: Functional
GPR Computer: R-M Instruction not with Indirect Address
3 Transfer Instruction with Indirect Address
AC Computer: Functional with Indirect Address
GPR Computer: R-M Instruction with Indirect Address
4 M-M Instruction not with Indirect Address
5 M-M Instruction with 1 Indirect Address
6 M-M Instruction with 2 Indirect Address

Control Rules for RISC-S
State Micro-Operations
Instruction Decode;
Functional: FU, Transfer: XF(Load: LD, Store: LD’), Control: CT, I/O: IO
Interrupt Request;
RI
EXE.t3 RI: INT, RI’: FET,
EXE.t2 (XF.LD): Rd MBR;
EXE.t1 (XF.LD’): MBR Rd;
(FU’.XF’.CT’.IO): -;
(FU’.XF’.CT. IO’)^(T): PC f(Rs1, S2), RI: INT, RI’: FET,
(FU’.XF. CT’.IO’): MAR f(Rs1, S2), EXE,
FET.t3 (FU. XF’.CT’.IO’): Rd f(Rs1, Rs2), RI: INT, RI’: FET,
FET.t2 IR MBR, Decode;
FET.t1 PC PC + 4;
FET.t0 MAR PC, R;
EXE.t0 (XF.LD): R, (XF.LD’): W;

Implementation Of CU
- Hardwired Implementation -
...
OP-code Cond
Rs1
Rs2
Rd
SCC
S2(imm)
Control Data
Control Logic Circuit
Major State
Timing State
Control Unit
IR Flag
Control Data
IndependentControlPoints
CPU

Microprogrammed Control UnitMicroprogrammed Control Unit

Microprogrammed Control Unit
In this topic, we will study
– Micro-instruction
• Data path control and Sequence control information
• Vertical micro-instruction and Horizontal micro-instruction
– Microprogramming RISC-S
• RISC-S Architecture and Instruction Set
• Vertical micro-instruction format
• Microprogramming with Vertical micro-instruction
• Horizontal micro-instruction format
– Microprogram control unit
– Advantages and Disadvantages of microprogram

Microprogrammed Control Unit
U-program
Control
Unit
CSAR
Control
Storage
Decoder
ControlPoint
IR Flag
Status
of CPU
Control Unit CPU
Branch Address
Micro-instruction

Micro-Instruction
• Micro-instruction should contain
– Data Path Control information
• Information needed to generate control signals required to activate the data path in the
CPU to execute intended micro-operation(s)
• Representation of the data path control information
– Horizontal Micro-instruction - Direct micro-instruction
– Vertical Micro-instruction - Encoded micro-instruction
– Sequence Control information
• A part of information needed to generate the next micro-instruction address
• e.g., Branch address
• One micro-instruction may contain both information,
• Or, Two types of micro-instructions
– Data path control micro-instruction
– Sequence control micro-instruction

Horizontal Micro-Instruction
Each of the bits in the data path control information is directly connected to an independent
control point, i.e., each bit is associated with a micro-action
– Data path control information field is very long
– Decoder is not needed to generate control signals, decoding delay is absent
– Very fast to execute a micro-instruction
– Concurrent micro-operation can be specified if there are multiple data paths
– However, in an ordinary machine, micro-instruction bit utilization is poor, thus control storage
utilization is inefficient
– Very high performance machines can only afford to have HM
Sequence Control
Control Points
CPU
0 1 2 3 n-1

Vertical Micro-Instruction
Data path control information is represented by a
set of fields, each of which represents a set of
micro-actions associated with a similar hardware
resources, e.g: INBUS1, OUTBUS, ALU, Registers,
Memory, etc
– Information in each field is encoded to reduce the micro-instruction length, thus
micro-instruction length is short
– Decoder is needed for each encoded field
– Concurrency is low, but micro-instruction bit utilization is good, thus control
storage utilization is efficient
– Generation of control signal is slow due to decoding delay
– Easy to make symbolic micro-instructions
– Most of commercially available machines employ VM

Encoding Control Information
• Direct Encoding
• Indirect Encoding
. . .
... ... ...
...
Sequence Control
. . .
...
Sequence Control
...
...

Micro-Action
• Micro-action that activates a data path
– Selection of a register whose content can be sent to a bus
» INBUS1 R2
– Selection of a register that stores the information on a bus
» R3 OUTBUS
• Micro-action that makes the selection of ALU function
– For 2’complement ADD
» A, C0, Cm, DI’, Cc’, Cr’, AO’, NS, SE
• Micro-action that activates the memory control
– Memory Read(R) and Write(W) control
» R(R) or R’(W)

Example - Architecture:
RISC-S
Memory
Register
File
ALU Flag
MAR
MBR
IR
PC
+4
INBUS2
INBUS1
OUTBUS

Example - Instruction Set:
RISC-S
OP-code Symbol Operands Operation
Op-code SCC Rd Rs1 S2
Cond 1 imm13
0 Rs2
31 24 23 19 18 13 12 0
F: Represents the Function of the instruction
T: Represents the Type of the instruction
000: Functional, 101: Transfer, 010: Sequencing
0 00 0000 ADD Rs1,Rs2,Rd Rd Rs1 +Rs2
0 00 0001 SUB Rs1,Rs2,Rd Rd Rs1 - Rs2
0 00 0100 AND Rs1,Rs2,Rd Rd Rs1 ^ Rs2
0 00 0101 OR Rs1,Rs2,Rd Rd Rs1 v Rs2
0 00 1000 SLL Rs1,Rd Rd logical shift left Rs1
1 01 0000 LD S2,Rd Rd M[PC+S2]
1 01 0001 ST Rd,S2 M[PC+S2] Rd
0 10 0000 JMP CD,S2 (COND=1):PC←PC+S2
0 10 0001 CALL Rd,S2 Rd PC, next PC←PC+S2
0 10 0010 RET S2 PC←PC+S2

Vertical Micro-Instruction for RISC-S:
Data Path Control
• Memory Control Field(M: 2 bits)
– Memory is either Read or Write, or No-operation, i.e. needs to represent 3 kinds
M
00 NOP
01 Not used
10 W(Memory MBR)
11 R(MBR Memory)
• Arithmetic Function Control Field(AF: 2 bits)
– ADD, 2’ Complement ADD, Pass, Disable - needs to represent 4 kinds
AF
00 Disable
01 Pass
10 ADD(Rd Rs1 + Rs2)
11 2’ complement ADD(Rd Rs1-Rs2)

Data Path Control
• Logical Function Control Field(LF: 2 bits)
– AND, OR, Disable - needs to represent 3 kinds
LF
00 Disable
01 Not used
10 OR(Rd Rs1 V Rs2)
11 AND(Rd Rs1 ^ Rs2)
• Shift Function Control Field(S: 1 bit)
– Either shift left or pass the shifter - needs to represent 2 kinds
S
0 Pass
1 Shift left(Rd SLL(Rs1))

Data Path Control
• Input Bus - INBUS1(IN1: 2 bits)
– MBR, PC, R(Rs1), Disable - needs to represent 4 kinds
Memory
Register
File
ALU Flag
MAR
MBR
IR
PC
+4
INBUS2
INBUS1
OUTBUS
IN1
00 Disable
01 INBUS1 PC
10 INBUS1 Rs1
11 INBUS1 MBR
• Input Bus - INBUS2(IN2: 2 bits)
– R(Rs2), IR[imm13(S2)], IR[Rs2(S2)], Disable - needs to represent 3 kinds
IN2
00 Disable
01 Not used
10 INBUS2 IR(imm13)
11 INBUS2 Rs2

Data Path Control
• Output Bus - OUTBUS(OUT: 3 bits)
– MAR, MBR, PC, IR, R(Rd), Disable - needs to represent 6 kinds
OUT
Memory
Register
File
ALU Flag
MAR
MBR
IR
PC
+4
INBUS2
INBUS1
OUTBUS
000 Disable
001 MAR OUTBUS
010 MBR OUTBUS
011 PC OUTBUS
100 IR OUTBUS
101 Rd OUTBUS
110,111 Not used
• PC Control Field(P: 1 bit)
– PC increment, Disable increment - needs to represent 2 kinds
P
0 Disable
1 PC PC + 4

Sequence Control
• Branch set
• Branch set with condition codes
– Least significant m bits of address are replaced by the m conditions codes
• Complete conditional branch
– If CC specified by Cond field is equal to the C-value, address specified in the micro-instruction is the branch address
Data Path Control xx
Data Path Control Cond Branch Address
Data Path Control Cond C-value Branch Address
xx Next address
00 uPC(repeat)
01 uPC + 1
10 uPC + 2
11 uPC + 3

Sequence Control
• Conditions in RISC-S
– CPU Flags: C, Z, S, O
– Machine language instruction OP-code field: T(t0t1t2) and F(f0f1f2f3)
• Branch types: FLG(3 bits)
FLG
000 Not branching
001 Unconditional branch
010 Conditional branch on CPU flags(COND field in machine instruction)
011 Not used
100 Conditional branch on T flags
101 Conditional branch on F flags
110,111 Not used
Data Path control FLG FVAL address
25 3 4 8
• Conditional branch micro-instruction must specify Branch Type(FLG: 3
bits) and Values of the specified Flags(FVAL: 4 bits)
– Maximum number of flags to be tested against the values is 4(CPU
flags, F flags)

Vertical Micro-Instruction
for RISC-S
Vertical micro-instruction formats for RISC-S
Data path control micro-instruction for RISC-S
Sequence control micro-instruction for RISC-S
0 M P AF LF S IN1 IN2 OUT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15
M P AF LF S IN1 IN2 OUT FLG FVAL Branch Address
0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 17 18 21 22 31
1 FLG FVAL Branch Address
0 1 3 4 7 8 15

Microprogram Model
FETCH
Routine
Instruction 1
Execution
Routine
Instruction 2
Execution
Routine
Instruction n
Execution
Routine

FETCH Routine
• Instruction Fetch
– Read Instruction from memory to store in IR
• Decode Instruction
– Separate instruction fields and store them in buffers
T I(31-29), F I(28-25), SC I(24), COND I(22-19),
Rd I(23-19), Ss1 I(18-14), Ss2 I(4-0), D I(12-0)
– Extend the displacement of the operand’s address into a 32-bit
displacement
S2 (I(12))19
#D (sign extension)
– Fetch operands from registers
Rs1 Reg[Ss1]
Rs2 Reg[Ss2]

FETCH Routine
MAR PC, R
PC PC + 4
IR MBR, Decode
T=0?
T=5?
T=2?
T=3?
F
FC XF SQ IO
Illegal OP-code
Interrupt
y
y
y
y
n
n
n
n
Instruction Decoding can be done either by hardware or microprogram.
We assume that decoding hardware does as follows;
OP-code(I31-I25): T(t0t1t2), F(f0f1f2f3)
T: Instruction Type
F: Function Type

Execution Routine - Functional
Control Unit Implementation CS510 Computer Architectures
Lecture 5- 50
FC
F=0?
F=1?
F=4?
F=5?
F=8?
y
y
y
y
y
n
n
n
n
n
Rd Rs1 + Rs2
F
Rd Rs1 - Rs2
Rd Rs1 ^ Rs2
Rd Rs1 v Rs2
Rd shl Rs1
Illegal OP-code

Execution Routine - Transfer
XF
F=0?
F=1?
MAR Rs1 + S2, R
n
ny
y
MBR Rd
F
Illegal
OP-code
Rd MBR
MAR Rs1 + S2, R

Execution Routine - Sequencing
SQ
F=1?
F=0?
F=3?COND=1?
Rd PC
PC Rs1 + S2
PC Rs1 + S2
F
n
n
n
n
y
y
y
y
Illegal
OP-code

Symbolic Microprogram
for RISC-S
FETCH: MAR PC, R; ORR: Rd Rs1 v Rs2, goto FETCH;
PC PC + 4; SHFTR: Rd shl Rs1, goto FETCH;
IR MBR, decode;
if T=Func goto FUN; XFR: if F=LD goto LOAD;
if T=Trans goto XFR; if F=ST goto STORE;
if T=Seq goto SEQ; goto OTHERXFR;
goto IO; LOAD: Rd M[Rs1+S2], goto FETCH;
FUN: if F=ADD goto ADDR; STORE: M[Rs1+S2] Rd, goto FETCH;
if F=SUB goto SUBR;
if F=AND goto ANDR; SEQ: if F=JMP goto JUMP;
if F=OR goto ORR; if F=CALL goto CALL;
if F=SLL goto SHFTR; if F=RET goto RETURN;
goto OTHERFUN; goto OTHERSEQ;
ADDR: Rd Rs1 + Rs2, goto FETCH; JUMP: if COND=true goto RETURN;
SUBR: Rd Rs1 - Rs2, goto FETCH; goto FETCH;
ANDR: Rd Rs1 ^ Rs2, goto FETCH; CALL: Rd PC;
RETURN: PC Rs1 + S2, goto FETCH;

Decoding Micro-Instruction
in RISC-S
X Y
Cc
A
C
DI
C0
Cm
Cr
Ri
Li
Ro
Lo
Adder
Logic
Unit
Shifter
S L
Z
PS
AN
AO
NS
LS
RS
SE

Decoding Micro-Instruction
in RISC-S
AF field A C0 Cm DI Cc Cr AO AN PS NS LS RS SE
AF=ADD 1 0 0 0 0 0 0 d 0 1 0 0 1
AF=SUB 1 1 1 0 0 0 0 d 0 1 0 0 1
AF=Pass 0 d 0 1 0 0 0 d 1 1 0 0 1
AF=Disa 0 d d d 0 0 0 d 0 d d d 0
LF field
LF=OR 0 d d d 0 0 1 0 0 1 0 0 1
LF=AND 0 d d d 0 0 1 1 0 1 0 0 1
LF=Disa 0 d d d 0 0 0 0 0 1 0 0 1
LF=unusedd d d d d d 0 d d d d d d
S field
S=Disa d d d 0 0 0 0 d 0 1 0 0 1
S=left 1 0 0 0 0 0 0 d 0 0 1 0 1

Horizontal Micro-Instruction
for RISC-S
Decoded form of control information in the
micro-instruction
M0 M1 P C0 Cm A DI Cc Cr AN AO PS NS LS RS SE IN1 IN2 OUT FLG
FVAL address
2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3
4 n

Microprogram Control Unit
• In-line execution
– We know it is simple if we have a uPC
• Repeat execution
– Disable incrementing uPC
• Conditional and Unconditional branch
– Target address or a part of the target address in the micro-instruction
– Branch conditions: CPU flags, Instruction’s T and F flags
• Loop
– We need a conditional branch and an iteration counter
– Loop counter(LCTR, and LZ flag that represents the state of LCTR, LZ is set to 1 when LCTR
represents 0
• Micro-routine call and return
– We know it is simple if we have a stack
– PUSH the return address when CALL, and POP for indirect branch

Redefining FLG Field
Definition of FLG field
FLG Micro-instruction execution sequenceNext micro-instruction
0000 In-line sequencing uPC
0001 Unconditional branch address
0010 Repeat uPC
0011 Beginning of loop uPC
0101 CALL address
0110 RETURN Stack
1000 Conditional branch on T address
1001 Conditional branch on F address
1100 Conditional branch on CPU flags address
1101 Conditional branch on LZ flag address
0100, 0111, 1010, 1011, 1110, 1111 are not used
We need a address MUX at the
input of CSAR

Address MUX and
Loop Counter
LZ
LCTR
S0
S1
AMUX
CSAR
uPC
+1 DPC
Stack
SP
Control Storage
Micro-instruction
addressC
PSH POP
=0
S0 S1 Address
0 0 Not used
0 1 uPC
1 0 address
1 1 stack
AMUX Control

Decoding Flag Field
FMUX
Z Z 1 1 1
S S 1 1 1
C C 1 1 1
O O 1 1 1
CPU FVAL
T0 T1 T2 1
F0 F1 F2 F3
LZ 1 1 1
En
Compare
=
FLG FVAL
S1 S0
PSH
POP
FLGD
DPC
0000 0d1d
1ddd
0110
0d01
0110
(0010+
0101)

Advantages of Microprogram
• Flexibility and adaptability are high
• Makes the development time shorter
• Convenient for developing a computer family
design
• Easy to develop ICs
• Maintenance and error detection/correction
cost is lower
• Development of Universal host

Disadvantages
of Microprogramming
• Inherently slow
• Not economic for a simple low cost machines

Control unit-implementation

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