The document discusses address sequencing in a microprogram control unit. It begins by defining key terms like control address register, which stores the initial address of the first microinstruction. It then explains that the next address generator is responsible for selecting the next address from control memory based on the current microinstruction. Microinstructions are stored in control memory in groups that make up routines corresponding to each machine instruction. The document also discusses control memory, hardwired control vs microprogrammed control, and examples of next address generation and status bits.
2. DEFINITION:
To appreciate the address sequencing in a micro
program control unit.
An initial address is loaded into the control address
register when power is turned on in the computer.
this address is usually the address of the first
microinstruction that activities the instruction fetch
routine.
3. Sequencer
Routine
Mapping
Process of address sequencing
Control unit
hardwire control
microprogrammed control
Microinstruction
Microprogram
4. SEQUENCER:
Next address generator
selection of address for control memory
ROUTINE:
Microinstruction are stored in control memory in groups with each group
specify a routine.
each computer instruction has its own micro program routine.
MAPPING:
INSTRUCTION CODE:
address in control memory where routine is locate is called mapping
process.
5. Incrementing of the control address register
Unconditional branch or conditional
branch,depending on status bit conditions
Mapping process
A facility for subroutine call and return
6. CONTROL MEMORY:
CONTROL UNIT:
Initate sequences of microoperations:control
signals in a bus organized system by the groups of
that select the path in multiplexer
TWO TYPES:
Hardwire control: the control logic is implemented
with gater f/fs,decoder,and other digital circuit.
Microinstruction:the instruction store in control
memory is called microinstruction.
7. DYNAMIC MICRO PROGRAMMING:
RAM can be used for writing
Microprogram is loaded initially from an
audilary memory.
A many user sequence of memory collections of
data in memory address.
9. Example (RISC architecture concept
RISC(Reduced instruction set computer)system
use hardwired control rather than micro
programmed control.
Next address
generator
Control
address
register
Control
memory
Control
data
register
Next address information
10. Multiplxer
Car increment
Jmp
Mapping control program
Subroutine return
car:
Increment
Branch
Mapping logic
Sbr
11. STATUS BITS
Control the conditional branch decision
generator in the branch logic
Branch logic
Test the specified condition and branch to the
indicated address.
12. 1:1 bit for indirect addressing
Opcode:4-bit operation code Address for system
memory.
1 OPCODE ADDRESS
15 14 0
F1 F2 F3 CD BR AD
13. VERTICAL:
Each micro instruction specified single path to
be performed.
Width is narrow,n control signals encoded into log2
bits
f1 f2 f3 Micro instruction address
Jump conditionFunction code
14. Each micro instruction specifies many different
micro operations to be performed.
Wide memory word
High degree of parallel operation possible.
internal cpu control signals Micro instruction address