This document presents an FPGA implementation of a genetic algorithm for identifying parameters of linear and nonlinear auto regressive moving average (ARMA) models. The genetic algorithm uses 6-bit fixed-point arithmetic to reduce hardware costs. Experimental results show the design can accurately identify parameters for both linear and nonlinear models using low FPGA resources.

1. FPGA Based Implementation of a Genetic Algorithm
for ARMA Model Parameters Identification
Abstract
In this work, we propose an FPGA implementation of a genetic algorithm (GA) for linear and nonlinear auto regressive moving average
(ARMA) model parameters identification. Specifically designed genetic operators for adaptive filtering applications are proposed to improve
processing performance and robustness to the quantization effect, making low bit-wordlength fixed-point arithmetic implementation possible,
which permit hardware cost saving. The design was implemented using 6-bit wordlength representation. The implementation experiments
show high parameters identification capabilities for both linear and nonlinear models, and low footprint.
An FPGA implementation of a GA for linear and nonlinear auto
regressive moving average (ARMA) model parameters identification
has been presented. The design considered low wordlength fixed-
point arithmetic processing environment. The implementation shows
high signal processing performances and low resources cost, where
only 6-bits wordlength fixed-point arithmetic was used in all
operations.
[1] T. Cassar, K. P. Camilleri, and S. G. Fabri, "Order Estimation of Multivariate ARMA Models,"IEEE Journal of
Selected Topics in Signal Processing, vol. 4, pp. 494-503, 2010.
[2] V. Duong and A. R. Stubberud, "System identification by genetic algorithm," IEEE Aerospace Conference
Proceedings, 2002, pp. 5-2331-5-2337 vol.5.
[3] Cheng-Yuan, C. and C. Deng-Rui, "Active Noise Cancellation Without Secondary Path Identification by Using an
Adaptive Genetic Algorithm," IEEE Transactions on Instrumentation and Measurement, 59(9), 2010, pp. 2315-2327.
[4] D. Massicotte and D. Eke, "High robustness to quantification effect of an adaptive filter based on genetic algorithm, "
IEEE Northeast Workshop on Circuits and Systems (NEWCAS), 2007, pp. 373-376.
[5] H. Merabti and D. Massicotte, "Towards Hardware Implementation of Genetic Algorithms for Adaptive Filtering
Applications," IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 2014, to appear.
Fig. 8 SQNR performance for the identification
problem considering 6-bits wordlength implementation.
Hocine MERABTI and Daniel MASSICOTTE
Université du Québec à Trois-Rivières
Department of electrical and computer engineering
{Hocine.Merabti, Daniel.Massicotte}@uqtr.ca
G
Ĝ ∑
+
-
( )x n
( )u n
( )y n
( )e n
ˆ( )y n
1 1 1
( ) ( ) ( ) ( )
N M P
L k k k
k k k
y n a y n k b x n k c u n k
  
       
Fig. 7 Identification problem.
……...
Parent 2
MUX
……...
Parent 1
MUX
……...
Random
weight (y)
Random
weight (x)
……...
MUX MUX MUX. . . . . . . . Crossover
position
……...
……...
Child
0 0 0 111
……...
MSBMSB LSBLSB
Proposed Hardware Architectures
ARMA Model
D Q D Q D Q D Q
D Q D Q D Q D Q
……...
……...
Rng[0] Rng[1] Rng[18] Rng[19]
Rng[20] Rng[21] Rng[40] Rng[41]Clk
V(n) V(n-1) ……... V(n-Window+1)
Data input vector
w1 w2 ……... wm
Chromosome
(RNG or mutation block)
MUX
V . W
Adder
Abs
Reg
w1 w2 ……... wm
Chromosome
f(n)
Fitness score
Reg
d(n) d(n-1) ……... d(n-Window+1)
Desired signal
MUX
Add-accumulate
w1 w2 ……... wm
Chromosome
f(n)
Fitness score
Sorter
Parents
pool 2
Parents
pool 1
In
DEMUX
Out
In
Out
w1 w2 ……... wm
Parent 1
w1 w2 ……... wm
Parent 2
DEMUXDEMUX
Random
selection
Random
selection
Addr Addr
Simplified
truncation
……...
Chromosome
MUX Random
weight (x)
……...
……...
……...
New chromosome
……...
……...
Random word
. . . . . . .
Start
Generate
Initial population
Apply fitness
function
Selection
Crossover &
Mutation
Add offspring to
new population
Full?
g=G?
Output best
chromosome
Stop
Yes
Yes
No
No
Fig. 1 GA flowchart.
Fig. 2 42-bits LFSR based RNG.
.
Fig. 3 Fitness block. Fig. 4 Selection block.
Fig. 5 Crossover block.
Fig. 6 Mutation block.
     
1
n
n B
f n d n y n
 
 
( ) tanh( ( ))NL NL Ly n v y n
0 200 400 600 800 1000 1200 1400 1600 1800 2000
-5
0
5
10
15
20
25
30
iteration (n)
SQNR(dB)
nonlinear ARMA
linear ARMA
Theroretical
Implementation Results
Conclusion References
Resource utilization Available Used
Slice registers 4800 889 (18%)
Slice LUTs 2400 1415 (58%)
Total Slices 600 498 (83%)
Parameters Rate
Maximum clock frequency 105 MHz
Maximum group rate 320 KGen/sec
Table 1. Post place-and-route implementation summary.
Table 2. Timing performance.
 For the nonlinear system:
 For the linear system:
  
22
1 1
ˆ( ) 10log
M M
i i i
i i
SQNR n w w w n
 
 
 
 
  
 The signal processing performance
analysis is done on the SQNR
given by:
( ) v ( ).W( )T
Ly n n n
 Target FPGA:
Xilinx Spartan-6 xc6slx4-3tqg144
 GA parameters:
Population size: 16
Smoothing window (B): 16
The 24th ACM Great Lakes Symposium on VLSI (GLSVLSI), 21-23 May 2014, Houston, Texas, USA
 ( ) ( 1), ( 2), ( 5), ( 6), ( ), ( 1), ( 2)
T
n y n y n x n x n u n u n u n      v
 1 2 7( ) ( ) ( ) ( )
T
n w n w n w nw L