The document discusses various components used in memory chips including row decoders, column decoders, sense amplifiers, and memory cell designs. It provides the following key details: 1. Row decoders select one of several row lines using a binary address and the number of transistors needed scales with the address size. Column decoders connect one of several bit lines to the data I/O line and can be implemented with pass-transistor logic and decoders. 2. Sense amplifiers are critical components that amplify small voltage differences on bit lines into full logic levels for reading memory cells. They use a differential amplifier design and operate by equalizing bit lines initially and then sensing and amplifying a voltage difference. 3. Memory

1. Row Address Decoder
A NOR address decoder in array form.
One out of eight lines (row lines) is
selected using a 3-bit address.
Number of transistors needed for a NOR
row decoder with an K-bit address is K2K
(NMOS) + 2K (PMOS) = (K + 1)2K

2. Decoders
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
The function of the column-address
decoder is to connect one of the 2N
bit lines to the data I/O line of the
chip.

3. Column Decoder
Column Decoder is basically a multiplexer
and can be implemented using pass-
transistor logic in combination with
Decoder.
Column Decoder should match the pitch of the bit line
Number of transistors needed for coulmn
decoder with an K-bit address is K2K
(NMOS) + 2K (PMOS) + 2K = (K + 1)2K + 2K

4. 4-input pass-transistor based column decoder
Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count
2-input
NOR
decoder
A 0
S0
BL 0 BL 1 BL 2 BL 3
A 1
S1
S2
S3
D
Better performance can be obtained by utilizing
transmission gates in place of NMOS transistor. In
such a case, however, the decoder needs to provide
complementary output signals.

5. Tree Decoder
An alternative implementation of the
column decoder that uses a smaller
number of transistors (but at the
expense of slower speed of operation)
since a relatively large number of
transistors can exist in the signal
path, the resistance of the bit lines
increases, and the speed decreases
correspondingly.

6. 4-to-1 tree based column decoder
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
buffers
progressive sizing
combination of tree and pass transistor approaches
Solutions:
BL 0 BL 1 BL 2 BL 3
D
A 0
A 0
A 1
A 1

7. Sense Amplifier
Sense amplifier is the most critical component in a memory chip.
Sense amplifiers are essential for proper operation of DRAMs, and their use in SRAMs
results in speed and area improvements.
In general a differential amplifier is used to implement sense amplifier.
Since the amplifier is differential it can be directly used with SRAM (SRAM cell utilizes
both the BL and BL Lines) and with slight modification, it can be used with 1T DRAM.
Slight difference in the Bit Lines voltage (in mV) is responded by the sense amplifier
by providing a full-swing (0 to VDD) signal at its output terminals

8. Sense Amplifiers
tp
C DV

Iav
----------------
=
make DV as small
as possible
small
large
Idea: Use Sense Amplifer
output
input
s.a.
small
transition

9. 3-Transistor DRAM Cell
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL -VTn
WWL
BL 1
M1 X
M3
M2
CS
BL 2
RWL
VDD
VDD 2 VT
DV
VDD 2 VT
BL 2
BL 1
X
RWL
WWL

10. The Voltage-Transfer Characteristic
The Voltage-Transfer Characteristic
The VTC of the inverter exhibits a very
narrow transition zone, when both
transistors are simultaneously on,
and in saturation region. This region
show the gain of inverter, which is very
high, as the steep of the slope show
VOH and VOL are VDD and
GND, respectively.
Switching Threshold VM
 Vin=Vout
 both PMOS and NMOS are
always saturated, since VDS = VGS.
VIH, and VIL can be obtained by
equating the current of PMOS
and NMOS in theses respective
regions
VM

11. Sense Amplifier
Transistors Q5 and Q6 act as switches that connect the
sense amplifier to ground and VDD only when data-sensing
action is required. This will conserve power.
during a read operation, if the cell has a stored 1, then a
small positive voltage will develop between B and B, with vB
higher than vB. The amplifier will then cause vB to rise to VDD
and vB to fall to 0 V.
Sense amplifier is a latch formed by cross-coupling two
CMOS inverters
When φp goes high (to VDD) prior to a read operation, all three
transistors conduct. While Q8 and Q9 precharge the B and B
lines to VDD/2, transistor Q7 helps speed up this process by
equalizing the initial voltages on the two lines.

12. Differential Sense Amplifier
Directly applicable to
SRAMs
M4
M1
M5
M3
M2
VDD
bit
bit
SE
Out
y

13. Differential Sensing ― SRAM
VDD
VDD
VDD
VDD
BL
EQ
Diff.
Sense
Amp
(a) SRAM sensing scheme (b) two stage differential amplifier
SRAM cell i
WL i
2
x
x
VDD
Output
BL
PC
M3
M1
M5
M2
M4
x
SE
SE
SE
Output
SE
x
2
x 2
x
y
y
2
y

14. Latch-Based Sense Amplifier (DRAM)
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
EQ
VDD
BL BL
SE
SE