Reconfigurable computing combines the flexibility of software with the high performance of hardware by using field-programmable gate arrays (FPGAs). There are several open challenges in reconfigurable computing including designing tools to simplify programming FPGAs, developing effective algorithms for FPGA placement and routing as these problems are computationally hard, minimizing the silicon area used, developing effective approaches for partitioning applications between hardware and software, and efficiently mapping and partitioning applications onto FPGAs.

1. Research Challenges in
Reconfigurable Computing
Sudhanshu Janwadkar

2. What is Reconfigurable Computing??
• Reconfigurable computing is a computer architecture
combining some of the flexibility of software with
the high performance of hardware
• It uses very flexible high speed computing fabrics
like field-programmable gate arrays (FPGAs).

3. Challenges in Reconfigurable Computing
 Reconfigurable computing systems is still a maturing
field and there are many open research questions.
 Over the last ten years numerous new reconfigurable
architectures have been proposed .
 However, there is not an existing framework to allow
quantitative analysis of these architectures

4. Challenges
1. Designing tools
2. FPGA Placement
3. Routing
4. Smallest silicon area
5. Effective partitioning approach
6. Mapping and partitioning of application

5. 1.Designing Tools
 A crucial challenge in developing RC architectures is
to create CAD tools and programming environments
that enable designer to use HLLS.
 This would allow designers to abstract the low-level
hardware of the RPF and to simplify programming the
architecture, while still achieving speedup over a
traditional processor.

6. 2.FPGA Placement
 A large commercial FPGA contains approximately
500,000 functional blocks, leading to approximately
500,000! Possible placements.
 The greatest challenge facing FPGA is FPGA
placement i.e. the need to produce high quality
placements for ever-larger circuits.
 Without a high quality placement, a circuit generally
cannot be successfully routed.

7. Continued…
 Furthermore, placement is a computationally hard
problem, so there are no known algorithms that
produce optimal results in practical central processing
unit (CPU) time.
 Consequently, the development of fast and effective
heuristic placement algorithms is a very important
research area

8. 3. Routing
 Unlike ASICs and printed circuit boards (PCBs),
FPGAs have a fixed amount of interconnect.
 The usual approach in placement is to minimize the
wiring resources anticipated for routing signals.
Although this reduces the overall demand for
resources, signal inevitably compete for the same
resources during routing.
 The challenge is to find a way to allocate resources
so that all signals can be routed.

9.  The second goal, minimizing delay, requires the use of
minimum-delay routes for signals, which can be
expensive in terms of routing resources, especially
for high-fanout signals.
 Thus, the solution to the entire routing problem
requires the simultaneous solution of two interacting
and often competing sub problems.
Continued…

10. 4.Smallest Silicon Area
 The different area occupying elements are switch
boxes, wires, interconnects.
 Balancing the cost of more wires with the needs of
typical digital circuit was important to making a cost-
effective device that would be commercially
successful.
 Covering as many potential circuit designs as possible
at as high a speed as possible, but with the smallest
silicon area, is still the challenge FPGA device
architects must confront

11. 5.Effective Partitioning
Approach
 Developing an approach for hardware/software
partitioning requires the consideration of granularity,
evaluation, alternative region implementations,
implementation models, exploration, and so forth, and
each such issue involves numerous options.
 The result is a tremendously large partition solution
space and a huge variety of approaches to finding
good partitions .
 A key future challenge will be the development of
effective partitioning approaches for these
increasingly complex formulations.

12. 6.Mapping & Partitioning of
Applications
 Reconfigurable computers can exploit parallelism at
many different levels of granularity, from coarse-
grained parallel tasks to fine-grained instruction-level
parallelism.
 The challenge is to partition and map the application
onto the inherently parallel fabric of lookup tables,
DSP blocks, and memories.