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Interconnects in Reconfigurable Architectures
The document discusses the importance and characteristics of interconnects in reconfigurable architectures, specifically in FPGAs. It covers various aspects including area considerations, delay and noise effects, types of interconnects, routing methods, and the implications of Rent’s rule on chip design and performance. The text emphasizes the significant role of interconnects in determining overall functionality and efficiency in semiconductor chips.
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Interconnects in Reconfigurable Architectures
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- 2. Introduction Chips are mostlymade of wires called interconnects, which form the physical connection between two transistors. Interconnects are basically metal layers that are fabricated along with transistors, and it depends on the technology and foundry the number and characteristics of the layers.
- 3. Introduction Alternate layersof such interconnects run through- out the chip orthogonally
- 4. Introduction They arefabricated of different metal layer
- 5. Introduction Dominant contributor todie area & cycle time Support large functional density Parallel data routing FPGA’s place most of the area into interconnect
- 6. Affecting factors Affectingparameters in interconnects Speed Power Noise
- 7. The Area considerations 4-LUT is roughly 600Kl2 . The flip-flop and 16:1 LUT multiplexor make up very little of this area, easily less than 20Kl2 . estimates the area of the 4-LUT multiplexor with flip-flop as 13K l2 The majority of the area associated with each 4-LUT (97%), goes into programmable interconnect and its configuration memory The area required for the full LUT, including its configuration memory, is less than 10% of the area of the 4-LUT cell
- 8. The Delay Considerations Vendors lump interconnect timing with evaluation time of lookup table Interconnect typically accounts for 80% of the path delay
- 9. The Noise Considerations- Crosstalk A capacitor does not like to change its voltage instantaneously A wire has high capacitance to its neighbor. When the neighbor switches from 1→ 0 or 0→ 1, the wire tends to switch too. Called capacitive coupling or crosstalk Crosstalk effects Noise on non switching wires Increased delay on switching wires Crosstalk causes noise on non switching wires
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- 11. Local interconnect Lowestlevel of interconnect Used for very short interconnects at device level Higher resistivity Do not travel long distances Withstand higher processing temperatures
- 12. Semi Global interconnect Usedto connect devices within the block Mid length wires for communication within a block is placed in this category Used because complexity of interconnects is increasing
- 13. Global Interconnect Upperlevel of interconnects Mostly made up of aluminum Used to connect long interconnects between the blocks, including power, ground & clocks Low resistivity Length increases as transistors per chip increases
- 14. Island Style-FPGA blockdiagram
- 15. Interconnects in FPGAArchitecture
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- 17. The programmablerouting between the Logic Blocks consists of fixed metal tracks Fixed metal tracks run horizontally and vertically, and are organized in channels Each channel contains the same number of tracks Switch Block defines all possible connections between channels Flexibility of each Switch Block is a key to the overall flexibility and the routability Interconnects Routing
- 18. Types of SwitchBlocks Disjoint switch block Universal switch block Wilton switch block - Two types of switches are used in switch block
- 19. The ConnectionBlock defines all the possible connections from a horizontal or vertical channel to a neighboring logic block The connections in the switch blocks and connection blocks are made by programmable switches A programmable switch consists of a pass transistor controlled by -a static random access memory cell (SRAM- based FPGA) -an anti-fuse (anti-fuse FPGAs) -a non-volatile memory cell (floating gate devices) Interconnects Routing
- 20. SRAM cellsbased FPGAs - can be reprogrammed by the end user as many times as required and are volatile Anti-fuse based FPGAs - can only be programmed once and are non-volatile NVRAM based FPGAs- floating gate technology - can be reprogrammed and are non-volatile Types of FPGAs based on Interconnects
- 21. Interconnect structure forRC analysis tox and Kox are the oxide thickness and dielectric constant
- 22. Parasitic Resistance andCapacitance The metal wires and antifuse contribute significant parasitic resistance and capacitance The parasitic resistance and capacitance result in large signal propagation delay and power consumption
- 23. Rent’s Rule In1960,E.F Rent, IBM employee stated that - Interfacial growth is driven by functional increase in semiconductor chips - Number of interconnections increases as a power function of number of circuits with N gates - No. of i/p and o/p Interconnections - No. of gates in circuit p – Rent’s Exponent (It denotes the degree of interconnection complexity) - typically for logic functions 0.5 < p < 0.7
- 24. Rent’s Rule VsIntel Data
- 25. Rent's ruleis an empirical result based on observations of existing designs Less applicable to the analysis of non-traditional circuit architectures It provides a useful framework with which to compare similar architectures.
- 26. Test yourself Whatare the different types of Interconnects in RC architectures? What is Rent’s rule? How do you correlate it with Moore’s law?