FPGA BASED VLSI DESIGN FPGAs allow designers to emulate IC designs using programming languages like VHDL and Verilog before final hardware implementation. FPGAs contain programmable logic blocks and interconnects that can be configured to implement different digital circuits. Common FPGA architectures include a 2D array of configurable logic blocks and routing channels that can be programmed to connect logic blocks according to a design. FPGAs offer advantages like reprogrammability, fast development times, and performance gains for software applications.

1. FPGA BASED VLSI DESIGN
Debargha Chakraborty
1. Introduction
Several design styles can be considered for chip implementation of specified algorithms or
logic functions using VLSI technique. Each design style has its own merits and demerits, thus
a proper choice has to be made by designers in order to provide specified functionality at low
cost and in a timely manner.
It is an integrated circuit that is designed in such a way that it allows us to configure its
internal connections using programming languages such as VHDL and Verilog. These chips
are very useful for IC designers in that they allow designers/verification engineers to emulate
designs and ensure proper functionality in the hardware domain. Any IC design using VHDL
or Verilog can be emulated on these FPGA.
2. Origin
Standard Cell Based Design
The other ASIC architecture was the standard cell, which started as a blank die. The standard
cell vendor created a library of logic gates and higher-level logic functions called cells. The
customer created a design from this library. The standard cell vendor provided place-and-
route software that placed each cell onto the die and wired them all together to create the
customer's design. Because only cells that the design specifically required were placed on the
chip, the chips were smaller and thus cost less per piece than a gate array. The tradeoff was
that the initial costs were not shared by other customers because each customer's standard cell
chip was completely unique.
Gate Array Design
Gate arrays consisted of regular arrays of unconnected transistors. The chips were complete
except for metal layers needed to connect the transistors. The gate array vendor would mass-
produce these chips. Software provided by the gate array vendor, called a place-and-route tool,
would map the logic gates of the customer's design – NANDs, NORs, flip-flops, and so forth –
to specific transistors on the chip and determine a good way to put metal traces on the chip to
connect the transistors so as to complete the design. Because all customers used the same basic
platform, the costs associated with creating these base wafers were shared among all the
customers. Thus, the initial NRE (non-recurring expense) for a gate array was fairly cheap,
though it could still be in the thousands or tens of thousands of dollars.
Field Programmable Gate Array
Around the mid-eighties, Xilinx pioneered the Field Programmable Gate Array (FPGA), so-
named because its architecture resembled the gate array, but it could be programmed by the
customer to perform a specific function. With an FPGA, the array consisted not of transistors

2. but of logic blocks that contained memories used to implement logic, multiplexers to select
signal sources, and flip-flops. Because these were programmed by the user, the routing had to
all be in place on the chip. This was done by placing metal traces all over the chip but keeping
them unconnected. At junctions between unconnected traces were transistors that could be
turned on by setting a bit in the chip, thus creating a slow but definite connection between the
traces, hence they have very low Non Recurring Expenses.
3. Architecture
FPGA contains a two dimensional arrays of logic blocks and interconnections between logic
blocks. Both the logic blocks and interconnects are programmable. Logic blocks are
programmed to implement a desired function and the interconnects are programmed using the
switch boxes to connect the logic blocks.
To be more clear, if we want to implement a complex design (CPU for instance), then the
design is divided into small sub functions and each sub function is implemented using one
logic block. Now, to get our desired design (CPU), all the sub functions implemented in logic
blocks must be connected and this is done by programming the interconnects.
The most common FPGA
architecture consists of an
array of logic blocks called
Configurable Logic Block
(CLB), or Logic Array Block
(LAB), depending on vendor,
I/O pads, and routing
channels. Generally, all the
routing channels have the
same width (number of
wires). Multiple I/O pads
may fit into the height of one
row or the width of one
column in the array.
An application circuit must be mapped into an FPGA with adequate resources. While the
number of CLBs/LABs and I/O required is easily determined from the design, the number of
routing tracks needed may vary considerably even among designs with the same amount of
logic. For example, a crossbar switch requires much more routing than asystolic array with
the same gate count. Since unused routing tracks increase the cost (and decrease the
performance) of the part without providing any benefit, FPGA manufacturers try to provide
just enough tracks so that most designs that will fit in terms of Lookup tables (LUTs) and I/O
can be routed. This is determined by estimates such as those derived from Rent's rule or by
experiments with existing designs. The main advantage of FPGA is ability to reprogram.

3. 4. Design
There are four basic methods for FPGA based design: Hardware Description Language, state
machine and schematic. These roughly correspond to decreasing levels of abstraction.
Hardware Description Language
HDL's excel in complex but well-defined designs, where one knows exactly what it is that
their logic must do, but what it needs to do is complex and involved. If one thinks in an
"algorithmic" or software-like way, HDL's will be the tool they will be most comfortable
with. The tools for HDL have extraordinary sophistication, with plenty of verification and
simulation options, lots of different flavors of synthesis entry, and usually a great many
options in the program itself. HDL's are also, oddly, very good for really quick, simple logic
functions that you don't feel like taking the time to figure out how the hardware would have
to be for them.
The downside of HDL's is that the abstraction isolates very much from the details of what's
going on in the hardware. Typically one doesn't have ultimate control over how the software
will actually implement the design on the chip. Furthermore, although the range of functions
you can implement is amazing, abstracting the functionality still means that at a certain level
you limit your design to the kinds of logic functions and blocks that the designers of the
software envisioned. So HDL's are things you to use with care, mostly to design relatively
mature logic functions.
State Machine
State machine entry works well when the design is simple and has a linear flow. If one thinks
in a sequential way, visualizing logic as a series of states that the system steps through, the
FSM entry method will be logical, and could perhaps get quite complex, depending on how big
of a state machine visualized. It's great for simple controllers, especially ones with feedback
where a state-machine description is fitting and natural. Even relatively complex, closed-loop
control systems are good with this kind of system. Nevertheless, it really comes into its own
with semi-simple functions, ones that may be more clear with a visual representation.
State machine synthesis is really for a narrow application range, where you're doing
something simple, well-defined, and probably control-system oriented.
Schematic
Schematic entry gives far more insight into what's happening at a gate-level. For a
"hardware" person, this will be a natural way to design. One can actually see what the gate
implementation is, and this will give you a better immediate feel for timing issues, data paths,
and simply what's actually going on in a design. Very, very complex logic can be designed and
it's easier to optimize the design for the specific device. It eliminates a lot of the associated
abstraction problems of HDL's, simply because everything happens at a more primitive level.
Also, one can instantly see how complex a function is *actually* going to turn out to be, so
they can be either eliminated or redesigned if it turns out to be too expensive. It is more

4. flexible, because the tool lets you create logic much more with a specific view to the hardware
capabilities of the chip. It may help also to de-mystify what's happening at a hardware level.
The big downside of schematic entry is that it's very difficult to modify the design, still
harder to port it to a different device. It basically locks one into the device and design they
envision at the present. Also a lot of debugging is expected because it doesn't isolate from
implementation-level errors, i.e. the logic may be right, but the implementation schematic
may be faulty, something you can avoid with HDL's.
5. Advantages
 Long time-availability.
 Can be updated and upgraded at customer’s site.
 Extremely short time to market.
 Fast and efficient systems.
 Performance gain for the software applications.
 Real time applications.
 Massively parallel data processing.
6. References
 Leblebici Yusuf, Sung-Mo Kang “CMOS Digital Integrated Circuit: Analysis and Design”.
ISBN-13: 978-0-07-053077-7, ISBN-10: 0-07-053077-7.
 “The Death of the Structured ASIC”, April/May 2016 http://chipdesignmag.com/. Retrieved
from http://chipdesignmag.com/print.php?articleId=434?issueId=16 on 28th
August 2015.
 Chaitanya Mandapati Krishna, “FPGA Design Flow”, http://www.vlsi-world.com/.
Retrieved from http://www.vlsi-world.com/content/view/28/47/1/0/ on 28th
August 2015.
 Rast Alex, Philip Freidin, “Schematics vs Verilog / VHDL”, July 16, 2001
http://www.fpga-faq.com/. Retrieved from http://www.fpga-
faq.com/FAQ_Pages/0024_Schematics_vs_Verilog_VHDL.htm on 29th August 2015.
 “Field-programmable gate array”, https://en.wikipedia.org/. Retrieved from
https://en.wikipedia.org/wiki/Field-programmable_gate_array on 29th August 2015.
 Jassal Gulshan “Comparison Between FPGA vs ASIC || VLSI design” June 28, 2015
http://ecetracker.com/. Retrieved from http://ecetracker.com/comparison-between-fpga-vs-
asic-vlsi-design/ on 29th
August 2015.