The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio (SDR) with high degree of flexibility and low power consumption has been a major challenge to the
scientific community ever since its conception. The basic philosophy of SDR is to implement different modulation or demodulation schemes on the same underlying hardware. Currently available high performance DSP processors, optimized with ‘Very Large Instruction Word (VLIW)’ architecture and multiply and accumulate (MAC) units, are unable to meet the near real time speed requirements of
Software Defined Radios (SDR) due to their inherent sequential execution of compute intensive signal
processing algorithms. Moreover, their power dissipation is considerably high. Even though, Application Specific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of their lack of flexibility. Various references on FPGA based implementations of reconfigurable architectures for SDRs are also available. However, the Look-up Table (LUT) based implementations of FPGAs are not
optimum and therefore, cannot offer highest performance at low silicon cost. Keeping this view, this paper presents the design of a configurable communication processor for Software Defined Radio. The proposed
scheme features the performance of an ASIC based design combined with the flexibility of software. Experimental results reveal that the proposed architecture has minimum hardware requirement, improved silicon area utilization and low power dissipation.
Wi MAX Deinter leaver’s Address Generation Unit through FPGA Implementationijceronline
The IEEE 802.16 standard, commonly known as WiMAX has broadband wirelessaccess over long distance. WiMAX has evolved from 802.16 to 802.16d for fixedwireless access and IEEE 802.16e standard is for mobility support. WiMAX Forumcreated the name "WiMAX". The forum describes WiMAX as "a standards-based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL". WiMAX is similar to Wi-Fi, but it can enable usage at much larger scale and at faster speeds [1]. Inorder to minimize the effect of burst error, the channel interleaver/deinterleaver employed in the WiMAX transreceiver is used. The channel interleaver/deinterleaver consists of two memory blocks and an address generator. The objective of this project is to implement an area and delay efficient circuitry for address generator for WiMAX 2- D Deinterleaver using the Xilinx FPGA for all permissible code rates and modulation schemes. This project also build up a generalized circuit for all permissible Ncbps without manual computation of column number.
Smart Grid solution offers improved efficiencies and cost savings.
The Truckee Donner Public Utility District (PUD) provides electric and water service
to 24,000 customers in the Truckee, California area. It is a non-profit, publiclyowned
utility governed by elected officials, and has an 86 year history of providing
quality service at reasonable prices.
Truckee Donner PUD has used Schneider Electric technology since 2000, when it
implemented ArcFM™. Since then, the utility has also implemented
Schneider Electric’s Designer and Responder products.
My presentation at the workshop on Federated Satellite Systems, held at Skolkovo University (Skoltech) on October 14th 2014. Its title: "Software Defined Radio: an Enabling Technology for Interoperability in Federated Satellite Systems".
A Project Report Submitted in Partial Fulfillment of the Requirements for the Degree of BACHELOR OF ENGINEERING in
(COMMUNICATION)
BY
AKRM ABDULAH RASSAM (91048)
AMAL ABDULRAHMAN HAMOUD (10003)
MOHAMMED ABDULJABBAR QAID (10029)
MOHAMMED ABDUL-RAHMAN (91028)
NADA YASIN ABDULSALAM (10038)
SAMAR ABDULKAWE ALSHARAIE (10016)
SUPERVISOR
DR. REDHWAN QASEM SHADDAD
TAIZ, YEMEN
2015
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicro...VLSICS Design
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation mplemented in <0.18µm.
Wi MAX Deinter leaver’s Address Generation Unit through FPGA Implementationijceronline
The IEEE 802.16 standard, commonly known as WiMAX has broadband wirelessaccess over long distance. WiMAX has evolved from 802.16 to 802.16d for fixedwireless access and IEEE 802.16e standard is for mobility support. WiMAX Forumcreated the name "WiMAX". The forum describes WiMAX as "a standards-based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL". WiMAX is similar to Wi-Fi, but it can enable usage at much larger scale and at faster speeds [1]. Inorder to minimize the effect of burst error, the channel interleaver/deinterleaver employed in the WiMAX transreceiver is used. The channel interleaver/deinterleaver consists of two memory blocks and an address generator. The objective of this project is to implement an area and delay efficient circuitry for address generator for WiMAX 2- D Deinterleaver using the Xilinx FPGA for all permissible code rates and modulation schemes. This project also build up a generalized circuit for all permissible Ncbps without manual computation of column number.
Smart Grid solution offers improved efficiencies and cost savings.
The Truckee Donner Public Utility District (PUD) provides electric and water service
to 24,000 customers in the Truckee, California area. It is a non-profit, publiclyowned
utility governed by elected officials, and has an 86 year history of providing
quality service at reasonable prices.
Truckee Donner PUD has used Schneider Electric technology since 2000, when it
implemented ArcFM™. Since then, the utility has also implemented
Schneider Electric’s Designer and Responder products.
My presentation at the workshop on Federated Satellite Systems, held at Skolkovo University (Skoltech) on October 14th 2014. Its title: "Software Defined Radio: an Enabling Technology for Interoperability in Federated Satellite Systems".
A Project Report Submitted in Partial Fulfillment of the Requirements for the Degree of BACHELOR OF ENGINEERING in
(COMMUNICATION)
BY
AKRM ABDULAH RASSAM (91048)
AMAL ABDULRAHMAN HAMOUD (10003)
MOHAMMED ABDULJABBAR QAID (10029)
MOHAMMED ABDUL-RAHMAN (91028)
NADA YASIN ABDULSALAM (10038)
SAMAR ABDULKAWE ALSHARAIE (10016)
SUPERVISOR
DR. REDHWAN QASEM SHADDAD
TAIZ, YEMEN
2015
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicro...VLSICS Design
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation mplemented in <0.18µm.
Design and analysis of optimized CORDIC based GMSK system on FPGA platform IJECEIAES
The gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements.
Enabling 5G X-Haul with Deterministic Ethernet - A TransPacket whitepaperIvar Søvold
Transpacket (www.transpacket.com) explores the concept of Ethernet X-Haul in a newly released whitepaper. Discussed extensively in the mobile industry in connection with 5G, the idea is to have an Ethernet based converged transport network serving multiple purposes including fronthaul and backhaul. The whitepaper presents the RAN architectures under consideration for 5G, and their consequences in terms of requirements for the transport network. It further describes how an innovative Ethernet scheduling mechanism is required to support deterministic Ethernet, and to fully achieve an 5G Ethernet X-Haul. It also introduces two use cases, namely Ethernet Crosshaul, and Indoor Coverage, which demonstrate the added value of deterministic Ethernet for mobile transport applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance evaluation of VLC system using new modulation approachjournalBEEI
We propose a modified OFDM modulation based on multiband scheme for visible light communications (VLC) system. The method called catenated-OFDM VLC system can efficiently boost the propagation distance and combat multipath induced the inter symbol interference and inter carrier interference. Design parameters such as number of optical bands, input power, distance and data rate are varied to see their effect on the system performances. Simulation analysis is done using Optisys software Ver. 11.0. The results show that the proposed system offers a good performance at longer transmission distance of 12 m for input power of 2 dBm in case of Band=3 with 10 Gbps data rate. BER curves also indicates that the proposed system can be operated at very high data rate of 15 Gbps. This exhibits the ability of the proposed system to be one of the candidate for future optical wireless communication system.
A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC ...IAEME Publication
The primary motivation of the work presented in this paper is to significantly reduce power consumption in pipe lined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables longer battery life in mobile applications, and lower cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the power dissipation in most high-speed analog to digital conversion applications. This work presents a 9 stage, 10-bit Pipe lined ADC with Error Correction Algorithm which achieves the dynamic power consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm CMOS. All the sub-blocks to generate top level Pipe lined ADC have been designed in Cadence environment and simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
IMPLEMENTATION OF A NEW IR-UWB SYSTEM BASED ON M-OAM MODULATION ON FPGA COMPO...ijwmn
This paper presents the implementation ofan Impulse Radio Ultra Wide Band (IR-UWB) communication system based on Orthogonal Amplitude Modulation (OAM) on the FPGA board (Field Programmable Gate Array). The Orthogonal Amplitude Modulationis a new modulation technique that provides a high data rate transmission, using the orthogonal waveforms named MGF (ModifiedGegenbaeur Function).In this work, the FPGA card and the converters DAC(Digital-to-Analog Converter) and ADC (Analog to Digital Converter) are considered to perform the implementation. The system is running in the simulation field
andin the real system on the hardware equipment.The obtained results show that the implementation of UWB-OAM system on FPGA board is running well andprovide a high - real time computations system.
[Case study] Dakota Electric Association: Solutions to streamline GIS, design...Schneider Electric
Applications:
Integration of GIS-based processes makes existing circuits and proposed circuits
available in the same system so operations staff can work in parallel with the designers
rather than in succession.
Customer benefits
• Model, design and manage critical infrastructure
• Highly configurable
• Easily adapted for multiple uses
• Proactively identify needed repairs and replacements well in advance
Overview 5G NR Radio Protocols by Intel Eiko Seidel
Very nice overview of the 5G Radio Interface protocol as defined by 3GPP in NR Rel.15. The document was submitted to the 3GPP workshop on ITU submission in Brussels on Oct 24, 2018.
In this paper, we propose and investigate a schottky tunneling source impact ionization MOSFET (STSIMOS)
with enhanced device performance. STS-IMOS has silicide (NiSi) source to lower the breakdown
voltage of conventional impact ionization MOS (IMOS). There is cumulative effect of both impact
ionization and source induced tunneling for the current gating mechanism of the device. The silicide source
offers immensely low parasitic resistance subsequently there is an increment in voltage drop across
intrinsic region. This leads to appreciable lowering of breakdown and threshold voltage for STS-IMOS.
Hence, it demonstrates enhanced device performance over conventional IMOS. Besides this for STS-IMOS
the location of maximum electric field has shifted towards the source and now it is quite away from gateoxide. Hence, it shows high immunity against Vth fluctuations due to hot electron damage. Consequently, itis found that device reliability is also improved significantly.
Static power optimization using dual sub threshold supply voltages in digital...VLSICS Design
Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
Design and analysis of optimized CORDIC based GMSK system on FPGA platform IJECEIAES
The gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements.
Enabling 5G X-Haul with Deterministic Ethernet - A TransPacket whitepaperIvar Søvold
Transpacket (www.transpacket.com) explores the concept of Ethernet X-Haul in a newly released whitepaper. Discussed extensively in the mobile industry in connection with 5G, the idea is to have an Ethernet based converged transport network serving multiple purposes including fronthaul and backhaul. The whitepaper presents the RAN architectures under consideration for 5G, and their consequences in terms of requirements for the transport network. It further describes how an innovative Ethernet scheduling mechanism is required to support deterministic Ethernet, and to fully achieve an 5G Ethernet X-Haul. It also introduces two use cases, namely Ethernet Crosshaul, and Indoor Coverage, which demonstrate the added value of deterministic Ethernet for mobile transport applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance evaluation of VLC system using new modulation approachjournalBEEI
We propose a modified OFDM modulation based on multiband scheme for visible light communications (VLC) system. The method called catenated-OFDM VLC system can efficiently boost the propagation distance and combat multipath induced the inter symbol interference and inter carrier interference. Design parameters such as number of optical bands, input power, distance and data rate are varied to see their effect on the system performances. Simulation analysis is done using Optisys software Ver. 11.0. The results show that the proposed system offers a good performance at longer transmission distance of 12 m for input power of 2 dBm in case of Band=3 with 10 Gbps data rate. BER curves also indicates that the proposed system can be operated at very high data rate of 15 Gbps. This exhibits the ability of the proposed system to be one of the candidate for future optical wireless communication system.
A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC ...IAEME Publication
The primary motivation of the work presented in this paper is to significantly reduce power consumption in pipe lined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables longer battery life in mobile applications, and lower cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the power dissipation in most high-speed analog to digital conversion applications. This work presents a 9 stage, 10-bit Pipe lined ADC with Error Correction Algorithm which achieves the dynamic power consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm CMOS. All the sub-blocks to generate top level Pipe lined ADC have been designed in Cadence environment and simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
IMPLEMENTATION OF A NEW IR-UWB SYSTEM BASED ON M-OAM MODULATION ON FPGA COMPO...ijwmn
This paper presents the implementation ofan Impulse Radio Ultra Wide Band (IR-UWB) communication system based on Orthogonal Amplitude Modulation (OAM) on the FPGA board (Field Programmable Gate Array). The Orthogonal Amplitude Modulationis a new modulation technique that provides a high data rate transmission, using the orthogonal waveforms named MGF (ModifiedGegenbaeur Function).In this work, the FPGA card and the converters DAC(Digital-to-Analog Converter) and ADC (Analog to Digital Converter) are considered to perform the implementation. The system is running in the simulation field
andin the real system on the hardware equipment.The obtained results show that the implementation of UWB-OAM system on FPGA board is running well andprovide a high - real time computations system.
[Case study] Dakota Electric Association: Solutions to streamline GIS, design...Schneider Electric
Applications:
Integration of GIS-based processes makes existing circuits and proposed circuits
available in the same system so operations staff can work in parallel with the designers
rather than in succession.
Customer benefits
• Model, design and manage critical infrastructure
• Highly configurable
• Easily adapted for multiple uses
• Proactively identify needed repairs and replacements well in advance
Overview 5G NR Radio Protocols by Intel Eiko Seidel
Very nice overview of the 5G Radio Interface protocol as defined by 3GPP in NR Rel.15. The document was submitted to the 3GPP workshop on ITU submission in Brussels on Oct 24, 2018.
In this paper, we propose and investigate a schottky tunneling source impact ionization MOSFET (STSIMOS)
with enhanced device performance. STS-IMOS has silicide (NiSi) source to lower the breakdown
voltage of conventional impact ionization MOS (IMOS). There is cumulative effect of both impact
ionization and source induced tunneling for the current gating mechanism of the device. The silicide source
offers immensely low parasitic resistance subsequently there is an increment in voltage drop across
intrinsic region. This leads to appreciable lowering of breakdown and threshold voltage for STS-IMOS.
Hence, it demonstrates enhanced device performance over conventional IMOS. Besides this for STS-IMOS
the location of maximum electric field has shifted towards the source and now it is quite away from gateoxide. Hence, it shows high immunity against Vth fluctuations due to hot electron damage. Consequently, itis found that device reliability is also improved significantly.
Static power optimization using dual sub threshold supply voltages in digital...VLSICS Design
Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
IMPLEMENTATION OF SDC - SDF ARCHITECTURE FOR RADIX-4 FFT VLSICS Design
Very large scale integration and Digital signal processing are the very crucial technologies from the last
few decades. DSP applications require high performance, low area and low power VLSI circuits. This
paper is discussing about FFT which is one of the vital component in the digital signal processing. In this
Paper, we propose a single path delay commutator–feedback (SDC-SDF) Architecture for Radix-4 FFT
and presented its simulation and synthesis results. The Radix-4 FFT architecture consists of log4 N-1 SDC
Stages and 1 SDF stage. Previously, the radix-2 SDC-SDF (Single path delay commutator-feedback) FFT
architecture was includes log2 N-1 SDC Stages and 1 SDF stage. The proposed Radix-4 SDC-SDF
architecture reduces the number of multiplications and additions as well as number of stages which
achieves reduced area and low power. The resultant architecture is simulated using Modelsim, design
verification and synthesis results are done using Xilinx ISE. The proposed architecture is compared with
Radix-2 SDC-SDF FFT and it can achieve less area as well as low power
DESIGN AND IMPLEMENTATION OF 10 BIT, 2MS/s SPLIT SAR ADC USING 0.18um CMOS TE...VLSICS Design
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is
designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample
and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC
using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using
Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
A new efficient fpga design of residue to-binary converterVLSICS Design
In this paper, we introduce a new 6n bit Dynamic Range Moduli set { 22n, 22n + 1, 22n – 1} and then present
its associated novel reverse converters. First, we simplify the Chinese Remainder Theorem in order to
obtain an efficient reverse converter which is completely memory less and adder based. Next, we present a
low complexity implementation that does not require the explicit use of modulo operation in the conversion
process and we demonstrate that theoretically speaking it outperforms state of the art equivalent reverse
converters. We also implemented the proposed converter and the best equivalent state of the art reverse
converters on Xilinx Spartan 6 FPGA. The experimental results confirmed the theoretical evaluation. The
FPGA synthesis results indicate that, on the average, our proposal is about 52.35% and 43.94% better in
terms of conversion time and hardware resources respectively.
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
This paper presents a novel Handover mechanism to minimize target Femto Access Points (FAPs) list
during macro-to-femto and femto-to-femto handover in LTE based Macro-Femto Heterogeneous Networks.
HandOver is the procedure that transfers an ongoing call from one cell to another as the users move
through the coverage area of cellular system. The femtocell has a limited coverage area (15 meters to 30
meters), and subsequently, HandOver is decided based on mobile User Equipment (UE) speed for handover
between macrocell-to-femtocell and femtocell-to-femtocell. In the existing networks, for handover
procedure, serving Base Station will decide the cell selection based on mostly the signal strength of the
neighbouring femtocells. This information is provided by the Measurement Reports sent by the
corresponding UE. In this paper, we present a novel handover management scheme which considers both
the Received Signal Strength and Cell Load of the target Femtocells for making the Handover decision.
This proposed scheme for macro-femto heterogeneous network reduces the number of target FAPs to avoid
handover to overloaded femtocells and also reduce the number of handovers.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
DUALISTIC THRESHOLD BASED MIN-MAX METHOD FOR VOICE SIGNAL ENHANCEMENTVLSICS Design
In this article, unwanted transitory assessment is specified by averaging previous phantom power
standards and through a levelling stricture that is in step by the symbol existence likelihood in sub-bands.
A two threshold based min-max method is proposed that we compare with the recursive averaging (RA)
approach for unwanted transient assessment with SAL (spectral amplitude with logarithm assessment) in
voice signal enrichment .The SAL procedure includes a transient assessment and the unwanted transient
PSDs in virtual stationary form, and enrichment of voice signal. It is proficient of tracing the incoming
signal rapid variations in spectra and supports to assessment of PSD for transients effectively. The
unwanted transient assessment is much efficient by proposed method as compared to SAL method and RA
in terms of the voice signal power to noise ratio (SNR). And finally by simulation modelling we show the
results.
A new design for fault tolerant and fault recoverable ALU System has been proposed in this paper. Reliability is one of the most critical factors that have to be considered during the designing phase of any IC. In critical applications like Medical equipment & Military applications this reliability factor plays a
very critical role in determining the acceptance of product. Insertion of special modules in the main design for reliability enhancement will give considerable amount of area & power penalty. So, a novel approach to this problem is to find ways for reusing the already available components in digital system in efficient way to implement recoverable methodologies. Triple Modular Redundancy (TMR) has traditionally used
for protecting digital logic from the SEUs (single event upset) by triplicating the critical components of the system to give fault tolerance to system. ScTMR- Scan chain-based error recovery TMR technique provides recovery for all internal faults. ScTMR uses a roll-forward approach and employs the scan chain implemented in the circuits for testability purposes to recover the system to fault-free state. The proposed
design will incorporate a ScTMR controller over TMR system of ALU and will make the system fault tolerant and fault recoverable. Hence, proposed design will be more efficient & reliable to use in critical applications, than any other design present till today.
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
In this paper, a novel architecture of RNS based 1D Lifting Integer Wavelet Transform (IWT) has been introduced. Advantage of Residue Number System (RNS) based Lifting Scheme over RNS based Filter Bank and non-binary IWT has been discussed. The performance of traditional predicts and updates stage of binary Lifting Scheme (LS) for Discrete Wavelet Transform (DWT) generates huge carry propagation
delay, power and complexity. As a result non binary number system is becoming popular in the field of Digital Signal Processing (DSP) due to its efficient performance. In this paper also a new fixed number ROM based RNS division circuit has been proposed. The proposed architecture has been validated on Xilinx Vertex5 FPGA platform and the corresponding result and reports are shown in here.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER ...VLSICS Design
The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a
rapidly growing research area driven by a wide range of emerging energy constrained applications such
as wireless sensor network, portable medical devices and brain implants. The asynchronous design
techniques allow the construction of systems which are samples driven, which means they only dissipate
dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous
design over conventional synchronous circuits allows them to be energy efficient. However the
implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandard
synchronous design tools and modelling languages. This paper devises a novel asynchronous
design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is
synthesizable and suitable for implementation using conventional synchronous systems design flow and
tools. The proposed design is based on a modified version of the micropipline architecture and it is
constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been
developed on an FPGA, and systematically verified. The results prove correct functionality of the novel
design and a superior performance compared to a synchronous FIR implementation. The findings of this
work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and
performance benefits.
LOW POWER, LOW NOISE AMPLIFIERS DESIGN AND ANALYSIS FOR RF RECEIVER FRONT END...VLSICS Design
This work is mainly to ensure the reliability of low power low noise amplifier design and analysis which is
useful for 4G receiver front ends in particularly WIMAX applications. The low noise amplifiers
implemented by using different topologies namely (a) Cascoded Common source amplifier technique(b)
Folded Cascode amplifier technique (c) Shunt feedback amplifier technique (d) Current reuse Common
gate amplifier with gm boosted technique with 90 nm TSMC CMOS technology, which is used for WIMAX
applications with 1V supply. In order to simulate and measurement the parameters such as Scattering
parameters(S21, S12 S11. S22 ),noise-figure, input matching, output matching ,stability, linearity the
Cadence ,Agilent technologies ADS and lab view graphical software have been used and Compare the
performance of the various parameters .
Transistor level implementation of digital reversible circuitsVLSICS Design
Now a days each and every electronic gadget is designing smartly and provides number of applications, so
these designs dissipate high amount of power. Reversible logic is becoming one of the best emerging design
technologies having its applications in low power CMOS, Quantum computing and Nanotechnology.
Reversible logic plays an important role in the design of energy efficient circuits. Adders and subtractors
are the essential blocks of the computing systems. In this paper, reversible gates and circuits are designed
and implemented in CMOS and pass transistor logic using Mentor graphics backend tools. A four-bit ripple
carry adder/subtractor and an eight-bit reversible Carry Skip Adder are implemented and compared with
the conventional circuits.
EVALUATION OF ATM FUNCTIONING USING VHDL AND FPGA VLSICS Design
It has been almost four decades that banks and other financial organizations have been gradually computerised, in order to improve service and efficiency and to reduce cost. The birth of Electronic Fund Transfer and Automated Teller Machines has given rise to 24-hour banking and a greater variety of services for the customer. This method uses a computer to transfer debits and credits, with the help of electronic pulses, which are carried through wires either to a magnetic disk or tape. ATM (Automated
Teller Machine) has become an important part in our daily lives. People use ATM for various purposes such as money withdrawal, checking balance, changing password etc. Since it mainly deals with people's
money, it has to be a secure system on which we can rely. We have taken a step towards increasing this
security and integrity by trying to implement the functioning of an ATM using VLSI-based programming, HDL(Hardware Description Language).The conventional coding languages such as C,C++ are replaced by VHDL(Very High Speed Integrated Circuit Hardware Description Language) so that the code cannot be easily hacked or changed. This article consists of an insight into the various functions that can be
performed using an ATM, a brief description of the Coding and the obtained simulation results. It alsoconsists of the implementation of the code using FPGA Kit (Spartan3; Model no.-XC 3S50).
Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
Design And Simulation of Modulation Schemes used for FPGA Based Software Defi...Sucharita Saha
Design of a BPSK and QPSK digital Modulation scheme and its implementation on FPGAs for universal mobile telecommunications system and SDR applications. The simulation of the system is made in MATLAB Simulink environment and System Generator, a tool used for FPGA design. Hardware Co-Simulation is designed using VHDL a hardware description language targeting a Xilinx FPGA and is verified using MATLAB Simulink. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Xilinx 14.2 ISE Edition software, and downloaded to Spartan 3E (XC3S500E) board.
Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.
FPGA, VLSI design flow using HDL, introduction to behavior, logic and physica...Rup Chowdhury
Field-Programmable Gate Arrays (FPGAs) and Very Large Scale Integration (VLSI) design play pivotal roles in the development of modern electronic systems, offering a flexible and efficient platform for implementing complex digital circuits. This description delves into the world of FPGA and VLSI design flow using Hardware Description Languages (HDL) and introduces the crucial concepts of behavior, logic, and physical synthesis.
FPGA Overview:
FPGAs are reconfigurable semiconductor devices that allow designers to implement custom digital circuits, making them ideal for prototyping, rapid development, and applications requiring flexibility. They consist of an array of programmable logic blocks, configurable interconnects, and memory elements, providing a versatile hardware platform.
VLSI Design Flow using HDL:
The VLSI design flow is a systematic process employed by engineers to design, implement, and verify integrated circuits. Hardware description languages, such as Verilog and VHDL, are essential components of this flow. These languages enable designers to express the functionality and structure of digital circuits in a human-readable and simulation-friendly manner.
AN DYNAMIC ENERGY MANAGEMENT ON FPGA FOR WIRELESS SENSOR NETWORKcsijjournal
Wireless sensor networks are occupying large space in the modern world. Technologies like FPGA appear with features to be explored as implementation of low-power system. In this project we built a low-power circuit applying the implementation of a technique to minimize the clocks number of the circuit and focusing on the dynamic power consumption of the architecture was evaluated energy and logical consumption module to module. The architecture built has all the necessary features to integrate, synchronize and perform communication according to the application. Different analyses the consumption of a general architecture is shown and an operation mode acceptable to dynamic energy consumption of circuit to wireless sensor network on FPGA is achieved.
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM
based digital down convertor for Software Defined Radios. The proposed DDC is implemented using
optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase
decomposition structure is used to improve the hardware complexity of the overall design. The proposed
model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the
system performance in terms of speed and area. The DDC model is designed and simulated with Simulink
and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II
Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum
frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed
design is consuming very less resources available on target device to provide cost effective solution for
SDR based wireless applications.
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
Implementation of Algorithms For Multi-Channel Digital Monitoring ReceiverIOSR Journals
Abstract: Monitoring Receivers form an important constituent of the Electronic support. In Monitoring
Receiver we can monitor, demodulate or scan the multiple channels.
In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The
implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital
Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to
Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs.
Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to
the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the
implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf)
development board. Xilinx System Generator will be used for the implementation of the algorithms.
Keywords: DDC, ADC, Digital Base band demodulation, IF, Monitoring Receiver.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.4, August 2015
DOI : 10.5121/vlsic.2015.6404 35
ARCHITECTURE OF A NOVEL CONFIGURABLE
COMMUNICATION PROCESSOR FOR SDR
Amiya Karmakar1
, Amitabha Sinha2
, Pratik Kumar Sinha3
& Pijush Biswas4
1
Department of Computer Science & Engineering, West Bengal University of
Technology, Salt Lake City, Kolkata, West Bengal, India
2
B.C.Roy Engineering College, Durgapur, West Bengal, India
3
Department of Computer Science & Engineering, N.I.T., Durgapur, West Bengal, India
4
Department of Computer Science & Engineering, N.S.H.M., Kolkata,
West Bengal, India
ABSTRACT
The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio
(SDR) with high degree of flexibility and low power consumption has been a major challenge to the
scientific community ever since its conception. The basic philosophy of SDR is to implement different
modulation or demodulation schemes on the same underlying hardware. Currently available high
performance DSP processors, optimized with ‘Very Large Instruction Word (VLIW)’ architecture and
multiply and accumulate (MAC) units, are unable to meet the near real time speed requirements of
Software Defined Radios (SDR) due to their inherent sequential execution of compute intensive signal
processing algorithms. Moreover, their power dissipation is considerably high. Even though, Application
Specific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of their
lack of flexibility. Various references on FPGA based implementations of reconfigurable architectures for
SDRs are also available. However, the Look-up Table (LUT) based implementations of FPGAs are not
optimum and therefore, cannot offer highest performance at low silicon cost. Keeping this view, this paper
presents the design of a configurable communication processor for Software Defined Radio. The proposed
scheme features the performance of an ASIC based design combined with the flexibility of software.
Experimental results reveal that the proposed architecture has minimum hardware requirement, improved
silicon area utilization and low power dissipation.
KEYWORDS
Field Programming Gate Array (FPGA), Software Defined Radio (SDR), Digital Signal Processing (DSP)
Processor, Hardware Description language (HDL), Signal Flow Graph (SFG), Application Specific
Integrated Circuit (ASIC), Union of graph, Reconfigurable DSP Processor
1. INTRODUCTION
The communication industry has witnessed substantial changes in digital communication
standards. The journey of digital communication commenced with GSM, D-AMPS and PDC
systems and gradually, a large portion of digital communication solutions were replaced by
WCDMA, HSPA and CDMA 2x standards. Though these 3G standards offer much higher data
rate and reliability, customers have now begun leaning towards the services offered by 4G
standards with data rates reaching 100 Mbits/s, if not more. To cope up with this ever changing
scenario of communication schemes, it is felt that the current developments in communication
systems and protocols should not only be of low cost and high efficiency, but also adaptive and
reusable. In conventional radio communications, the hardware components used for modulations/
demodulations are fixed for a particular communication scheme. For large varieties of
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.4, August 2015
36
applications, particularly for military and cell phone services, radio protocols need to be changed
in real time with very high speed. This necessitates the design of a high performance radio system
with high degree of flexibility. The “Software Defined Radio(SDR)” [1][2][3][4][5] offers
flexible, high performance radio systems where hardware components of modulators/
demodulators are implemented by means of software on different hardware platforms like DSP
processors or FPGAs.
Software Defined Radio (SDR) systems [6][7][8][9] are flexible communication systems where
components of classical radio systems are replaced by software modules. Implementing different
modules (modulators, demodulators, filters etc.) in software has the distinct advantage that SDR
systems can be modified on the fly to deploy different communication schemes [10][11] without
changing the hardware. Though the concept of SDR has been in existence for more than a decade,
introduction of latest Digital Signal processing Processors [12][13] and FPGAs have made newer
types of design of SDR possible. The block diagram of a SDR system is presented in Fig.1.
Figure 1. Block Diagram of SDR
Evaluation history and literature survey of SDR reveals that there are various types SDR systems,
projects and platforms. Joe Mitola[14] proposed software radio which was a software-based
transceiver. He used GSM base station- combination of Ferdensi's digital receiver and E-Systems
Melpar's. E-Systems Melpar sold the software radio idea to the US Air Force and Melpar built a
prototype commanders' tactical terminal in 1990-91 that employed Texas Instruments
TMS320C30 Processors. SPEAKEASY [15] is an open architecture and proves the concept of
multi-band, multi-mode software programmable radio operating from 2 MHz to 2 GHz. Tactical
radio systems as well as voice and data communications to aircraft and onto battlefield has been
used as Military applications and civilian applications. Academic projects, the CHARIOT and
SpectrumWare, were funded by DARPA. GNU Radios as well as some European projects has
also attracted a large number of SDR developers.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.4, August 2015
37
Flexible radio systems are generally implemented on programmable platforms like Digital Signal
processing Processors and FPGAs. In the case of DSP based implementation [16][17], programs
for the proposed architecture are executed on the DSP processor. Flexibility can be achieved as
the programs are easily modifiable. The major problem is that the power consumption in this case
is considerably high. Moreover the efficiency of the design will also be limited by the efficiency
of the instruction set of that particular digital signal processor. On the other hand FPGA
[18][19][20][21][22][23][24] is configured for a particular design by downloading the
corresponding bit streams onto FPGA. These bit streams are generated after synthesis of the
description of the circuit in some Hardware Description Language (HDL)[25][26] like VHDL,
Verilog etc. Changes in these HDL programs will thus be reflected in the final configuration of
the FPGA, thereby offering flexibility. However the drawback of FPGA based design lie within
the issues of un-optimized Look Up Table (LUT) based implementation, large silicon area usage,
high power dissipation, communication delay and considerable configuration latency. On the
contrary, Application Specific Integrated Circuits (ASICs) [27] provide lower power dissipation,
minimum latency time and higher silicon area utilization factor. The major issue with this type of
VLSI [28] based design is lack of flexibility in the architecture.
Considerable effort has been given by designers and researchers to implement software define
radio (SDR) system in various platforms, including recent works related to FPGA based
implementation[20][21][23][29] of SDR. These designs, though aim to leverage flexibility of
FPGAs, are not also free from the drawbacks discussed above. Jignesh Oza et.al;[29] in their
work have combine different modulation schemes into a single circuit and have implemented on
FPGA but no efforts were made to minimize the hardware requirement. Only selection lines were
used for choosing available schemes at a particular instant of time. On the other hand Tadayuki
Kamisaka, et. al; [30] proposed modulators where different modulation schemes can be chosen by
simply changing the ROM contents. Although it is useful for various data transmission speeds but
the operating speed was bottlenecked due to use of non-optimized LUT-based ROMs. FPGA
based design of composite of modulation schemes either by selection line or by union method
[23](graph theory method) is free from the inherent drawback like high latency time, un-
optimized LUT (i.e. poor silicon utilization factor) and high power consumption. On the other
hand ASIC based design is highly optimized, low power and high speed without or little
flexibility. Hence in this paper, ASIC design of composite modulators and their various level of
hardware optimization using graph theory methods (nomenclature, labelling, precedence
relationship and union of graph) have been presented in details. This design was also converted
into Verilog codes (HDL) and was synthesized by ASIC synthesis tool Synopsis tool sets-Design
Vision/design Compiler.
Keeping these issues in view, this paper aims to present a new reconfigurable architecture for an
ASIC based SDR architecture which offers high performance at the same time adding flexibility
features to overcome the drawback of legacy ASIC based systems.
2. PROPOSED ARCHITECTURE OF RECONFIGURABLE MODULATORS
2.1. Architecture of Reconfigurable Modulators
In the proposed architecture, for case study, a number of different modulation schemes [10] [11]
[31] [32] like amplitude shift keying(ASK), frequency shift keying (FSK), binary phase shift
keying (BPSK), Quadrature phase shift keying (QPSK) have been considered and the architecture
can be configured to work according to any one of the schemes at a given time. The main
intention is to perform all these above mentioned modulation operations using the same
underlying hardware platform while the software above the hardware layer controls the
configuration. The different modulation/demodulation schemes can be visualized as
interconnected building blocks where such building blocks are Adder, Multiplier, Comparator,
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.4, August 2015
38
Multiplexor etc. These building blocks primitives have to be chosen in such a fashion that they
are basic enough so that a particular modulation scheme can be made by connecting these
primitives in appropriate order. Obviously a number of switches are required to maintain the
interconnections among the primitives for implementing a scheme. So, the architecture consists
of:
1. A number of primitive building blocks for performing the signal processing functions for
different modulation schemes. These blocks include Adder, Multiplier, Comparator,
Multiplexor etc.
2. A number of switches for implementing different routing functions, so that by interconnecting
different building blocks different modulation schemes can be implemented. These switches
can be implemented using Multiplexers.
3. A control unit or Logical unit is required to generate the control signals for configuring these
switches. This unit consists of a number of hardware switches and a Decoder. For a particular
modulation scheme to be implemented one particular hardware switch is to be on which sends
some particular bit fashion to the input of the decoder. The decoder in turn generates the
corresponding configuration bit stream for the routing switches to configure that particular
modulation scheme.
The main advantage of such architecture is that it can be configured to any one of the large
number of modulation schemes by generating different control signals to the Multiplexers /
switches resulting the speed of the hardware with the flexibility of the software.
The efficiency of such a scheme depends on the trade-off among three important factors. They
are: 1) minimum number of basic building blocks required for configuring to a desired
modulation scheme, 2) minimum number of switches required establishing a given modulation
scheme, 3) Minimum Routing delay.
Keeping these factors in focus, a graph theoretic approach for hardware optimization has been
considered in this paper.
2.2. Graph theoretic approach for minimization of hardware in composite
architecture
At first four the modulation schemes were visualized as a connection of primitive building blocks.
The same blocks existing in different modulations schemes are then identified and marked with
identical names. With these primitive blocks different Signal Flow Graphs (SFG) are drawn for
different modulation schemes. By combining the SFGs common blocks are eliminated and hence
there will be sufficient hardware reduction in composite circuit. Such practices are discussed in
the following subsection.
2.2.1 Nomenclature of primitive building blocks
Same functionality primitive building blocks have given same nomenclatures are as follows:
Random Number Generator (S1), comparator (B1), Multiplier (B2), Constant1 (B3), Cosine
Generator (S2), Constant2 (B4), Switch1 (B5), Gain(-1) (B6), Switch2 (B7), Adder (B8), Sine
wave generator (S3), Switch3 (B9). Using these primitive blocks as nodes and connecting them
accordingly, Signal Flow Graph (SFG)s of four modulation schemes have been drawn.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.4, August 2015
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2.2.2 Signal Flow Graph
The Signal Flow Graphs (SFG) of four modulation schemes and their labelling are shown in the
following subsection.
2.2.2.a Labelling of SFGs
The labelling procedure has been so adapted that the nodes performing the same function has
been labelled by the same symbol in all the signal flow graphs. Further, the same nomenclatures
across the all SFGs are also used for the directed branches joining the same pair of nodes. This
avoids duplication of nodes and branches. The labels are listed in Table 1.
Table 1. Labels of directed branches in SFGs
Source Node Destination Node Label of the directed branch
S1 B1 e1
S1 B8 e2
S2 B2 e3
S2 B5 e4
S2 B6 e5
S2 B7 e6
S2 B9 e7
S3 B6 e8
S3 B7 e9
S3 B9 e10
B1 B2 e11
B1 B5 e12
B1 B9 e13
B3 B1 e14
B4 B8 e15
B6 B5 e16
B6 B7 e17
B8 B7 e18
2.2.2.b SFG representation of four individual modulation schemes
SFG of four individual modulation Schemes following the convention discussed above are shown
in Fig. 2, Fig. 3, Fig. 4 and Fig. 5.
Figure 2. Graph-I (SFG of ASK modulation) Figure 3. Graph-II (SFG of BPSK modulation)
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.4, August 2015
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Figure 4. Graph-III (SFG of QPSK modulation) Figure 5. Graph-IV (SFG of FSK modulation)
2.2.3 Construction of a Combined Architecture from the SFGs
In the previous section, the four SFGs for four modulation schemes have been presented. Now
using these SFGs and applying the graph theoretic operations [33] like “precedence relationship”
and “union of graph” to these SFGs, a new SFG can be developed for proposed architecture.
Union of graph property is used to eliminate the common portion of the different graphs.
However a combined signal flow graph resulting merely from union of graph would produce
erroneous results unless the order of data processing i.e. signal dependency in individual SFGs
remains preserved in the combined SFG.
2.2.3.a Precedence Relationship
In constructing network diagrams which represents any project comprising of several activities,
preserving precedence relationship is important so that the order of activities be properly
represented. In this work two standard operation research methods i.e. PERT and CPM methods
are used. Assuming that the time required by the signal to flow across all the branches are same
the weight of all branches are considered as 1. Now the precedence relationship for the four
modulation schemes is as follows:
For ASK (Graph-I): e1<e11, e14<e11 i.e. e1, e14<e11;
For BPSK (Graph-II): e1, e14<e12, e5<e16;
For QPSK (Graph-III): e2, e15<e18, e5, e8<e17;
For FSK (Graph-IV): e1, e14< e13;
2.2.3.b Union of Graphs
In graph theory, the union of two graph is defined as follows: IF G1 is a graph with vertex set v1
& edge set E1 and G2 be another graph with vertex set V2 & edge set E2 then their union denoted
by G1 U G2 is a graph with vertex set is V1 U V2 & edge set is E1U E2. Since the union
operation excludes duplicate entry of set elements, the union of two signal flow graphs union will
provide the minimum possible number of vertex and edges without affecting the desired
functionality of the combined network or combined system provided the precedence of operations
are not disrupted. Fig.6 and Fig.7 depicts the two individual directed graphs G1 and G2. Fig. 8
represents the union of two graphs G1 and G2. Now the pair of nodes (V1, V2) and their
connecting branch (e1) is same in both G1 and G2. But the resultant graph from the union
operation of G1 and G2 will have no duplication of nodes or branches.
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Figure 6. Directed Graph G1 Figure 7. Directed Graph G2
Figure 8. Result of Union Operation G1U G2
In first step of union operation to construct the combined architecture, Graph-I and Graph-II are
combined using the Union and preserving the precedence relationship. The nodes S1, B1, S2 and
B3 are the common nodes in the both graph. These common nodes are combined strictly adhering
to the precedence relationship. The principle being the same pair of nodes and their connecting
branches having same directed path are merged. The node pair (S1, B1) and connecting branch e1
being present in both the graphs (Graph-I and Graph-II). The same thing is applicable for the
node pair (B3, B1) and connecting branch e14. The resultant graph from the union of graph
operation is shown in Fig.9.
Figure 9. Graph Showing Graph-I U Graph-II
In this work the union of graph operation has been applied in the following fashion to obtain the
combined SFG:
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Step 1: (Graph-I) U (Graph-II)
Step 2: (Graph-I) U (Graph-II) U (Graph-III)
Step 3: (Graph-I) U (Graph-II) U (Graph-III) U (Graph-IV)
During the operation the following points were observed. In the above case (B1, B1, B1), (B6,
B6, B6) are the repeated internal nodes. B1 follows the same pair of branches e1, e14 in all the
three graphs I, II & IV. Hence the sum of the incoming signals is same in the all three graphs. The
outgoing signals, although different, do not affect the output of the combined system. Hence node
B1 will appear once. The repeated node B6 is represented in the Fig.10. The precedence
relationship of this repeated node are e16>e5, e17>e5, e17>e8 i.e. e16>e5, e17>e5, e8. Hence the
combined digraph will need a “Dummy branch” shown in dotted lines depicted in Fig. 12. The
final combined SFG is shown in Fig. 13 which is the union of all four graphs.
Figure 10. Same node B6 but with different input-output branches
Figure 11. Graph for Precedence Relationship e16 > e5, e17> e5,e8
Figure 12. Graph for dummy branch (Shown in dotted line)
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Figure 13. The Composite Graph
3. ASIC IMPLEMENTATION OF COMPOSITE MODULATORS
3.1. Synthesis results for ASIC implementation of individual modulation schemes
The Synthesis report of VERILOG codes of four individual modulation schemes and combined
modulation scheme using Design Vision / Design Compiler [34]–a Synopsys tool has been
presented and also graphically represented in Fig. 14, Fig. 15 Fig. 16, Fig. 17 and Fig. 18.
Library(s) Used for both Area and Power calculation:
vtvt_tsmc180(File:home/ue/my_cadence_directory/vtvt_tsmc180_release/Synopsys_Libraries/lib
s/vtvt_tsmc180.db)
Power calculation parameters:
Operating Conditions: nom_pvt
Wire Load Model Mode: top
Global Operating Voltage = 1.8
Power-specific unit information:
Voltage Units = 1V , Capacitance Units = 1.000000ff
Time Units = 1ps , Dynamic Power Units = 1mW (derived from V, C, T units), Leakage Power
Units = 1mW
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HDL Synthesis Reports of all four Individual Modulation Schemes:
Area Report:
ASK:
Number of ports: 40
Number of nets: 77
Number of cells: 45
Total cell area: 1965.675575
FSK:
Number of ports: 40
Number of nets: 47
Number of cells: 15
Total cell area: 946.096199
QPSK:
Number of ports: 40
Number of nets: 131
Number of cells: 99
Total cell area: 4465.853958
BPSK:
Number of ports: 40
Number of nets: 91
Number of cells: 59
Total cell area: 2758.317297
Power Report:
ASK:
Cell Internal Power = 84.2933 mW (64%)
Net Switching Power = 47.8766 mW (36%)
Total Dynamic Power = 132.1700 mW (100%)
Cell Leakage Power = 986.6118 pW
FSK:
Cell Internal Power = 71.1495 mW (80%)
Net Switching Power = 18.1995 mW (20%)
Total Dynamic Power = 89.3489 mW (100%)
Cell Leakage Power = 591.1196 pW
QPSK:
Cell Internal Power = 121.3645 mW (73%)
Net Switching Power = 44.8811 mW (27%)
Total Dynamic Power = 166.2456 mW (100%)
Cell Leakage Power = 2.4679 nW
BPSK:
Cell Internal Power = 132.3196 mW (67%)
Net Switching Power = 66.1420 mW (33%)
Total Dynamic Power = 198.4616 mW (100%)
Cell Leakage Power = 1.5080 nW
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HDL Synthesis Reports of the Proposed Configurable Combined Architecture:
Area:
Number of ports: 56
Number of nets: 181
Number of cells: 133
Number of buf/inv: 17
Total cell area: 5845.632261
Power:
Cell Internal Power = 168.4776 mW (66%)
Net Switching Power = 88.5400 mW (34%)
Total Dynamic Power = 257.0177 mW (100%)
Cell Leakage Power = 3.0346 nW
3.2. Analysis of the Synthesis Report
References are available in literature featuring different modulation/demodulation schemes in a
single architecture. However in the reported works combined circuits where implemented mainly
aggregating the individual circuits and the selection lines to choose a particular modulation
/demodulation scheme at any particular instance. On the contrary here in this work, the ASIC
based design, the hardware requirements of the combined circuits have been minimized using
union of graphs and ASIC synthesis tool –Synopsis tool like Design Vision/ Design Compiler.
Although FPGA implementation of different modulation schemes using union of graph shown in
literature but due to inherent drawback of FPGA like configuration latency, un-optimized LUT
and high power consumption this paper suggest ASIC implementation of four composited
modulation scheme with optimal union of graph. Various Graphs have been plotted form the
ASIC synthesis results. From the graphical analysis of the cell area usage experimental data
shown in Fig. 14, it can be clearly derived that the total cell area required to implement the
combined architecture is significantly less than the sum total of the all individual implementation.
The power analysis shown in Fig. 15 also reveals that the combined scheme requires substantially
less power compared to the total power requirement to implement the modulation schemes
individually. The port, net and cell analysis, switching and dynamic power analysis as well as cell
leakage power analysis depicted in Fig. 16, Fig. 17 and Fig. 18 also show that the implementation
of the modulation schemes in the combined architecture is better than implementing the
modulation schemes individually.
Figure 14. Area Analysis of individual and combined schemes
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Figure 15. Cell Internal Power of individual and Combined Schemes
Figure 16. Number of Ports, Nets and Cells Versus individual and Combined Schemes
Figure 17. Switching and dynamic power analysis of individual and Combined Schemes
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Figure 18. Cell Leakage Power Analysis of Individual and Combined Schemes
4. CONCLUSIONS
In this paper feasibility of ASIC implementation of a novel architecture of Reconfigurable DSP
Processor for Different Modulation Schemes with optimum hardware requirements has been
explored. The synthesis reports derived from the Synopsis tool have also been presented. It can be
concluded from the synthesis results that the ASIC implementation has substantially reduced area
and power requirements. The architecture is flexible because run time configuration for any
particular modulation scheme can be achieved by activating few switches only. Thus the
proposed architecture provides high performance of while retaining flexibility reduced power
requirements and improved silicon utilization factor.
To achieve enhanced performance, unions of the set of building blocks for different modulation /
demodulation schemes have been combined. Since the performance of most of the building
blocks depend on the speed of adders ,multipliers , exploring the possibilities of implementing
these arithmetic units using non-binary systems can be thought of . The choice of number system
can influence the execution speed of the arithmetic computation to a great extent. Recent studies
in computer arithmetic have unleashed that use of number systems like Double Base number
System[35], Ternary Number System[36], Logarithmic Number system [37], Single Digit Triple
Base Number System[38] etc. can improve the performance of digital signal processing to a great
extent. Thus, the performance of the proposed configurable communication Processor for SDR
may further be improved by leveraging the advantages of the non-conventional number systems.
This study is a potential future research issue related to the current work.
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AUTHORS
Amiya Karmakar was born in Kolkata, India and obtained his Master of Engineering
(M. E.) in Computer Sc. & Engineering with specialization in Embedded Systems
from West Bengal University of Technology in 2005.Mr. Karmakar has been engaged
in teaching and research for the last nearly twelve years. He has been working with
West Bengal University of Technology as Project Officer for last nine years. Prior to
this he was faculty in a Polytechnic College for two years. His areas of research
include Embedded System Design, Re-configurable Architecture using FPGAs,
Software Defined Radio, VLSI design, Digital Signal Processing etc..
Prof.Amitabha Sinha was born in Kolkata and obtained Ph.D degree in Computer
Sc.& Engg. from Indian institute of Technology ( IIT), Delhi in 1984. He has been
working with Neotia Institute of Technology, an Institution affiliated to West Bengal
University of Technology as a Principal. Prior to this assignment, he was with West
Bengal University of Technology, Kolkata, India as a Professor and Director, school of
Engg. & Technology since August 2005/2006. He has more than 25 years of
experience in industry, premier academic institutes, R&D centers and IT/Telecom
organizations in India & abroad and his areas of research include Embedded System
Design, VLSI design, Digital Signal Processing, Re-configurable Architecture using FPGAs, Software
Defined Radio, Processor Architecture and System On-chip Design, Advanced Computer Architecture
etc..He was Assistant Professor of the Dept.of Comp.Sc.& Engg., Bengal Engineerig College ( Now Bengal
Engineering & Science University), West Bengal, India during 1985-1991 and Associate Professor of the
Dept.of Comp.Sc.&Engg, BITS Pilani, during 1997-1998. He was visiting faculty, Dept.of Computer
Sc.&Engg.,Oakland University, U.S.A. during 1994 and 1999. He was an expatriate faculty member of a
premier Malaysian University Mara Institute of Technology during 1994-1995. Prof. Sinha also served R
&D centres of different premier industries in the country at senior levels.
Mr. Pijush Biswas is a PhD student in Institute of Radiophysics and Electronics,
University of Calcutta, India. He has received his B.Tech and M.Tech in Information
Technology from University of Calcutta. His research interest includes Reconfigurable
Computing, VLSI Design and Computer Architecture. He is a student member of
ACM. He is a professional Fashion Photographer and enjoys Bird watching and
Nature conservation activities.