IS 139 Lecture 2
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This document describes the different levels of the computer hierarchy. It begins with the user level (Level 6) and high-level language level (Level 5) where users interact. It then describes lower levels including the assembly language level (Level 4), system software level (Level 3), machine level (Level 2), control level (Level 1), and digital logic level (Level 0) where circuits are implemented. The document also explains the von Neumann model of stored-program computers and how they fetch, decode, and execute instructions in sequential order. Improvements to von Neumann models include adding additional processors for increased computational power.
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The document discusses basic logic operations and logic gates. It explains that logic operations like AND, OR, and XOR can be implemented using logic gates and combined to perform more complex functions. Some common logic functions mentioned are comparison, arithmetic, coding, decoding, data selection, storage, and counting. Logic gates take binary inputs and produce binary outputs based on truth tables that define the logic operations.
IS 151 Lecture 2
This document covers digital circuitry topics including number systems, digital waveforms, pulse characteristics, waveform characteristics, and timing diagrams. It defines positive and negative pulses, and describes pulse parameters like rise time, fall time, pulse width, and amplitude. Periodic and non-periodic waveforms are discussed as well as frequency, period, and duty cycle. Timing diagrams are introduced as a way to synchronize digital signals with a clock waveform where each clock interval represents one bit. Examples are provided to demonstrate calculating pulse characteristics and drawing timing diagrams.
IS 151 Lecture 1
This document provides information about a course on digital circuitry, including required materials, assessment details, and contact information for the instructor. It discusses the textbook, simulation software, and additional recommended resources. Coursework will be 40% of the grade and an exam will make up the remaining 60%. Students should contact their class representative for any questions.
IS 151 Outline 2014
This document outlines the modules, activities, and assessments for an IS 151 course on digital circuits and logic design. Over 15 weeks, topics will include digital and binary concepts, number systems, logic gates and functions, Boolean algebra, Karnaugh maps, combinational logic, sequential logic elements like latches and flip-flops, finite state machines, and programmable logic devices. Assessment will include laboratory work, assignments, tests, and a final laboratory exercise on designing a Gray code counter.
IS 139 Assignment 3
This document contains 5 questions related to binary, hexadecimal, and decimal number conversions as well as calculating memory size needed for storing a film. Question 1 asks to convert between base 10, 2, and 16. Question 2 asks for the ASCII code for a word. Question 3 asks to write decimal fractions in binary. Question 4 asks to write positive and negative numbers in 6-bit two's complement binary form. Question 5 asks to calculate the memory needed in gigabytes for a film with given frame size, bit depth, frame rate, and length.
IS 139 Lecture 7
This document provides an overview of memory organization and cache memory. It discusses the memory hierarchy from fast, small registers and caches closer to the CPU to larger, slower main memory and permanent storage like disks further away. Cache memory stores recently accessed data from main memory to speed up future accesses by taking advantage of temporal and spatial locality. Caches can be direct mapped, set associative, or fully associative and use different replacement policies like LRU when a block needs to be evicted.
IS 139 Lecture 6
This lecture provides a detailed look at instruction set architectures (ISAs). It discusses instruction formats, including the number of operands, operand locations and types. It also covers addressing modes like immediate, direct, register, indirect and indexed. Additionally, it examines different approaches to storing data like stack, accumulator and general purpose register architectures. The lecture concludes by discussing instruction-level pipelining and examples of ISAs like Intel, MIPS and Java Virtual Machine.
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This document provides instructions for an assignment in a class on the MARIE assembly language. Students must complete 4 programming problems in groups of at most 2 people by writing MARIE programs, assembling them, and testing them using a MARIE simulator. They are to submit a zip file of their assembly code for each question, which includes writing loops to multiply numbers with repeated addition, an if/else statement to multiply or subtract values of variables x and y, adding the first 10 numbers, and subtracting 2 numbers input from the keyboard.
IS 139 Lecture 5
The document provides an overview of the components and architecture of the MARIE computer system, which was designed to illustrate basic computer concepts. It describes the CPU, registers, memory, bus, instruction set, and fetch-decode-execute cycle. The MARIE CPU has 7 registers, including the accumulator, program counter, and instruction register. It uses a 16-bit instruction format. Example load and add instructions are shown in register transfer language to demonstrate how instructions are executed as a series of microoperations. Interrupts can alter the execution cycle by adding an additional "process interrupt" step.
IS 139 Lecture 4
The document discusses data representation in computer systems. It begins by explaining that computers use the binary system for logic and arithmetic because it is easy to implement in electronics and switches. It then discusses how integers, floating point numbers, and Boolean logic are represented. The document provides details on bits, bytes, words, and how positional numbering systems like binary represent values. It covers converting between decimal and binary, including fractional values. Finally, it discusses signed integer representation using methods like signed magnitude, one's complement, and two's complement.
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This document provides instructions for an assignment to design and implement a 4-bit arithmetic logic unit (ALU) that can perform addition, subtraction, AND and OR operations. Students are asked to deliver a functioning logic circuit in Deeds that takes two 4-bit input operands and an operation code as input, and produces a 4-bit output result. The circuit should correctly perform the specified operations and optionally detect overflow conditions.
IS 139 Lecture 3
This document discusses Boolean algebra and digital logic circuits. It begins by introducing Boolean algebra, which uses variables that can have two values (true/false, on/off, 1/0) and operations like AND, OR, and NOT. Boolean functions are implemented using logic gates like AND, OR, NAND and NOR gates. Combinational logic circuits like adders, decoders, and multiplexers perform Boolean functions without state, while sequential circuits like flip-flops use feedback and clocks to remember state over time. Finite state machines can model sequential circuits.
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The document provides an overview of computer architecture and organization. It discusses how computers work at a component level, different types of computer systems and their structures and behaviors. It covers key concepts like instruction sets, memory access methods, and I/O mechanisms. The document also distinguishes between architecture, which defines attributes visible to programmers, and organization, which refers to how components are interconnected. It outlines reasons for studying computer architecture and what skills can be developed. Finally, it briefly traces the evolution of computers through different generations defined by underlying technologies.
IS 151 Lecture 11
This document discusses edge-triggered flip-flops and their use in counters. It describes how edge-triggered flip-flops change state only on the triggering edge of a clock pulse. Specifically, it discusses positive-edge triggered S-R flip-flops, showing how they set and reset based on the S and R inputs at the positive clock edge. It also provides an example of a 2-bit asynchronous binary counter built using two flip-flops, where the output of the first flip-flop clocks the second flip-flop. The counter cycles through the binary states 00, 01, 10, 11 with each clock pulse before recycling.
IS 151 Lecture 10
The document discusses different types of multivibrators including monostables, astables, and bistables. It focuses on bistables, specifically latches and flip-flops. Latches have two stable states, SET and RESET, and can remain in either state indefinitely. The document describes the basic S-R latch using NOR or NAND gates and explains how the outputs change based on the input signals. It also introduces the gated S-R latch which only changes state when the enable signal is high.
IS 151 Lecture 9
This document discusses basic combinational logic functions including adders, comparators, decoders, and encoders. It begins by explaining half adders and full adders, including their truth tables and logic expressions. It then covers parallel binary adders used to add multi-bit numbers. Comparators are introduced for comparing the magnitude of two binary quantities. Decoders and encoders are also discussed, with decoders detecting a specified input code and encoders performing the reverse by converting an input to a coded output. Examples and exercises are provided to illustrate the concepts.
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IS 151 Lecture 7
The document describes the process of minimizing Boolean expressions using K-maps. It involves grouping adjacent 1s on the K-map to form product terms. Each group represents a product term in the simplified sum of products (SOP) expression. The goal is to minimize the number of product terms by forming the largest possible groups. The document provides examples of K-maps and the resulting minimized SOP expressions. It also discusses how to map truth tables directly to K-maps and handle "don't care" conditions.
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This document discusses Boolean expressions and truth tables. It introduces truth tables as a way to present the logical operation of a circuit by listing all possible input combinations and corresponding outputs. An example truth table is given for a standard sum-of-products (SOP) expression. Karnaugh maps are also introduced as another way to simplify Boolean logic, where each cell represents a variable combination and 1s are placed in cells for product terms in SOP expressions. The document provides examples of mapping logic expressions to Karnaugh maps and using cell adjacency to minimize logic.
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IS 139 Lecture 2
- 1. IS 139 Lecture 2 (Introduction – Part 2) Introduction
- 2. The Computer Level Hierarchy Computers consist of many things besides chips. Before a computer can do anything worthwhile, it must also use software. Writing complex programs requires a “divide and conquer” approach, where each program module solves a smaller problem. Complex computer systems employ a similar technique through a series of virtual machine layers. 2
- 3. The Computer Level Hierarchy Each virtual machine layer is an abstraction of the level below it. The machines at each level execute their own particular instructions, calling upon machines at lower levels to perform tasks as required. Computer circuits ultimately carry out the work. 3
- 4. The Computer Level Hierarchy Level 6: The User Level Program execution and user interface level. The level with which we are most familiar. Level 5: High-Level Language Level The level with which we interact when we write programs in languages such as C, Pascal, Lisp, and Java. 4
- 5. The Computer Level Hierarchy Level 4: Assembly Language Level Acts upon assembly language produced from Level 5, as well as instructions programmed directly at this level. Level 3: System Software Level Controls executing processes on the system. Protects system resources. Assembly language instructions often pass through Level 3 without modification. 5
- 6. The Computer Level Hierarchy Level 2: Machine Level Also known as the Instruction Set Architecture (ISA) Level. Consists of instructions that are particular to the architecture of the machine. Programs written in machine language need no compilers, interpreters, or assemblers. 6
- 7. The Computer Level Hierarchy Level 1: Control Level A control unit decodes and executes instructions and moves data through the system. Control units can be microprogrammed or hardwired. A microprogram is a program written in a low- level language that is implemented by the hardware. Hardwired control units consist of hardware that directly executes machine instructions. 7
- 8. The Computer Level Hierarchy Level 0: Digital Logic Level This level is where we find digital circuits (the chips). Digital circuits consist of gates and wires. These components implement the mathematical logic of all other levels. 8
- 9. The von Neumann Model On the ENIAC, all programming was done at the digital logic level. Programming the computer involved moving plugs and wires. A different hardware configuration was needed to solve every unique problem type. 9 Configuring the ENIAC to solve a “simple” problem required many days labor by skilled technicians.
- 10. The von Neumann Model Inventors of the ENIAC, John Mauchley and J. Presper Eckert, conceived of a computer that could store instructions in memory. The invention of this idea has since been ascribed to a mathematician, John von Neumann, who was a contemporary of Mauchley and Eckert. Stored-program computers have become known as von Neumann Architecture systems. 10
- 11. The von Neumann Model Properties of a von Neumann architecture Data & Instructions are stored in the same memory – are only distinguishable through usage Only a single memory space – accessed sequentially Memory is one dimensional Meaning of data is not stored with it 11
- 12. The von Neumann Model Today’s stored-program computers have the following characteristics: Three hardware systems: A central processing unit (CPU) A main memory system An I/O system The capacity to carry out sequential instruction processing. A single data path between the CPU and main memory. This single path is known as the von Neumann bottleneck. 12
- 13. The von Neumann Model This is a general depiction of a von Neumann system: These computers employ a fetch- decode-execute cycle to run programs as follows . . . 13
- 14. The von Neumann Model The control unit fetches the next instruction from memory using the program counter to determine where the instruction is located. 14
- 15. The von Neumann Model The instruction is decoded into a language that the ALU can understand. 15
- 16. The von Neumann Model Any data operands required to execute the instruction are fetched from memory and placed into registers within the CPU. 16
- 17. The von Neumann Model The ALU executes the instruction and places results in registers or memory. 17
- 18. von Neumann Models - Improvements Conventional stored-program computers have undergone many incremental improvements over the years. These improvements include adding specialized buses, floating-point units, and cache memories, to name only a few. But enormous improvements in computational power require departure from the classic von Neumann architecture. Adding processors is one approach. 18
- 19. von Neumann Models - Improvements In the late 1960s, high-performance computer systems were equipped with dual processors to increase computational throughput. In the 1970s supercomputer systems were introduced with 32 processors. Supercomputers with 1,000 processors were built in the 1980s. In 1999, IBM announced its Blue Gene system containing over 1 million processors. 19
- 20. Non-von Neumann Models Typed storage (self-identifying data) Each operand (data item) carries bits to identify its type Programs that operate on structures rather than words Functional approach Replacing computation as a sequence of discrete operations Data flow model – order of execution depends on data interdependence 20
- 21. Conclusion & Further reading You should now be sufficiently familiar with general system structure to guide your studies throughout the remainder of this course. Subsequent lectures will explore many of these topics in great detail. Essentials of Computer Organization & architecture – Linda Null => Chapter 1 21