The Von Neumann architecture is characterized by its serial processing nature, fetch-decode-execute cycle, and use of a common bus. It has four main components: a processor, memory, I/O devices, and secondary storage. The processor contains an arithmetic logic unit and control unit, and uses registers like the program counter, memory address register, and accumulator. Instructions are fetched from memory one at a time by the processor and executed sequentially, limiting processor speed.

1. Von Neumann
Architecture
1
Computer
Organisation
Loren Al Hamwi

2. 2
• What are the important features of Von Neum
- Why is processor speed limited in
the Von Neumann Architecture?
• How does the Fetch-Decode-
Execute cycle work?

3. What is Von Neumann
Architecture?
Digital Computer- 4 parts:
1. Processor design (Arithmetic & control
units + along with internal memory)
2.Memory to store data and instructions
3.I/O devices
4.Secondary storage
3

4. Processor
Main Memory
Arithmetic &
Logic Unit
Control Unit
Input Devices
Output Devices
Mass Storage
4

5. 5
Serial Nature
There is one bus used to transport data an
instructions
Only One Instruction
at a Time

6. 6
Think about how programs are written in
sequences…..
.Instructions are stored in CPU registers
.Locations are directly modified as a result of
instruction execution
Fetch
DecodeExecute
Why Von Neumann Architect
These sequences of instructions relate to the
serial nature of Von Neumann processors.

7. Registers:
1-Program Counter =>PC
2-Memory Address Register
=>MAR
3-Memory Data Register
=>MDR
4-Current Instruction Register
=>CIR
5-Accumulator =>ACC
Other Important Components: 7

8. Processor
Arithmetic &
Logic Unit
Control Unit
PC
MAR
MDR
CIR
ACC
Primary Memory
Fetch Decode Execute
Start StartStart
Stop
Stop
Stop
Copy
address
from PC to
MAR
Get data
from primary
memory
and copy to
MDR
Copy from
MDR to CIR
Increment PC
Split opcode
from data
(address) in
MDR
Control unit
interprets
opcode
(Data)
Address
copied from
CIR to MAR
Get data
from primary
memory and
copy to MDR
Instruction
executed
8
+1

9. Decode: Splitting an instruction
Opcode Operand
Opcode
Operand 1
Operand 2
bit
-15
bit
-15
bit 0
bit 0
Instruc
tion
Data or
Address
Result stored in
Accumulator
9

10. Executing
instructions:
. Calculations:
-Contents of MDR sent
to MDR
. Jump Instructions:
-Contents of MDR
sent to PC
10

11. 11
Thank You
for
Your
Attention