This document discusses an intelligent clock gating technique to reduce power consumption in VLSI sequential circuits. It describes implementing the technique on an asynchronous counter in Xilinx Vivado and comparing the power with and without clock gating. With intelligent clock gating, the asynchronous counter design saw a 21.57% reduction in dynamic power consumption from 3.432W to 2.692W. Intelligent clock gating automatically inserts clock enable signals to turn off unused portions of the design, reducing unnecessary switching without affecting functionality or timing constraints. This allows significant power savings to be achieved with less manual effort compared to traditional clock gating techniques.