This paper presents a power-optimized ALU design using a control-signal gating technique to reduce switching activity on datapath buses. The proposed ALU model shows improved dynamic power consumption compared to a conventional ALU model, making it a viable solution for power efficiency in digital circuits. Future work will explore integrating clock gating techniques to further minimize unnecessary switching activities.

1. Power Optimized ALU Design with Control-Signal
Gating Technique for Efficient Datapath
Anil Kumar Yadav
Department of Electronics Engineering
Pondicherry University
Pondicherry, India.
anil8210yadav@gmail.com
Mohammed Aneesh Y.
Department of Electronics Engineering
Pondicherry University
Pondicherry, India.
aneeshssw1@gmail.com
Abstract— In this paper, we have presented an ALU
(Arithmetic and Logic Unit) with a control-signal gating
technique for reducing the switching activity on datapath buses.
The main idea behind this logic is the control-signal gating
technique that will detect the bus, which is not going to be used
and it will turn on only that unit which is functioning and
switch-off the module which is not functioning. Control-gating
circuit employs a series of AND gate on the input bus line which
is controlled by a decoder. We have compared the dynamic
power of proposed ALU model with conventional ALU by
considering target FPGA device Virtex-6 low power with speed
grade -1L.
Keywords— control-signal gating, data buses, low power,
switching activity, dynamic power.
I. INTRODUCTION
ALU is one of the basic blocks and crucial component of all
the processing unit. It mainly consists of a number of
functional units, for different arithmetic, logic and shift
operation, making it the hot spot of datapath. An important
part of energy is wasted in the datapath due to switching
activity that does not contribute to the functionality of the
circuit, causing power dissipation.
Power dissipation consists of two components: static power
and dynamic power. Dynamic power is also called as
switching power which is dissipated due to the switching
activity. Dynamic power is defined as:
Pdynamic = α * c * v2
*f (1)
In equation (1): α is the switching activity, c the capacitance,
v the supply voltage and f the frequency of operation. From
the relation, it is observed that the dynamic power is
proportional to the frequency and the switching activity.
Thus, the possible solution to reduce power could be achieve
by reducing the switching activity and not the frequency as,
devices need to operate at high speed.
There are different technique which has been proposed to
suppress this switching activity like Pre-computational logic,
guarded evaluation etc. [6]. To reduce the power on datapath
buses, it is necessary to employ a technique that can reduce
its switching activity. So, here we introduces a method that
can be used for reducing the switching activity on datapath
buses, named control-signal gating technique.
The control-signal technique implements the advantage of a
fine granularity analysis to minimize the switching activity of
the datapath buses which is based on the observability don’t
care concept (ODC) to detect the bus when it is not going to
be use and to block the propagation of the switching activity
through the module(s) driving the bus [1]. There are different
ways to employ control-signal gating. The simplest one is to
put an AND/ OR gate at the signal path to stop the
propagation of signal, when there is no need of it. Another
method is to use a latch or flip-flop to stop the propagation of
the signal. Sometimes, a transmission gate or a tristate buffer
can be used in place of a latch if charge leakage is not a
concern. All signal gating method requires control signals to
stop the propagation of switching activities as shown in
Fig.1.
The proposed control-signal gating circuit consists of a series
of AND Control gates which is controlled by a decoder. The
output of decoder is connected to one of the inputs of the
AND gate and input of decoder is connected to the selection
line of the ALU, which is act as a controlling signal for this
logic circuit and other input of the AND gate.
Fig.1. Control-Signal Gating Technique
II. CONVENTIONAL16-BIT ALU
We have introduced a conventional 16-bit ALU to compare
the results of proposed ALU model. Conventional 16-bit ALU
consists of sixteen operational blocks, whose operation has
been explained in Table I. and it is simulated in Xilinx Tool,
whose top level schematic (RTL) view and timing waveform
is shown in Fig.2 and Fig.3.
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2. Table I. Function of ALU
Select
operation
Arithmetic
Operation
Select
operation
Logic
Operation
0000 Add 1000 OR
0001 Subtract 1001 AND
0010 Increment 1010 NOT
0011 Decrement 1011 EXOR
0100 Multiply 1100 Shift right
0101 Division 1101 Shift left
0110 Clear 1110 Rotate right
0111 Set 1111 Rotate left
Fig.2. Top level schematic of conventional ALU
Fig.3. Timing waveform of conventional ALU
III. PROPOSED ALU MODEL WITH CONTROL-SIGNAL GATING
A. Architecture and Functional of Proposed ALU
The architecture of proposed ALU is shown in Fig.4,
which consist of ALU with control-signal gating circuit.
Control-gating circuitry consist of a series of AND gate with
decoder, input of each AND gate is fed with output of decoder
to control the input bit line and input of decoder is connected
with Selection line of ALU. Selection line is used to select the
operation of ALU, which is also fed with OUTMUX of ALU.
Here, control-signal gating has been introduced to reduce the
switching activity of datapath, when one operation is running
and other is not. For example, when selection line is “0000”
then it will select the first AND gate of both input bit line and
it will switch on the first bit line of ALU and OUTMUX will
select the first output of ALU. Hence, by introducing this
technique we can reduce the switching activity of other fifteen
input bit line.
Fig.4. Architecture of proposed ALU
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3. B. Top level schematic (RTL) of proposed ALU
The top level schematic of proposed model is shown in
Fig.5.
Fig.5. Top level schematic of proposed ALU
C. Timing waveform of proposed ALU
The timing waveform for proposed model is shown in Fig.6.
Fig.6. Timing waveform of proposed model
IV. SIMULATION RESULTS
A. Power comparison
The dynamic and total power for conventional and proposed
model is calculated by Xilinx X’Power Analyzer tool
considering target FPGA Device Virtex-6 low power with
speed grade -1L, given in Table II.
Table II. Power comparison of both model
Parameter Conventional model Proposed model
Total power 1176 mW 1173 mW
Dynamic power 77 mW 74 mW
Quiescent Power 1099 mW 1099 mW
Hence, it can be inferred from the Table II and can be seen from
Fig. 7 that the proposed model consumes less dynamic power
than conventional model.
Fig.7. Dynamic power comparison of conventional and
proposed ALU model
B. Device Utilization Summary
Device Utilization Summary of both the model
(conventional as well as proposed) is shown in Fig.7 and Fig.8.
Fig.7. Device utilization summary of conventional model
Fig.8. Device utilization summary of proposed Model
77
74
72
74
76
78
Dynamic Power (mW)
Dynamic Power Comparison
Conventional Model Proposed Model
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4. V. CONCLUSION
Hence, we have designed, simulated and compared the result
of both the model using Xilinx Tool and it has been seen that the
ALU with control-signal gating techniques consumes less power
than conventional model. So, it can be concluded that the
proposed model can be utilized as power optimized technique to
reduce the switching activity on datapath buses. There are other
logic circuitry which can be developed and designed in future to
control the switching activity on datapath buses. Future work
includes the implementation of clock gating technique with
control-signal gating technique to reduce the unnecessary
switching activity of clock and datapath buses, when there is no
need of it.
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