In this paper, we have presented an ALU (Arithmetic and Logic Unit) with a control-signal gating technique for reducing the switching activity on datapath buses. The main idea behind this logic is the control-signal gating technique that will detect the bus, which is not going to be used and it will turn on only that unit which is functioning and switch-off the module which is not functioning. Control-gating circuit employs a series of AND gate on the input bus line which is controlled by a decoder. We have compared the dynamic power of proposed ALU model with conventional ALU by considering target FPGA device Virtex-6 low power with speed grade -1L.