This document describes the design and implementation of a low power 16-bit arithmetic logic unit (ALU) using clock gating. Clock gating is used to selectively clock only the active modules of the ALU, reducing dynamic power consumption by an estimated 66.7%. The ALU uses a variable block length carry skip adder for arithmetic operations and supports logic operations. It is implemented in VHDL and synthesized on a Xilinx Spartan 3E FPGA, achieving a maximum frequency of 65.19MHz with reduced power consumption compared to a non-clock gated design. Clock gating selectively activates either the arithmetic or logic units using control signals to reduce unnecessary switching activity and lower dynamic power dissipation.