This document discusses low power CMOS binary counters. It proposes a clock gating technique for flip-flops to reduce power consumption in counters. It compares conventional non-clock gated, clock gated, and the proposed conditionally pulsed clock gating flip-flop designs. Simulation results in 0.18um CMOS technology show the proposed technique reduces power by 12% over conventional clock gating. Synchronous counters are chosen over asynchronous ones for their ability to scale to more bits with less delay per bit, important for reducing leakage power in high leakage technologies.