This document discusses efficient testing of SRAM using clock gating techniques. It begins with an introduction about how memory elements occupy most of the chip area in modern SOCs and outlines reliability issues with tightly integrated memory. It then describes March C and TLAPNPSF algorithms that are used for efficient memory testing. The document proposes using clock gating applied to a ring counter to selectively power memory rows during testing, reducing power consumption. It provides details on delay buffers used for temporary data storage and describes the implementation of a ring counter using D flip-flops to sequentially select memory addresses.
This document presents a sequential quadratic programming (SQP) algorithm for sizing clock meshes to minimize area while meeting skew constraints. The algorithm uses adjoint sensitivity analysis and a compact gate model to efficiently compute sensitivities. It formulates and solves a quadratic programming subproblem at each iteration to determine wire width updates. Experimental results on ISCAS and ISPD benchmarks show up to 33% reduction in clock mesh area compared to initial designs. Future work will extend the approach to simultaneously size interconnects and buffers.
IRJET- Metastability Mitigation & Error Masking of High Speed Flip-FlopIRJET Journal
This document discusses techniques for mitigating metastability and masking timing errors in high-speed flip-flops. It proposes flip-flop designs that take advantage of delayed data or pulse-based methods to detect timing violations. Simulation results show the proposed flip-flops can reduce error masking latency by up to 23% and increase the effective timing error detection window compared to state-of-the-art metastability immune flip-flops. The document also analyzes metastability in flip-flops qualitatively and quantitatively, and evaluates the performance of the proposed designs in reducing metastability errors.
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
The document provides a project report on the physical design implementation of a torpedo subsystem. Key aspects covered include:
1. Floorplanning with goals of power planning and defining placement and routing blockages. The initial floorplan resulted in an IR drop of 88.9mV.
2. Placement was performed with a focus on timing optimization and congestion reduction. This resulted in a worst negative slack of -1.75ns and total negative slack of -19256.
3. Clock tree synthesis was done to balance skew and meet timing targets. This reduced hold violations from 14247 to 316.
4. Routing created physical interconnects for clocks and signals using global routing, track assignment, and detailed routing
Thermal reliability faces critical challenges from emerging FinFET-based designs. As designs transition from planar MOS to FinFET transistors, current density increases by 25% and that combined with lower thermal conductivity substrate and 3-D narrow fin structure, local heat gets trapped resulting in thermal-aware EM issues. This presentation introduces Sentinel-TI™, a thermal integrity platform and demonstrates how Chip Thermal Model (CTM™) based power-thermal convergence and interconnect-driven methodology help address the thermal reliability challenges associated with these design. Learn more on our website: https://bit.ly/1sh7I8p, https://bit.ly/1CW3FRT, https://bit.ly/1qk5Juj and (https://bit.ly/1rtrGat)
Totem Technologies for Analog, Memory, Mixed-Signal DesignsAnsys
Analog, mixed-signal and custom designs face unique challenges when it comes to power and reliability analysis. SRAM and FLASH memories are pushing the envelope to handle large designs, while mixed-signal and RF designs need concurrent analysis of large analog blocks with interspersed digital logic as well as substrate noise coupling. This presentation demonstrates how Totem, a single platform for Power Noise and Reliability, can be used to address the unique challenges for analog, mixed-signal and custom designs. Learn more on our website: https://bit.ly/1qk5Juj
This document discusses topographical synthesis and its benefits. Topographical synthesis enables congestion prediction and avoidance early in the design flow during synthesis. It uses advanced optimization algorithms to deliver high quality results that correlate well to physical implementation. This eliminates costly iterations between synthesis and layout. Key benefits include accurately predicting congestion hotspots, performing optimizations to minimize congestion, and delivering results matched to post-layout timing and area without needing wire load models.
Full DDR Bank Power and Signal Integrity Analysis with Chip-Package-System Co...Ansys
For today's DDR/IO designs, reliable and predictable chip-to-chip signal transmission depends on the quality of the voltage delivered to the I/O circuit and the magnitude of the signal-to-signal and signal-to-power coupling. Validation of high-speed parallel I/O interfaces requires simulation of an entire I/O bank together with the entire power distribution network for the die, package and the PCB. This presentation discusses Sentinel-SSO™ and how its underlying technologies deliver sign-off accurate I/O-SSO verification with the capacity to handle an entire I/O bank. Learn more on our website: https://bit.ly/1qklvW0
This document presents a sequential quadratic programming (SQP) algorithm for sizing clock meshes to minimize area while meeting skew constraints. The algorithm uses adjoint sensitivity analysis and a compact gate model to efficiently compute sensitivities. It formulates and solves a quadratic programming subproblem at each iteration to determine wire width updates. Experimental results on ISCAS and ISPD benchmarks show up to 33% reduction in clock mesh area compared to initial designs. Future work will extend the approach to simultaneously size interconnects and buffers.
IRJET- Metastability Mitigation & Error Masking of High Speed Flip-FlopIRJET Journal
This document discusses techniques for mitigating metastability and masking timing errors in high-speed flip-flops. It proposes flip-flop designs that take advantage of delayed data or pulse-based methods to detect timing violations. Simulation results show the proposed flip-flops can reduce error masking latency by up to 23% and increase the effective timing error detection window compared to state-of-the-art metastability immune flip-flops. The document also analyzes metastability in flip-flops qualitatively and quantitatively, and evaluates the performance of the proposed designs in reducing metastability errors.
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
The document provides a project report on the physical design implementation of a torpedo subsystem. Key aspects covered include:
1. Floorplanning with goals of power planning and defining placement and routing blockages. The initial floorplan resulted in an IR drop of 88.9mV.
2. Placement was performed with a focus on timing optimization and congestion reduction. This resulted in a worst negative slack of -1.75ns and total negative slack of -19256.
3. Clock tree synthesis was done to balance skew and meet timing targets. This reduced hold violations from 14247 to 316.
4. Routing created physical interconnects for clocks and signals using global routing, track assignment, and detailed routing
Thermal reliability faces critical challenges from emerging FinFET-based designs. As designs transition from planar MOS to FinFET transistors, current density increases by 25% and that combined with lower thermal conductivity substrate and 3-D narrow fin structure, local heat gets trapped resulting in thermal-aware EM issues. This presentation introduces Sentinel-TI™, a thermal integrity platform and demonstrates how Chip Thermal Model (CTM™) based power-thermal convergence and interconnect-driven methodology help address the thermal reliability challenges associated with these design. Learn more on our website: https://bit.ly/1sh7I8p, https://bit.ly/1CW3FRT, https://bit.ly/1qk5Juj and (https://bit.ly/1rtrGat)
Totem Technologies for Analog, Memory, Mixed-Signal DesignsAnsys
Analog, mixed-signal and custom designs face unique challenges when it comes to power and reliability analysis. SRAM and FLASH memories are pushing the envelope to handle large designs, while mixed-signal and RF designs need concurrent analysis of large analog blocks with interspersed digital logic as well as substrate noise coupling. This presentation demonstrates how Totem, a single platform for Power Noise and Reliability, can be used to address the unique challenges for analog, mixed-signal and custom designs. Learn more on our website: https://bit.ly/1qk5Juj
This document discusses topographical synthesis and its benefits. Topographical synthesis enables congestion prediction and avoidance early in the design flow during synthesis. It uses advanced optimization algorithms to deliver high quality results that correlate well to physical implementation. This eliminates costly iterations between synthesis and layout. Key benefits include accurately predicting congestion hotspots, performing optimizations to minimize congestion, and delivering results matched to post-layout timing and area without needing wire load models.
Full DDR Bank Power and Signal Integrity Analysis with Chip-Package-System Co...Ansys
For today's DDR/IO designs, reliable and predictable chip-to-chip signal transmission depends on the quality of the voltage delivered to the I/O circuit and the magnitude of the signal-to-signal and signal-to-power coupling. Validation of high-speed parallel I/O interfaces requires simulation of an entire I/O bank together with the entire power distribution network for the die, package and the PCB. This presentation discusses Sentinel-SSO™ and how its underlying technologies deliver sign-off accurate I/O-SSO verification with the capacity to handle an entire I/O bank. Learn more on our website: https://bit.ly/1qklvW0
The document discusses various layout optimizations that can be made to standard cells to reduce both internal power and area. These include removing "hammer head" structures to decrease transistor length, moving gate contacts over active areas to reduce transistor height, and reducing source/drain capacitances to decrease dynamic current without impacting speed. Post-layout simulations showed a new D flip-flop design with these optimizations reduced internal power by 20% while maintaining clock-to-Q delay, and improved saturation current by 15-50% while reducing area by 20%.
High performance standard cell layout synthesis for advanced nanometer國立交通大學
This document summarizes a presentation on standard cell layout synthesis for advanced technology nodes. It discusses the challenges of standard cell design at smaller process nodes. The presentation introduces standard cell basics and describes a cell layout synthesis flow involving transistor placement, cell routing, and transistor folding. It provides experimental results comparing the proposed flow to a commercial standard cell library, showing improvements in area and routing resources while maintaining similar performance. Future work areas discussed include routability estimation during transistor placement and new techniques for advanced process nodes.
The document discusses upgrading the emergency shutdown (ESD) system for an oil and gas platform's turret equipment room (TER) to provide additional spare capacity. It analyzes various techniques for increasing spare capacity in the TER ESD system. It determines that replacing the existing TER ESD system with a new Trusted triple modular redundant (TMR) safety system would be the best option, as it offers increased capacity, fault tolerance and availability within the existing installation space constraints.
IRJET - Augmented Tangible Style using 8051 MCUIRJET Journal
This document describes the optimization of an 8051 microcontroller design using VLSI techniques. The original 8051 design operated at 12 MHz with a large chip area due to its 3.5um process technology. The authors synthesized the RTL code of the 8051 using a 90nm process, which allowed it to operate at 150 MHz with a 77249.814850um2 chip area, 12.5x faster and 30% smaller than the original. Floorplanning, placement, routing, and other physical design steps were performed. Power consumption was reduced by at least 32% to 593.9899uW compared to other 8051 derivatives. The optimized design demonstrated significant improvements in speed, area, and power consumption through
The document compares different types of testers used for debugging components, including S9K, IMS Vanguard, and CWMA testers, describing their key features such as speed, operating system, memory size, and capabilities for timing, patterns, and levels of testing. It also provides overviews of tester channel connections, functional test content and tools, and terms and definitions used for testing.
1) The document discusses the history and development of EMTP-RV, a software for simulating electromagnetic transients. 2) EMTP-RV is a completely new version that took 5 years and over 1 million lines of code to develop. 3) Support and ongoing development is led by Jean Mahseredjian at École Polytechnique de Montréal along with various partners.
Digital standard cell library Design flowijsrd.com
Commercial library cells are companies 'proprietary information and understandably companies usually impose certain restrictions on the access and use of their library cells. Those restrictions on commercial library cells severely hamper VLSI research and teaching activities of academia. To address the problem the goal of this paper is to discuss the development of standard cell library. This involves in creating new standard cells, layout design, simulation and verification of each standard cell and finally characterization of all cells for timing and functional properties.
This document contains information about various VLSI and low power projects, including titles, codes, and brief descriptions. It lists 30 projects related to topics like area-efficient adders and multipliers, low power filter and encryption designs, testing techniques, and transforms. The projects aim to optimize aspects like area, speed, power consumption and implementation on FPGAs or ASICs.
Pactron is an electronics design and manufacturing company founded in 1988. They provide end-to-end services including design, engineering, manufacturing, and testing of printed circuit boards. They have design centers in California and India and manufacturing facilities in multiple locations. Pactron produces a broad range of products including evaluation boards, reference designs, system boards, and final test boards for the semiconductor, telecom, industrial, and medical industries.
This document discusses various concepts related to physical design implementation. It describes the inputs and outputs of physical design tools, important checks to perform before starting design such as clock and high fanout net budgeting, and concepts like floorplanning, placement, routing, libraries, multi-voltage design, and clock tree synthesis and optimization.
FD-SOI Harnessing the Power - DAC 2016 Austin PresentationRick Tewell
A brief analysis of the measured benefits of FD-SOI semiconductor process technology. Answers the question about whether FD-SOI can deliver on the promises of power efficiency versus frequency tuning.
IRJET- Design of Area Efficient and Highly Reliable RHBD 10T Memory Cell for ...IRJET Journal
The document presents a design for an area efficient and highly reliable 10T memory cell for use in aerospace applications. It aims to balance performance, area, power, and reliability. An existing 12T radiation-hardened memory cell is described first but has large area overhead. The proposed 10T cell is then presented and analyzed through simulations. It can tolerate single node upsets while keeping smaller area. Write and read access times are increased as a tradeoff. Compared to other hardened cells, the 10T cell provides a good balance of metrics required for aerospace memories operating in radiation environments.
The document provides a profile summary for Jushoraj Veluppal, an analog layout engineer with over 4 years of experience in analog and custom digital layouts. It details his work experience with various companies on projects involving SERDES, frequency synthesizers, standard cells and more. Technologies include TSMC 110nm, 40nm, GF 28nm, 20nm and 14nm.
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
https://www.udemy.com/vlsi-academy
The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'.
IRJET- An Improved DCM-Based Tunable True Random Number Generator for Xilinx ...IRJET Journal
The document describes an improved tunable true random number generator (TRNG) design for Xilinx FPGAs based on the principle of beat frequency detection. The proposed TRNG uses two digital clock manager (DCM) modules instead of ring oscillators to generate oscillating waveforms. It has the key advantage of on-the-fly tunability through dynamic partial reconfiguration to modify DCM parameters and improve randomness characteristics without impacting normal functionality. Experimental results on a Xilinx Virtex-5 FPGA show the TRNG passes statistical tests and has low hardware overhead and built-in bias removal capabilities.
Field Measurement Options for Network OperatorsADVA
The document discusses field measurement options for network operators to monitor synchronization. It describes how synchronization probes can be used to monitor slave clocks, boundary clocks, and the network by measuring time error, time interval error, and mean time interval error. Probes can monitor clocks and network paths passively by tapping signals or actively by exchanging precision time protocol messages. This allows operators to ensure synchronization quality and detect any issues to help meet new stringent time and phase requirements for next generation networks.
Design for Testability in Timely Testing of Vlsi CircuitsIJERA Editor
Even though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system.Two main issues related to test and security domain are scan-based attacks and misuse of JTAG interface. Design for testability presents effective and timely testing of VLSI circuits. The project is to test the circuits after design and then reduce the area, power, delay and security of misuse. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in self-test (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both. BIST is usually performed using pseudorandom pattern generators (PRPGs). Among the advantages of pseudorandom BIST are: (1) the low cost compared to testing from automatic test equipment (ATE). (2) The speed of the test, which is much faster than when it is applied from ATE. (3) The applicability of the test while the circuit is in the field, and (4) the potential for high quality of test.
IRJET- UART Testing under Built-In-Self-Test(BIST) using Verilog on FPGAIRJET Journal
This document discusses testing of a UART (Universal Asynchronous Receiver/Transmitter) chip using Built-In Self-Test (BIST) and implemented with Verilog on an FPGA. It proposes a BIST-enabled UART architecture that uses a linear feedback shift register (LFSR) as the test pattern generator and a multiple input shift register (MISR) as the response analyzer. The goal is to provide high test coverage with low hardware overhead. Key aspects of BIST and how it can test chips through embedded self-testing circuits like LFSRs and MISRs are described. The paper also discusses implementing and testing the proposed BIST-enabled UART design using Verilog on an FPGA to
The document discusses various layout optimizations that can be made to standard cells to reduce both internal power and area. These include removing "hammer head" structures to decrease transistor length, moving gate contacts over active areas to reduce transistor height, and reducing source/drain capacitances to decrease dynamic current without impacting speed. Post-layout simulations showed a new D flip-flop design with these optimizations reduced internal power by 20% while maintaining clock-to-Q delay, and improved saturation current by 15-50% while reducing area by 20%.
High performance standard cell layout synthesis for advanced nanometer國立交通大學
This document summarizes a presentation on standard cell layout synthesis for advanced technology nodes. It discusses the challenges of standard cell design at smaller process nodes. The presentation introduces standard cell basics and describes a cell layout synthesis flow involving transistor placement, cell routing, and transistor folding. It provides experimental results comparing the proposed flow to a commercial standard cell library, showing improvements in area and routing resources while maintaining similar performance. Future work areas discussed include routability estimation during transistor placement and new techniques for advanced process nodes.
The document discusses upgrading the emergency shutdown (ESD) system for an oil and gas platform's turret equipment room (TER) to provide additional spare capacity. It analyzes various techniques for increasing spare capacity in the TER ESD system. It determines that replacing the existing TER ESD system with a new Trusted triple modular redundant (TMR) safety system would be the best option, as it offers increased capacity, fault tolerance and availability within the existing installation space constraints.
IRJET - Augmented Tangible Style using 8051 MCUIRJET Journal
This document describes the optimization of an 8051 microcontroller design using VLSI techniques. The original 8051 design operated at 12 MHz with a large chip area due to its 3.5um process technology. The authors synthesized the RTL code of the 8051 using a 90nm process, which allowed it to operate at 150 MHz with a 77249.814850um2 chip area, 12.5x faster and 30% smaller than the original. Floorplanning, placement, routing, and other physical design steps were performed. Power consumption was reduced by at least 32% to 593.9899uW compared to other 8051 derivatives. The optimized design demonstrated significant improvements in speed, area, and power consumption through
The document compares different types of testers used for debugging components, including S9K, IMS Vanguard, and CWMA testers, describing their key features such as speed, operating system, memory size, and capabilities for timing, patterns, and levels of testing. It also provides overviews of tester channel connections, functional test content and tools, and terms and definitions used for testing.
1) The document discusses the history and development of EMTP-RV, a software for simulating electromagnetic transients. 2) EMTP-RV is a completely new version that took 5 years and over 1 million lines of code to develop. 3) Support and ongoing development is led by Jean Mahseredjian at École Polytechnique de Montréal along with various partners.
Digital standard cell library Design flowijsrd.com
Commercial library cells are companies 'proprietary information and understandably companies usually impose certain restrictions on the access and use of their library cells. Those restrictions on commercial library cells severely hamper VLSI research and teaching activities of academia. To address the problem the goal of this paper is to discuss the development of standard cell library. This involves in creating new standard cells, layout design, simulation and verification of each standard cell and finally characterization of all cells for timing and functional properties.
This document contains information about various VLSI and low power projects, including titles, codes, and brief descriptions. It lists 30 projects related to topics like area-efficient adders and multipliers, low power filter and encryption designs, testing techniques, and transforms. The projects aim to optimize aspects like area, speed, power consumption and implementation on FPGAs or ASICs.
Pactron is an electronics design and manufacturing company founded in 1988. They provide end-to-end services including design, engineering, manufacturing, and testing of printed circuit boards. They have design centers in California and India and manufacturing facilities in multiple locations. Pactron produces a broad range of products including evaluation boards, reference designs, system boards, and final test boards for the semiconductor, telecom, industrial, and medical industries.
This document discusses various concepts related to physical design implementation. It describes the inputs and outputs of physical design tools, important checks to perform before starting design such as clock and high fanout net budgeting, and concepts like floorplanning, placement, routing, libraries, multi-voltage design, and clock tree synthesis and optimization.
FD-SOI Harnessing the Power - DAC 2016 Austin PresentationRick Tewell
A brief analysis of the measured benefits of FD-SOI semiconductor process technology. Answers the question about whether FD-SOI can deliver on the promises of power efficiency versus frequency tuning.
IRJET- Design of Area Efficient and Highly Reliable RHBD 10T Memory Cell for ...IRJET Journal
The document presents a design for an area efficient and highly reliable 10T memory cell for use in aerospace applications. It aims to balance performance, area, power, and reliability. An existing 12T radiation-hardened memory cell is described first but has large area overhead. The proposed 10T cell is then presented and analyzed through simulations. It can tolerate single node upsets while keeping smaller area. Write and read access times are increased as a tradeoff. Compared to other hardened cells, the 10T cell provides a good balance of metrics required for aerospace memories operating in radiation environments.
The document provides a profile summary for Jushoraj Veluppal, an analog layout engineer with over 4 years of experience in analog and custom digital layouts. It details his work experience with various companies on projects involving SERDES, frequency synthesizers, standard cells and more. Technologies include TSMC 110nm, 40nm, GF 28nm, 20nm and 14nm.
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
https://www.udemy.com/vlsi-academy
The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'.
IRJET- An Improved DCM-Based Tunable True Random Number Generator for Xilinx ...IRJET Journal
The document describes an improved tunable true random number generator (TRNG) design for Xilinx FPGAs based on the principle of beat frequency detection. The proposed TRNG uses two digital clock manager (DCM) modules instead of ring oscillators to generate oscillating waveforms. It has the key advantage of on-the-fly tunability through dynamic partial reconfiguration to modify DCM parameters and improve randomness characteristics without impacting normal functionality. Experimental results on a Xilinx Virtex-5 FPGA show the TRNG passes statistical tests and has low hardware overhead and built-in bias removal capabilities.
Field Measurement Options for Network OperatorsADVA
The document discusses field measurement options for network operators to monitor synchronization. It describes how synchronization probes can be used to monitor slave clocks, boundary clocks, and the network by measuring time error, time interval error, and mean time interval error. Probes can monitor clocks and network paths passively by tapping signals or actively by exchanging precision time protocol messages. This allows operators to ensure synchronization quality and detect any issues to help meet new stringent time and phase requirements for next generation networks.
Design for Testability in Timely Testing of Vlsi CircuitsIJERA Editor
Even though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system.Two main issues related to test and security domain are scan-based attacks and misuse of JTAG interface. Design for testability presents effective and timely testing of VLSI circuits. The project is to test the circuits after design and then reduce the area, power, delay and security of misuse. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in self-test (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both. BIST is usually performed using pseudorandom pattern generators (PRPGs). Among the advantages of pseudorandom BIST are: (1) the low cost compared to testing from automatic test equipment (ATE). (2) The speed of the test, which is much faster than when it is applied from ATE. (3) The applicability of the test while the circuit is in the field, and (4) the potential for high quality of test.
IRJET- UART Testing under Built-In-Self-Test(BIST) using Verilog on FPGAIRJET Journal
This document discusses testing of a UART (Universal Asynchronous Receiver/Transmitter) chip using Built-In Self-Test (BIST) and implemented with Verilog on an FPGA. It proposes a BIST-enabled UART architecture that uses a linear feedback shift register (LFSR) as the test pattern generator and a multiple input shift register (MISR) as the response analyzer. The goal is to provide high test coverage with low hardware overhead. Key aspects of BIST and how it can test chips through embedded self-testing circuits like LFSRs and MISRs are described. The paper also discusses implementing and testing the proposed BIST-enabled UART design using Verilog on an FPGA to
Advancing VLSI Design Reliability: A Comprehensive Examination of Embedded De...IRJET Journal
The document summarizes research on Embedded Deterministic Test (EDT) logic insertion's impact on VLSI designs. Key findings include:
1) EDT insertion enhances test and fault coverage, but also increases the number of test patterns required.
2) There are significant shifts in fault sub-classes like untestable faults and tied cells after EDT insertion, highlighting its nuanced effects.
3) Results provide empirical evidence for designers to optimize testability by strategically integrating EDT logic.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Improvement in Error Resilience in BIST using hamming codeIJMTST Journal
In the current scenario of IP core based SoC, to test the CUT we need to communication link between Circuit Under Test and ATPG, so before applying to actual DUT. If there is a problem with this link, there may be a lip in bit of test data. Compared to original test data, if there is a bit lip in the original data, the codeword may change and hence the decompressed data will have a large number of bit deviation. This deviation in bits can severely degrade the test quality and overall fault coverage which may affect yield. The error resilience is the capability of the test data to resist against such bit lips. Here in this paper, the earlier methods of error resilience is compared and a Hamming code based error resilience technique is proposed to improve the error resilience capacity of compressed test data. This method is applied on Huffman code based compressed test data of widely used ISCAS benchmark circuits. The fault coverage measurement results show the effectiveness of the proposed method. The basic goal here is to survey the effect of bit lips on fault coverage and prepare a platform for further development in this avenue.
IRJET- A Unique Methodology for Transmission Line Breakage Detection and ...IRJET Journal
This document describes a proposed system for detecting transmission line breakages and alerting relevant parties. The system uses voltage sensors along transmission lines to continuously monitor voltages between sections. If a rapid voltage change is detected between two sections, a signal is sent to trip the power supply and alert the public via buzzers. Data is communicated between sections using wireless sensor networks. The system is simulated using a PIC microcontroller and results are displayed on an LCD screen and transmitted to peripherals. The goal of the system is to quickly detect broken power lines to prevent electrical accidents and power outages.
IRJET- Comparative Analysis of High Speed SRAM Cell for 90nm CMOS TechnologyIRJET Journal
This document presents a comparative analysis of 6T and 8T SRAM cells for 90nm CMOS technology. It begins with an abstract discussing the simulation of low power SRAM cells at different frequencies. The main body then provides background on SRAM cells, discusses related work analyzing 6T and 8T SRAM cell designs. It presents the architecture and operating principles of an 8T SRAM cell, including write and read modes. Simulation results show the 8T SRAM cell has lower dynamic power consumption than a 6T cell, with readings of 82 micro Watts for read and 120 micro Watts for write. Logic validation testing confirms the 8T cell correctly writes and reads input bit values.
IRJET- Implementation of TPG-LFSR with Reseeding Pattern ValueIRJET Journal
This document discusses the implementation of a reseeding linear feedback shift register (RLFSR) for test pattern generation. RLFSR is used to generate pseudorandom test patterns for built-in self-test (BIST) to test circuits. It can reduce the number of test patterns needed and test time compared to traditional LFSR techniques. The proposed method uses a counter to generate seed values for the RLFSR to produce test patterns for the circuit under test. Experimental results demonstrate that the RLFSR approach can improve fault coverage while reducing storage and time requirements compared to other BIST methods.
This document discusses hardware design verification and testing techniques. It covers emulation architectures like FPGA-based and processor-based systems. It also discusses formal property verification methods, software formal verification, design for test objectives, chip-level DFT techniques, automatic test pattern generation, and testing techniques for analog/mixed-signal circuits like ADCs, PLLs and oscillators.
Study and Analysis of Low Power SRAM Memory Array at nano-scaled TechnologyIRJET Journal
This document summarizes a study analyzing the design of low-power SRAM memory arrays at nano-scaled CMOS technology. The study adapts a multi-threshold CMOS design to create a novel low-power 6T SRAM cell that can reduce power usage and access time by using transistors with different threshold voltages. Simulation results show that leakage power can be significantly reduced in the idle state, lowering overall power consumption. Various SRAM cell designs are reviewed and a 1KB SRAM memory array is implemented using the proposed low-power 6T SRAM cell to validate the approach.
IRJET- Low Voltage High Speed 8T SRAM Cell for Ultra-Low Power ApplicationsIRJET Journal
The document discusses an 8-transistor (8T) SRAM cell designed for low-power applications. The 8T SRAM cell aims to improve read and write operations at sub-threshold voltages down to 0.1V. It uses single-ended read and write operations enabled by additional access transistors. The 8T cell is proposed to reduce power consumption and delay compared to standard 6T and conventional 8T SRAM cells. Key aspects of the 8T cell include improved readability using a read assist technique and reduced dynamic power usage through two extra pass transistors.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET-Power Efficient Implementation of Asynchronous Counter using Intelligen...IRJET Journal
This document discusses an intelligent clock gating technique to reduce power consumption in VLSI sequential circuits. It describes implementing the technique on an asynchronous counter in Xilinx Vivado and comparing the power with and without clock gating. With intelligent clock gating, the asynchronous counter design saw a 21.57% reduction in dynamic power consumption from 3.432W to 2.692W. Intelligent clock gating automatically inserts clock enable signals to turn off unused portions of the design, reducing unnecessary switching without affecting functionality or timing constraints. This allows significant power savings to be achieved with less manual effort compared to traditional clock gating techniques.
Robust Fault Tolerance in Content Addressable Memory InterfaceIOSRJVSP
With the rapid improvement in data exchange, large memory devices have come out in recent past. The operational controlling for such large memory has became a tedious task due to faster, distributed nature of memory units. In the process of memory accessing it is observed that data written or fetched are often encounter with fault location and faulty data are written or fetched from the addressed locations. In real time applications, this error cannot be tolerated as it leads to variation in the operational condition dependent on the memory data. Hence, It is required to have an optimal controlling fault tolerance in content addressable memory. In this paper, we present an approach of fault tolerance approach by controlling the fault addressing overhead, by introducing a new addressing approach using redundant control modeling of fault address unit. The presented approach achieves the objective of fault controlling over multiple fault location in different dimensions with redundant coding.
IRJET- A Review Paper on Development of General Purpose Controller BoardIRJET Journal
This document provides a review of the development of a general purpose controller board. It describes the design and implementation of the controller board, which includes a microcontroller, analog sensors, communication capabilities, and a display. The controller board allows different applications by enabling communication between the microcontroller and connected devices. It provides a portable system for controlling, displaying, and manipulating inputs. The availability of various peripherals reduces complexity and cost. The controller board is programmed to perform tasks by running a set of instructions coded in the microcontroller. It provides a platform for real-time monitoring systems using sensors like a temperature sensor.
FPGA IMPLEMENTATION OF RECOVERY BOOSTING TECHNIQUE TO ENHANCE NBTI RECOVERY I...Editor IJMTER
Negative Bias Temperature Instability is an important lifetime reliability problem in
microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI
since one of the PMOS devices in the memory cell always has an input of ‘0’. Previously proposed
recovery techniques for SRAM cells aim to balance the degradation of the two PMOS devices by
attempting to keep their inputs at a logic ‘0’ exactly 50% of the time. However, one of the devices is
always in the negative bias condition at any given time. In this paper, we propose a technique called
Recovery Boosting that allows both PMOS devices in the memory cell to be put into the recovery
mode by slightly modifying the design of conventional SRAM cells to verify its functionality and
quantity area and power consumption.
FAULT DETECTION SCHEME OF 5 BUS BY ANN AND ANFISIRJET Journal
This document proposes a fault detection scheme for a 5 bus system using artificial neural networks (ANN) and adaptive neuro-fuzzy inference systems (ANFIS). The scheme involves using discrete wavelet transform (DWT) to preprocess current and voltage measurements and extract statistical features. These features are then input into three ANNs/ANFIS models for fault classification, identification of fault phase, and detection of fault location. Simulation results on the 5 bus system demonstrate the effectiveness of the proposed scheme in accurately detecting fault type, phase and location in a fast and robust manner compared to previous methods.
Enhanced Skewed Load and Broadside Power Reduction in Transition Fault TestingIJERA Editor
This Paper Proposes the T-algorithm technique to optimize the testing Skewed Load and Broadside architecture. And the architecture used to the compare the test pattern results. In this architecture, T-algorithm used to optimize the testing architecture. This architecture compare the test pattern output for the required any type of combinational architecture. The optimization process mainly focused by gate optimization for secure architecture. The proposed system to use the T-algorithm, to optimize the testing clocking level for the required test patterns. This technique to replace the flip flop and the mux arrangement. To reduce the flip flops in Skewed Load architecture. And to develop the accuracy for testing architecture. The proposed system consists of the secure testing architecture and includes the XOR-gate architecture. So the modification process applied by the Broadside and over all Skewed Load architecture. The proposed technique to check the scanning results for the testing process. The testing architecture mainly used to the error attack for the scanning process and the scanning process work with any type of testing architecture. The scanning process to be secure using the T-algorithm for the Skewed Load architecture. And to develop the testing process for the fault identification process. The diagnosis technique to detect error for the scanning process in any type combinational architecture. The T-algorithm used to reduce the circuit complexity for the testing architecture and the testing architecture used to reduce the delay level. And the future process, this technique used to reduce the gate level for the sticky comparator architecture and to modify the clocking function for the testing process. This technique to develop the accuracy level for the testing process compare to the present methodology.
IRJET- Adding Support for Vector Instructions to 8051 ArchitectureIRJET Journal
This document describes a project to add vectorization capabilities to the 8051 microcontroller architecture. Vectorization allows a single instruction to operate on arrays of data, called vectors, reducing instruction overhead compared to scalar operations. The authors propose adding vector register banks and vector instructions like VADD, VSUB, and VMUL to the 8051 instruction set. They implement control logic to sequentially access vector elements and demonstrate a 92.98% reduction in instructions for a matrix addition example compared to non-vectorized code. Potential applications in IoT devices and further work adding multiple ALUs or variable vector lengths are discussed.
IRJET- High Speed Multi-Rate Approach based Adaptive Filter using Multiplier-...IRJET Journal
This document presents a high-speed multi-rate approach for an adaptive filter using a multiplier-less technique. The proposed approach uses decimator and interpolator structures in VHDL to design a narrow band filter. Each structure is simulated using an FPGA and compared to existing structures. The resulting structure is more hardware efficient and uses fewer logic slices than existing structures. Key aspects of multi-rate signal processing and the proposed narrow band filter design using decimation and interpolation are discussed. Simulation results show the proposed approach reduces hardware complexity and resource usage compared to direct-form implementation of the filter.
Similar to IRJET- An Efficient and Low Power Sram Testing using Clock Gating (20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...IRJET Journal
This study compares the use of Stark Steel and TMT Steel as reinforcement materials in a two-way reinforced concrete slab. Mechanical testing is conducted to determine the tensile strength, yield strength, and other properties of each material. A two-way slab design adhering to codes and standards is executed with both materials. The performance is analyzed in terms of deflection, stability under loads, and displacement. Cost analyses accounting for material, durability, maintenance, and life cycle costs are also conducted. The findings provide insights into the economic and structural implications of each material for reinforcement selection and recommendations on the most suitable material based on the analysis.
Effect of Camber and Angles of Attack on Airfoil CharacteristicsIRJET Journal
This document discusses a study analyzing the effect of camber, position of camber, and angle of attack on the aerodynamic characteristics of airfoils. Sixteen modified asymmetric NACA airfoils were analyzed using computational fluid dynamics (CFD) by varying the camber, camber position, and angle of attack. The results showed the relationship between these parameters and the lift coefficient, drag coefficient, and lift to drag ratio. This provides insight into how changes in airfoil geometry impact aerodynamic performance.
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...IRJET Journal
This document reviews the progress and challenges of aluminum-based metal matrix composites (MMCs), focusing on their fabrication processes and applications. It discusses how various aluminum MMCs have been developed using reinforcements like borides, carbides, oxides, and nitrides to improve mechanical and wear properties. These composites have gained prominence for their lightweight, high-strength and corrosion resistance properties. The document also examines recent advancements in fabrication techniques for aluminum MMCs and their growing applications in industries such as aerospace and automotive. However, it notes that challenges remain around issues like improper mixing of reinforcements and reducing reinforcement agglomeration.
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...IRJET Journal
This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
The document discusses optimizing business management processes through automation using Microsoft Power Automate and artificial intelligence. It provides an overview of Power Automate's key components and features for automating workflows across various apps and services. The document then presents several scenarios applying automation solutions to common business processes like data entry, monitoring, HR, finance, customer support, and more. It estimates the potential time and cost savings from implementing automation for each scenario. Finally, the conclusion emphasizes the transformative impact of AI and automation tools on business processes and the need for ongoing optimization.
Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
The document describes the seismic design of a G+5 steel building frame located in Roorkee, India according to Indian codes IS 1893-2002 and IS 800. The frame was analyzed using the equivalent static load method and response spectrum method, and its response in terms of displacements and shear forces were compared. Based on the analysis, the frame was designed as a seismic-resistant steel structure according to IS 800:2007. The software STAAD Pro was used for the analysis and design.
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
artificial intelligence and data science contents.pptxGauravCar
What is artificial intelligence? Artificial intelligence is the ability of a computer or computer-controlled robot to perform tasks that are commonly associated with the intellectual processes characteristic of humans, such as the ability to reason.
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Artificial intelligence (AI) | Definitio
Design and optimization of ion propulsion dronebjmsejournal
Electric propulsion technology is widely used in many kinds of vehicles in recent years, and aircrafts are no exception. Technically, UAVs are electrically propelled but tend to produce a significant amount of noise and vibrations. Ion propulsion technology for drones is a potential solution to this problem. Ion propulsion technology is proven to be feasible in the earth’s atmosphere. The study presented in this article shows the design of EHD thrusters and power supply for ion propulsion drones along with performance optimization of high-voltage power supply for endurance in earth’s atmosphere.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.