VLSI stands for Very Large Scale Integrated Circuits.
SSI – Small Scale Integration (50s and 60s)
1 – 10 transistors
Simple logic gates
MSI – Medium Scale Integration(70s)
10-100 transistors
logic functions, counters, etc
LSI – Large Scale Integration(80s)
100-10,000 transistors
First microprocessors on the chip
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.
Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in large scale integration technologies and system design applications. With the advent of very large scale integration (VLSI) designs, the number of applications of integrated circuits (ICs) in high-performance computing, controls, telecommunications, image and video processing, and consumer electronics has been rising at a very fast pace.
The current cutting-edge technologies such as high resolution and low bit-rate video and cellular communications provide the end-users a marvelous amount of applications, processing power and portability. This trend is expected to grow rapidly, with very important implications on VLSI design and systems design.
VLSI stands for Very Large Scale Integrated Circuits.
SSI – Small Scale Integration (50s and 60s)
1 – 10 transistors
Simple logic gates
MSI – Medium Scale Integration(70s)
10-100 transistors
logic functions, counters, etc
LSI – Large Scale Integration(80s)
100-10,000 transistors
First microprocessors on the chip
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.
Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in large scale integration technologies and system design applications. With the advent of very large scale integration (VLSI) designs, the number of applications of integrated circuits (ICs) in high-performance computing, controls, telecommunications, image and video processing, and consumer electronics has been rising at a very fast pace.
The current cutting-edge technologies such as high resolution and low bit-rate video and cellular communications provide the end-users a marvelous amount of applications, processing power and portability. This trend is expected to grow rapidly, with very important implications on VLSI design and systems design.
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
Practical IEC 61850 for Substation Automation for Engineers and TechniciansLiving Online
COPY THIS LINK INTO YOUR BROWSER TO FIND OUT MORE: bit.ly/11AM1oL
Older (‘legacy’) substation automation protocols and hardware/software architectures provided basic functionality for power system automation, and were designed to accommodate the technical limitations of the technologies available at the time. However, in recent years there have been vast improvements in technology, especially on the networking side. This has opened the door for dramatic improvements in the approach to power system automation in substations.
The latest developments in networking such as high-speed, deterministic, redundant Ethernet, as well as other technologies including TCP/IP, high-speed Wide Area Networks and high-performance embedded processors, are providing capabilities that could hardly be imagined when most legacy substation automation protocols were designed.
IEC61850 is a part of the International Electro-technical Commission (IEC) Technical Committee 57 (TC57) architecture for electric power systems. It is an important new international standard for substation automation, and it will have a significant impact on how electric power systems are designed and built in future. The model-driven approach of IEC61850 is an innovative approach and requires a new way of thinking about substation automation. This will result in significant improvements in the costs and performance of electric power systems.
This workshop provides comprehensive coverage of IEC 61850 and will provide you with the tools and knowledge to tackle your next substation automation project with confidence.
WHO SHOULD ATTEND?
This workshop is designed for personnel with a need to understand the techniques required to use and apply IEC 61850 to substation automation, hydro power plants, wind turbines and distributed energy resources as productively and economically as possible. This includes engineers and technicians involved with:
Consulting
Control and instrumentation
Control systems
Design
Maintenance supervisors
Electrical installations
Process control
Process development
Project management
SCADA and telemetry systems
COPY THIS LINK INTO YOUR BROWSER TO FIND OUT MORE: bit.ly/11AM1oL
Practical IEC 61850 for Substation Automation for Engineers & TechniciansLiving Online
COPY THIS LINK INTO YOUR BROWSER FOR MORE INFORMATION: bit.ly/11AM1oL
Older (‘legacy’) substation automation protocols and hardware/software architectures provided basic functionality for power system automation, and were designed to accommodate the technical limitations of the technologies available at the time. However, in recent years there have been vast improvements in technology, especially on the networking side. This has opened the door for dramatic improvements in the approach to power system automation in substations.
The latest developments in networking such as high-speed, deterministic, redundant Ethernet, as well as other technologies including TCP/IP, high-speed Wide Area Networks and high-performance embedded processors, are providing capabilities that could hardly be imagined when most legacy substation automation protocols were designed.
IEC61850 is a part of the International Electro-technical Commission (IEC) Technical Committee 57 (TC57) architecture for electric power systems. It is an important new international standard for substation automation, and it will have a significant impact on how electric power systems are designed and built in future. The model-driven approach of IEC61850 is an innovative approach and requires a new way of thinking about substation automation. This will result in significant improvements in the costs and performance of electric power systems.
This workshop provides comprehensive coverage of IEC 61850 and will provide you with the tools and knowledge to tackle your next substation automation project with confidence.
WHO SHOULD ATTEND?
This workshop is designed for personnel with a need to understand the techniques required to use and apply IEC 61850 to substation automation, hydro power plants, wind turbines and distributed energy resources as productively and economically as possible. This includes engineers and technicians involved with:
Consulting
Control and instrumentation
Control systems
Design
Maintenance supervisors
Electrical installations
Process control
Process development
Project management
SCADA and telemetry systems
COPY THIS LINK INTO YOUR BROWSER FOR MORE INFORMATION: bit.ly/11AM1oL
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
Practical IEC 61850 for Substation Automation for Engineers and TechniciansLiving Online
COPY THIS LINK INTO YOUR BROWSER TO FIND OUT MORE: bit.ly/11AM1oL
Older (‘legacy’) substation automation protocols and hardware/software architectures provided basic functionality for power system automation, and were designed to accommodate the technical limitations of the technologies available at the time. However, in recent years there have been vast improvements in technology, especially on the networking side. This has opened the door for dramatic improvements in the approach to power system automation in substations.
The latest developments in networking such as high-speed, deterministic, redundant Ethernet, as well as other technologies including TCP/IP, high-speed Wide Area Networks and high-performance embedded processors, are providing capabilities that could hardly be imagined when most legacy substation automation protocols were designed.
IEC61850 is a part of the International Electro-technical Commission (IEC) Technical Committee 57 (TC57) architecture for electric power systems. It is an important new international standard for substation automation, and it will have a significant impact on how electric power systems are designed and built in future. The model-driven approach of IEC61850 is an innovative approach and requires a new way of thinking about substation automation. This will result in significant improvements in the costs and performance of electric power systems.
This workshop provides comprehensive coverage of IEC 61850 and will provide you with the tools and knowledge to tackle your next substation automation project with confidence.
WHO SHOULD ATTEND?
This workshop is designed for personnel with a need to understand the techniques required to use and apply IEC 61850 to substation automation, hydro power plants, wind turbines and distributed energy resources as productively and economically as possible. This includes engineers and technicians involved with:
Consulting
Control and instrumentation
Control systems
Design
Maintenance supervisors
Electrical installations
Process control
Process development
Project management
SCADA and telemetry systems
COPY THIS LINK INTO YOUR BROWSER TO FIND OUT MORE: bit.ly/11AM1oL
Practical IEC 61850 for Substation Automation for Engineers & TechniciansLiving Online
COPY THIS LINK INTO YOUR BROWSER FOR MORE INFORMATION: bit.ly/11AM1oL
Older (‘legacy’) substation automation protocols and hardware/software architectures provided basic functionality for power system automation, and were designed to accommodate the technical limitations of the technologies available at the time. However, in recent years there have been vast improvements in technology, especially on the networking side. This has opened the door for dramatic improvements in the approach to power system automation in substations.
The latest developments in networking such as high-speed, deterministic, redundant Ethernet, as well as other technologies including TCP/IP, high-speed Wide Area Networks and high-performance embedded processors, are providing capabilities that could hardly be imagined when most legacy substation automation protocols were designed.
IEC61850 is a part of the International Electro-technical Commission (IEC) Technical Committee 57 (TC57) architecture for electric power systems. It is an important new international standard for substation automation, and it will have a significant impact on how electric power systems are designed and built in future. The model-driven approach of IEC61850 is an innovative approach and requires a new way of thinking about substation automation. This will result in significant improvements in the costs and performance of electric power systems.
This workshop provides comprehensive coverage of IEC 61850 and will provide you with the tools and knowledge to tackle your next substation automation project with confidence.
WHO SHOULD ATTEND?
This workshop is designed for personnel with a need to understand the techniques required to use and apply IEC 61850 to substation automation, hydro power plants, wind turbines and distributed energy resources as productively and economically as possible. This includes engineers and technicians involved with:
Consulting
Control and instrumentation
Control systems
Design
Maintenance supervisors
Electrical installations
Process control
Process development
Project management
SCADA and telemetry systems
COPY THIS LINK INTO YOUR BROWSER FOR MORE INFORMATION: bit.ly/11AM1oL
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
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Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
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Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
Chapter_01 Course Introduction.pdf
1. FPGA & ASIC Design with Verilog
Digital system and Integrated Circuit
Design
Associate professor. Truong Ngoc Son
Email: sontn@hcmute.edu.vn
Mobile: 0931.085.929
Department of Computer and Communication Engineering
Faculty of Electrical and Electronics Engineering
2. Tools
Lecture notes from the LMS
Textbook
Software
Xilinx ISE Design Suite
Truong Ngoc Son, Ph.D - Department of Computer and Communication Engineering
3. Course goal
Truong Ngoc Son, Ph.D - Department of Computer and Communication Engineering
Why should student study FPGA and Verilog?
4. Student activity
Truong Ngoc Son, Ph.D - Department of Computer and Communication Engineering
Attending class
It is absolutely important that you attend class regularly (>80%)
Solving the problem
Take all examinations ( including online exam, paper-based exams)
Submit the homework on time
5. Course Outline
5
• Course Outline
• Introduction to IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
6. Course Outline
6
• Course Outline
• Introduction to ASIC/FPGA IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
7. Course Description
module RippleCarryAdderII (Cin, X, Y,S,Cout);
parameter n = 4; input Cin; input [n-1:0] X, Y; output [n-1:0] S;
wire [n-1:0] C;
Full_Adder stage0 (Cin, X[0], Y[0], S[0], C[1]);
Full_Adder stage1 (C[1], X[1], Y[1], S[1], C[2]);
Full_Adder stage2 (C[2], X[2], Y[2], S[2], C[3]);
Full_Adder stage3 (.Cout(Cout), .Cin(C[3]), .x(X[3]), .y(Y[3]), .S(S[3]));
endmodule
ASIC FPGA
How to go from Idea/Algorithm to the actual hardware
8. Course Description
Hardware Description Language (HDL) :Verilog
Professional Verilog Coding for Synthesis
Verification Techniques
FPGA Architectures
Digital System Design with Xilinx FPGAs
ASIC Digital Design Flow (from Verilog to the actual Chip!)
Synthesis Algorithms
Power Dissipation
Power Grid and Clock Design
Fixed-point Simulation Methodology
Detailed Design Optimization Workshop with ISE (for the fist time!)
9. Course Description:
1. HDL Coding
RTL Coding
Simulation
Pass?
Test Bench
Specifications
Synthesis
Standard
Cells
Timing
Constraints
Pre-Layout
Timing
Alanysis
Pass?
APR
Back
Annotation
Post-Layout
Timing
Alanysis
Pass?
Logic
verification
Tapeout
Yes
NO
Yes
NO
Yes
NO
2. Simulation 3. Synthesis 4. Placement & routing 5. Timing Analysis & Verification
Front-End Back-End
In this course we learn all the above steps in detail for
ASIC Platform
FPGA Platform
10. Course Description:
Hardware Description Language
Verilog Fundamentals
Language Fundamentals
Modeling Combinational/Sequential Logic Circuits
Modeling Finite State Machines
Verilog for Verification
Verification/Simulation techniques with test‐benches
Verilog for synthesis
Verilog Styles for Synthesis
Architectural techniques for high‐speed designs
o Parallel proc., pipelining, retiming, …
Implementations of common operations
o Complex multiplication, division, complex norm, CORDIC
Fundamentals of fixed‐point realization
11. Course Description:
PLDs & FPGA Architectures
FPGA Technologies
SPLDs (PAL and PLA architectures)
Commercial CPLD Architectures
SRAM/LUT Based FPGAs
Anti‐fuse/MUX Based FPGAs
Flash Based FPGAs
FPGA Architectures
Heterogeneous/Homogeneous FPGAs
Fine‐grained, coarse‐grained and platform FPGAs
FPGA Elements & Design Trade‐offs
Logic Cells Common Architectures
Programmable Routing Channels Design
I/O & Pad architectures
Commercial FPGAs
Altera (FLEX 10K, Stratix III) , Xilinx (XC4000, Virtex II,4,5), Actel (Act3, Axcelerator)
12. Course Description:
Advanced Digital System Design with Xilinx FPGAs
Design Creation
Synthesize
Simulation
Constraints Entry
Implementation
Implementation Results Analysis – Timing Analysis
Implementation Results Analysis – Power Analysis
Implementation Results Improvement
Device Configuration and Programming
Design Debugging
13. Course Description:
Core Generator
CORE Generator Tool
Intellectual Property (IP) Cores
CORE Generator Tool files
Design Flows
Defining Memory Contents for RAM and ROM
Defining Coefficient Values in a COE File
14. Course Description:
ASIC Design Flow:
HDL Coding & Verification
Synthesis & Timing Optimization
Complete Synopsys Design Complier Design Flow
Physical Design
Cadence First Encounter
Floorplan (Initial floorplan and power planning)
Placement (Full‐scale floorplan and clock tree insertion)
Routing (power routing & Nanoroute)
Timing Closure (Analysis & Optimization of setup and hold time violations)
Fill (Filler Cells, Metal Fill, and Verify Geometry)
16. Course Description:
Power Dissipation
Power Dissipation concept
Dynamic Power
Static Power
Challenges
17. Course Description:
Power Grid and Clock Design
Power Distribution Design
Introduction
IR Drop
Ldi/dt Drop
Decoupling Capacitances
Clock Considerations
PLL/DLL Architecture
18. Course Description:
Prerequisites:
Only Digital Logic!
All the skills you need will be taught in the course
Softwares you will learn:
Altera Quartus
Xilinx ISE
Mentor Graphics Modelsim
TCL Scripting
Synopsys Design Compiler
Cadence SOC Encounter
19. Course Description:
Implementation Platform:
Altera DE2 Board
Atlys Xilinx Board
You will do several practical assignments including Verilog Coding,
FPGA implementation and testing based on the DE2 and Atlys Boards
20. Course Outline : References
HDL:
Thomas & Moorby, The Verilog Hardware Description Language, 3rd ed, Kluwer Academic.
Introduction to Logic Synthesis using Verilog HDL, Robert Reese, Mitchell Thornton, 2006.
Advanced FPGA Design, Architecture, Implementation, and Optimization, Steve Kilts, 2007.
IC Design Flow:
Course Lecture notes, 2014
Digital IC Design Flow, provided by the instructor, 2014
21. Course Outline
20
• Course Outline
• Introduction to ASIC/FPGA IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
22. Integrated Circuit (IC) History
Discrete Circuits
Limited applications
Power hungry
Large area
Moderate speed
Integrated Circuits
Many applications
Low power
Small area
High speed
23. Integrated Circuits (IC) History
A picture of the filed patent
1940 1945 1947 1951 1955 1957 1958 1959 1961 1962 1968 1970 1971
Ohl built the PN Junction: 1940
Shockley Lab was established: 1945
Brattain and Bardeen invented the first transistor (US Patent 2524035): 1947
24. Integrated Circuits (IC) History
A picture of the filed patent
1940 1945 1947 1951 1955 1957 1958 1959 1961 1962 1968 1970 1971
1951: Shockley invented the first junction transistor for mass production
(US Patent
2623105)
25. IC History
Number of Transistors doubled every 18 months!
(Moore’s Law)
Scaling still continues…
1,000,000
100,000
10,000
1,000
10
100
8086
i386
80286
i486
Pentium® Pro
Pentium®
K 1 Billion Transistors
1
1975 1980 1985 1990 1995 2000 2005 2010
Source: Intel
Projected
Pentium®III
Pentium® II
1971 ……………………………………………………………………………………… 2010
26. IC History
1971 ………………………………………………..……………………… 2015
Amazingly visionary – million transistors/chip barrier was
crossed in the 1980’s.
2300 transistors, 1 MHz clock (Intel 4004) - 1971
16 Million transistors (Ultra Sparc III)
42 Million, 2 GHz clock (Intel P4) - 2001
140 Million transistor (HP PA-8500)
Integration Levels
SSI:
MSI:
LSI:
VLSI:
10 gates
1000 gates
10,000 gates
> 10k gates
27. IC History
Early Designs Advanced Designs
(1971)
1000 Transistors (1 MHz)
Process: 10um
Fully Handcrafted
Manual Layout
Individually Optimized
(2017)
Intel Corei7 -7700K(~ 4.2 GHz)
Process: 14nm
Fully Automated
Automated Layout
Hierarchical Design
Digital Very Large Scale Integration (VLSI) (Not Analog!)
30. Why Scaling?
Technology shrinks by ~0.7 per generation
With every generation can integrate 2x more functions on a chip; chip cost
does not increase significantly
Cost of a function decreases by 2x
But …
How to design chips with more and more functions?
Design engineering population does not double every two years…
Hence, a need for more efficient design methods
Exploit different levels of abstraction
31. IC Manufacturing Process
Silicon Wafer
Unpackaged Die
Patterned Silicon
Wafer
Silicon Cylinder
Packaged Die Final Test
Circuit Core
33. Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
37
34. Digital vs. Analog Design : Analog Circuits
Transmitter:
Receiver:
Modulator
Power
Amplifier
Voice
Analog/RF
High-frequency
carrier
Low-Noise
Amplifier
Down
Converter
Demodulator
Audio
Amplifier
Analog/RF
35. Digital vs. Analog Design : Analog-Digital Circuit
ADC
Voice
Compression
Coding
Interleaving
Pulse
shaping
Modulator
Power
Amplifier
Voice
Digital (Baseband) Analog/RF Front-end
Low-Noise
Amplifier
Down
Converter
ADC Demodulator Equalizer
De-interleaving
Decoding
Voice
Decompression
DAC
Audio
Amplifier
Digital (Baseband)
Transmitter:
Receiver: This Course
36. Digital vs. Analog Design
Digital Design Advantages:
More noise reliability
Allows signal decoding and amplification
Allows coding to achieve higher performance
Allows encryption for higher security
Provides a perfect vehicle for digital signal processing
Allows modular chip design
Enjoys the benefit of advanced sophisticated CAD tools
Can be verified on programmable devices before tape-out
Provides a platform to merge multiple networks such as
telephone, terrestrial TV and computer networks.
38. Digital System Design Steps
Specific application (e.g., Digital Image Processor)
As opposed to a general microprocessor
Design requirements
Images to be processed per second
Required processing
Interfacing
Dimension, power, price,…
General design and simulation
RTL level design to verify and simulate the design
Higher levels: Few complicated blocks
Lower levels: Many simple blocks
Toavoid any problem in lower levels, many simulations
in higher levels
RTL
39. Design Flow
Idea
Architecture Design
Circuit & Layout Design
Block
diagram
Layout
IC Fabrication
Wafer
(hundreds of dies)
Sawing & Packaging
Final chips
Testing
Bad chips Good chips
customers
40. Digital Systems Components
Printed Circuit Board (PCB)
Embedded Software
Microprocessor (general Purpose)
Microcontroller
Digital Signal Processor (DSP)
Programmable Logic Devices
Simple Programmable Logic Device (SPLD)
Complex Programmable Logic Device (CPLD)
Field Programmable Gate Arrays (FPGAs)
Application Specific Integrated Circuits (ASICs)
41. Digital Systems Components
DSPs
Easy to program (usually standard C)
Very efficient for complex sequential math-intensive tasks
Fixed datapath-width. Ex: 24-bit adder, is not efficient for 5-bit addition
Limited resources
42. Digital Systems Components
Microprocessors/Microcontrollers
Lessens the risk of system development by reducing design complexity
Fixed hardware so more effort on developing a good code
Fixed HW not suitable for high level of parallelism/computations
Many sequential nature
One order of magnitude less performance than to-date FPGA/ASICs
43. Digital Systems Implementation Platforms
PLDs
PLA PAL
CPLD FPGA
SPLD Semi-Custom Full-Custom
Digital IC
ASIC
Standard cell Gate Array
This course
44. Technology Timeline
The white portions of the timeline bars indicate that although early incarnations of these technologies
may have been available, they weren’t enthusiastically received by the engineers working in the
trenches during this period. For example, although Xilinx introduced the world’s first FPGA as early as
1984, design engineers didn’t really start using it until the early 1990s.
45. Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
49
46. FPGA vs. ASIC
Field Programmable Gate Array (FPGA) Advantages:
Fast programming and testing time by the end user (instant turn-around)
Excellent for prototyping
Easy to migrate from prototype to the final design
Can be re-used for other designs
lower start-up costs
Cheaper (in small volumes)
Re-programmable
Lower financial risk
Ease of design changes/modifications
Cheaper design tools
47. FPGA vs. ASIC
FPGA Drawbacks:
Slower than ASIC (2-3 times slower)
Power hungry (up to 10 times more dynamic power)
Use more transistors per logic function
More area (20 to 35 times more area than a standard cell ASIC)
48. FPGA vs. ASIC
Application Specific Integrated Circuit (ASIC) Advantages:
Faster
Lower power
Cheaper (if manufactured in large volumes)
Use less transistors per logic function
ASIC Drawbacks:
Implements a particular design (not programmable)
Takes several months to fabricate (long turn-around)
More expensive design tools
Very expensive engineering/mask cost for the first successful design
49. ASIC Mask Generation Cost
The ASIC is accompanied by increasing nonrecurrent engineering (NRE) costs which meant
that there was an increased emphasis on “right first time” design.
These NRE costs is largely due to the cost of generating masks as it is becoming more
expensive to generate the masks for finer geometries needed by shrinking silicon
technology dimensions.
50. Implementation Approaches (ASIC vs. FPGA)
ASIC
Application Specific
Integrated Circuit
FPGA
Field Programmable
Gate Array
Expensive & time consuming
fabrication in semiconductor
foundry
Designed all the way from
behavioral description to
physical layout
Bought off the shelf & reconfigured
by the end designers
No physical layout design
Design ends with a bitstream
used to configure a device
51. Implementation Approaches (ASIC vs. FPGA)
Re-configurability
ASICs FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes
53. Course Outline
57
• Course Outline
• Introduction to ASIC/FPGA IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
54. 57
Design Abstraction Levels
n+
n+
S
G
+
DEVICE
D
CIRCUIT
GATE
MODULE
SYSTEM
Divide-and-Conquer
Design modules once
Instantiate them
thereafter
Standard Cells
Already laid out
Avoid re-design
Same as programming
Designer cares about module’s:
Functionality
Delay characteristics
Area
NOT:
How the module was
designed
Detailed solid-state behavior
This Course VLSI Course
56. Single Die
Wafer
Device Metrics
Performance Metrics of a Digital Chip:
Cost
NRE (fixed) costs - design effort
RE (variable) costs - cost of parts, assembly, test
Speed
Delay (ns) → Operating Frequency (MHz)
Power Dissipation
Energy to Perform a Function
Energy per bit (nJ/b)
Reliability
Noise immunity
Noise margin
Scalability
Larger Designs
Time-to-Market
Diameter: 10-30 cm
Thickness: 1 mm
57. Single Die
Wafer
Device Metrics
Performance Metrics of a Digital Chip:
Cost
NRE (fixed) costs - design effort
RE (variable) costs - cost of parts, assembly, test
Speed
Delay (ns) → Operating Frequency (MHz)
Power Dissipation
Energy to Perform a Function
Energy per bit (nJ/b)
Reliability
Noise immunity
Noise margin
Scalability
Larger Designs
Time-to-Market
58. Cost of Integrated Circuits
NRE (non-recurring engineering) costs
Fixed cost to produce the design
• Design effort
• Design verification effort
• Mask generation
Influenced by the design complexity and designer productivity
More pronounced for small volume products
RE (Recurring costs) – proportional to the product volume (i.e., Variable)
Silicon processing
• also proportional to chip area
Assembly (packaging)
Test
fixed cost
Cost per IC = variable cost per IC + -----------------
volume
59. Recurring Costs
cost of die + cost of die test + cost of packaging
variable cost = ----------------------------------------------------------------
final test yield
cost of wafer
cost of die = -----------------------------------
dies per wafer × die yield
× (wafer diameter/2)2 × wafer diameter
---------------------------
Dies per wafer = ----------------------------------
die area 2 × die area
die yield = (1 + (defects per unit area × die area)/)-
α depends on the complexity of the
manufacturing process (roughly
proportional to the number of masks)
60. Yield Example
Example
Wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
= 3 (measure of manufacturing process complexity)
252 dies/wafer (remember, wafers round & dies square)
Die yield of 16%
252 x 16% = only 40 dies/wafer die yield !
Die cost is a strong function of the die area
Proportional to the third or fourth power of the die area
Cost of die = f(die area)4
61. Examples of Cost Metrics (1994)
65
Chip Metal
layers
Line
width
Wafer
cost
Defects
/cm2
Area
(mm2)
Dies
/wafer
Yield Die
cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486DX2 3 0.80 $1200 1.0 81 181 54% $12
PowerPC 601 4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super SPARC 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417
62. Single Die
Wafer
Device Metrics
Performance Metrics of a Digital Chip:
Cost
NRE (fixed) costs - design effort
RE (variable) costs - cost of parts, assembly, test
Speed
Delay (ns) → Operating Frequency (MHz)
Power Dissipation
Energy to Perform a Function
Energy per bit (nJ/b)
Reliability
Noise immunity
Noise margin
Scalability
Larger Designs
Time-to-Market
63. Performance
Frequency of operation: 1/T
Dependent on the propagation delay of signal through the logic
Time to get the data out/in of the registers
Clock uncertainty
tp is a typical measure (not an accurate one)
the delay experienced by a signal when passing through a gate
50% transition points of the input and output waveforms
• Two types LH and HL
• Good for comparison
Rise time/fall time affects delay
10% - 90% definitions
65. Single Die
Wafer
Device Metrics
Performance Metrics of a Digital Chip:
Cost
NRE (fixed) costs - design effort
RE (variable) costs - cost of parts, assembly, test
Speed
Delay (ns) → Operating Frequency (MHz)
Power Dissipation
Energy to Perform a Function
Energy per bit (nJ/b)
Reliability
Noise immunity
Noise margin
Scalability
Larger Designs
Time-to-Market
66. Power Consumption
Peak transient power
Power line sizing, decoupling, etc.
Average power
Battery current delivery, cooling system
Static power vs. Dynamic power
Static current no computation, etc
Dynamic current Switching on/off the gates
The higher the number of switching events, the higher the dynamic power consumption
Dynamic Energy Amount of energy that is needed to be spent to do a job
Time is no matter
Ppeak = ipeakVsupply =max[p(t)]
67. Power and Energy Dissipation
Propagation delay and the power consumption of a gate are related
Propagation delay is (mostly) determined by the speed at which a
given amount of energy can be stored on the gate capacitors
the faster the energy transfer (higher power dissipation) the faster the gate
For a given technology and gate topology, the product of the power
consumption and the propagation delay is a constant
Power-delay product (PDP) – energy consumed by the gate per switching event
An ideal gate is the one that is fast and consumes little energy, so the
ultimate quality metric is
Energy-delay product (EDP) = power-delay
68. Single Die
Wafer
Device Metrics
Performance Metrics of a Digital Chip:
Cost
NRE (fixed) costs - design effort
RE (variable) costs - cost of parts, assembly, test
Speed
Delay (ns) → Operating Frequency (MHz)
Power Dissipation
Energy to Perform a Function
Energy per bit (nJ/b)
Reliability
Noise immunity
Noise margin
Scalability
Larger Designs
Time-to-Market
69. Reliability: Noise in Digital Integrated Circuits
Noise : unwanted variations of voltages and currents at the logic nodes
VDD
v(t)
i(t)
from two wires placed side by side
Capacitive coupling
Voltage change on one wire can
influence signal on the neighboring wire
Cross talk
Inductive coupling
Current change on one wire can
influence signal on the neighboring wire
from noise on the power and ground supply rails
May influence signal levels in the gate
70. Noise Margins
Region
"1"
"0"
Gate Output Gate Input
VOH
VIL
VOL
VIH
Undefined
Noise Margin High
Noise Margin Low
NMH = VOH -VIH
NML = VIL -VOL
Noise margin represents the levels of noise that can be sustained
when gates are cascaded
Gnd Gnd
For robust circuits, want the “0” and “1” intervals to be as large as possible
VDD VDD
71. Noise Immunity
Noise margin expresses the ability of a circuit to overpower a noise source
Noise sources: supply noise, cross talk, interference, offset
Absolute noise margin values are deceptive
Floating node is more easily disturbed than a node driven by a low
impedance (in terms of voltage)
Noise immunity expresses the ability of the system to process and transmit
information correctly in the presence of noise (noise rejection)
For good noise immunity, the signal swing (i.e., the difference between VOH
and VOL) and the noise margin have to be large enough to overpower the
impact of fixed sources of noise
72. Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
78
73. MOS Device Theory
Bipolar Junction Transistor (BJT)
Small current in Base drives a larger current b/w Emitter & Collector.
Quiescent power dissipation due to the Base current
High power dissipation limits the number of transistors on a single chip
Not suitable for Very Large Scale Integration (VLSI)
Metal Oxide Semiconductor Field Effect Transistors (MOSFET)
Come with almost zero control current (Gate voltage controls the drain current)
Higher integration
Much lower power consumption than BJT
Come in two flavors : n-MOS (n-type dopants), p-MOS (p-type dopants)
Complementary Metal Oxide Semiconductor (CMOS)
Utilizing both n-MOS and p-MOS transistors
Mostly
Analog
Mostly
Digital
74. MOS Device Theory
Transistors are built on a silicon substrate
Silicon is a Group IV material → covalent bonds with 4 adjacent atoms
Silicon is a poor conductor → can be raised by adding dopants
Si Si Si
Si Si Si
Si
Si Si
Si
Si
Si
Si
Si
Si Si
Si
Si- Si
As+
+
B -
Si
Si Si
Si Si Si
Group V dopants
Five valence electrons
Extra electron free to move
Negative carrier
Example:
Arsenic, Phosphorus
Group III dopants
3 valence electrons
Missing electron(hole) free to move
Positive carrier
Example:
Boron
n-type p-type
75. MOS Device Theory
Four terminals:
1. Gate
2. Source
3. Drain
4. Body
Consists of :
Gate (Metal (old), Polysilicon (now))
Insulating layer (SiO2 (oxide- glass))
Source (n+ in nMOS, p+ in pMOS)
Drain (n+ in nMOS, p+ in pMOS)
Body (conductor)
n+: Heavily doped n-type
P+: Heavily doped p-type
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
Body
G
D S
B
nMOS
76. nMOS Transistors
n+
p
Gate
Source Drain
bulk Si
n+
Body
OFF
Gate–oxide–body stack looks like a capacitor
Body is commonly tied to ground (0 V)
Gate at low voltage:
Body is at low voltage
Source-body diode is OFF
Drain-body diode is OFF
No current flows
Transistor is OFF
77. nMOS Transistors
n+
p
Gate Drain
bulk Si
n+
Body Source
ON
Gate at high voltage:
Positive charge on gate
Negative charge attracted to body
Inverts a channel under gate to n-type
Current flow in this channel b/w source and drain when drain voltage is nonzero
Transistor is ON
78. pMOS Transistors
Similar to nMOS with reversed doping and voltages
Body is commonly tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
p+
p
Gate Drain
bulk Si
p+
Body Source
Polysilicon
SiO 2
G
D S
B
pMOS
79. MOS Transistors
L is the channel length
L : Process parameter, technology
Smaller L → Faster transistors → higher speed circuits
Typical process values: 0.35μm, 0.18μm, 0.13μm, 90nm, 60nm, …
VDD decreases by technology
1.5 V for 0.18 μm
1.2 V for 0.13 μm
Lower VDD saves power consumption
GND = 0 V
80. CMOS
Silicon wafer is the base material
Diameter: 10-30 cm
Thickness: 1 mm
CMOS : both nMOS and pMOS transistors fabricated on a single wafer
Wells : special regions to separate bulks of nMOS and pMOS
n+
p substrate
p+
n well
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
81. CMOS
Substrate must be tied to GND and n-well to VDD
Poor connection of metal to lightly-doped semiconductor (Shottky Diode)
Use heavily doped well and substrate contacts
n+
p substrate
p+
n well
GND VDD
n+
p+
substrate tap well tap
n+ p+
A
GND VDD
Top View
Cross Section along DashedLine
82. Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
“Feature size”
Lmin= distance between source and drain (channel)
(minimum width of Polysilicon)
Feature size improves 30% every 3 years or so
Can integrate 2× more functions per chip → 2× less cost per function
Normalize for feature size when describing design rules ( Lmin / 2 )
E.g., = 90nm in 0.18 μm process
n+
n+
p-type body
W
L
tox
SiO2 gateoxide
polysilicon
gate
Feature Size
83. Layout Layers
Each layout consists of various levels described by different colors.
P substrate
wafer
n well
TopView
Cross Section View
84. Design Rules
Circuit engineer designs a circuit
Process engineer fabricates the design
DRC : constraints on patterns in terms of minimum width and separation
DRC: guarantees that the circuit to be manufacturable
Deign Rule Check (DRC)
is the interface between them
85. Digital VLSI Layout
Designed and laid-out standard cells
They are placed & abutted in a chip
Metal 2
Via 12
Metal 1
Several metal layers used for routing
86. Digital VLSI Layout
Standard cells are automatically placed and routed using different metal
layers through the corresponding CAD tools
87. Chip Floorplan
Start with the pin count (# of I/O and VDD, VSS pads)
Pads are already designed (provided in the design kit)
I/O Pads
I/O Pads
I/O
Pads
I/O
Pads
Corner
Pads
Corner
Pads
Corner
Pads
Corner
Pads
Core
Design
VDD Core
VSS Core
89. Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
Integrated Circuits (IC) History
Digital Design vs. Analog Design
ASIC vs. FPGA
Design Abstraction and Metrics
CMOS as the building block of Digital ASICs
Layout
Packaging
97
90. Packaging
Package:
Die interface to outside world
Removes heat from chip
Mechanical support
Protects die against humidity
× Introduces delay/parasitics to the chip
Advanced Package Requirements:
Electrical: Low Parasitics
Mechanical: Reliable and Robust
Thermal: Efficient Heat Removal
Economical: Cheap
91. Package/Socket to Board Interconnection
Through-Hole Mounting
Mechanically reliable
× Low package density
× Limits routing on the board
Dualin-Line (DIP) (up to 64 pins)
PGA (up to 400 pins)
Surface Mount
More wiring space
Higher package density
Chips at both sides of the board
× Weak chip-board connection
× Non-accessible pins for testing
92. Package/Socket to Board Interconnection
Solder bumps are used to connect both the die to the
package substrate and the package to the board
For very large pin-counts, even surface-mount packaging is not enough!
Ball Grid Array (BGA)