1. Jaydip Bharatkumar Patel__ _____________________________________________________
1255 University Avenue, #221, Sacramento, CA -95825 (312)-608-8200 jaydip.patel@gmail.com
OBJECTIVE: Seeking a full-time internship or entry-level position in the field of VLSI design & validation.
EDUCATION:
M.S (Electrical & Electronics Engineering) California State University, Sacramento GPA 3.9/4.0 May 2009
B.S (Electronics & Communication Engineering) Gujarat University, India GPA 4.0/4.0 June 2007
RELATED COURSE WORK:
CMOS & VLSI Analog & mixed signal IC design Advanced analog and mixed signal IC design
Digital IC design Mixed Signal IC methodology lab. Key mixed signal building blocks IC design
Advanced Logic Design Advanced Timing Analysis Computer Architecture and Organization
VLSI Design for test I VLSI Design for test II Microcomputer system Architecture
PROFESSIONAL EXPERIENCE:
Teaching Assistant, Analog & Mixed Signal IC design – EEE department, CSUS, Sacramento Sept 2008- present
• Assist Prof. Perry Heedley to maintain student records, provide Pspice help sessions, grade exams and home-work
Pad Design Summer Intern, Analog I/O IP Team – Freescale Semiconductor, Austin TX June 2008-August 2008
• Performed latch-up functional simulation on various pads (using Cadence & MICA in Linux environment) and
tested the results with practical latch up stress on silicon parts. (Silicon debugging).
• Wafer level micro-probing for I/O pad circuits for latch-up characterization ( Silicon testing)
• Designed latch up test structures for analog I/O pads for 90nm process and documented validation methods.
• Debugged layouts for latch up tolerance and improved floor planning to improve latch up tolerance.
• Simulations, layout analysis and design work was accomplished using Cadence Virtuoso, Calibre & MICA tools
in a Linux Environment.
Design Engineer Student Intern, ASIC/FPGA Team - System Level Solutions (I) Pvt. Ltd. July 2006-June 2007
• Designed SoC using Altera’s FPGA kit along with software tools (Quartus II, SOPC builder, Nios II IDE).
• Implemented custom instructions for the Nios II embedded processor using Altera’s Cyclone FPGA kit.
TOOLS & SOFTWARE:
Software Tools: Xilinx ISE ∙ Modelsim ∙ Synopsis VCS ∙ Matlab 6.0 ∙ NIOS IDE ∙ Quartus II ∙ SOPC builder
IC design tools: Cadence (Virtuoso, Allegro, OrCad) ∙ Mentor Graphics* (Design architect IC, Eldo, Calibre) ∙ MICA
Languages: Verilog HDL ∙ VHDL∙ Perl ∙ TCL ∙ C ∙ C++ ∙ 8086 ∙ Nios II
Operating System: UNIX (Working knowledge) ∙ Linux ∙ Windows 95/98/ME/NT/2000/XP/Vista
Equipment: Logic Analyzer ∙ Digital Oscilloscope ∙ Flash Programmer ∙ Parametric Analyzer
PROJECTS:
ANALOG & MIXED SIGNAL DESIGN:
• CMOS PLL Design*: Design a CMOS PLL which works as a FM frequency synthesizer to generate 2
frequencies – 97.5MHz and 103.1MHz. This frequency will act as a carrier wave for FM modulation for FM
transmitter and receiver set. (using Mentor Graphics IC EDA tools and manufactured by MOSIS)
• CMOS Comparator Design: Comparison time < 1 ns, accuracy = 10mV, Von min = 200mV, Overhead recovery
test for differential inputs up to + 500mV, Vdd = 5.0 V, Process technology = 0.5um. (Cadence Schematic)
• Behavioral Model Design of Flash ADC: 6-bit interpolating flash ADC using 3 stages of preamplifiers with
resistive interpolation of 2 at the output of each preamplifier for a total interpolation of 8. (Matlab 8.0)
• CMOS 2 Stage Opamp Design: Unity gain bandwidth > 350 Mhz, DC open loop gain > 50 dB, Phase Margin >
65 degrees C, Vout swing > 2.0 V(p-p), Minimum Von for all 150 mV, Minimum Load capacitance = 2pF, Vdd =
3.0 V, Process technology = 0.35um. (Cadence Schematic)
• Device Matching of Differential Amplifier: Study the mismatch of transistors in a differential amplifier with
active load, analyze the characteristics of offsets in this amplifier, Process Technology = 0.18um.(Pspice)
• Design/Layout of 3-bit register: Design a memory with 3 registers of 2 bits each and design its layout.(Pspice,
LEDIT layout tool)
2. LOGIC DESIGN:
• ALU & FIFO DESIGN*: Design ALU & FIFO Verilog design and perform test bench verification. Also, use
Perl scripting tool to read /write user data into the test bench. (Synopsys VCS )
• ADC-SRAM Interface Design: Designed an interface to write and read the data from the ADC output to the
SRAM using Verilog HDL and Xilinx board and display the current data on the LCD display.(Xilinx ISE)
• Flash-SRAM Interface Design: Designed an interface to read the data from Flash and to write the same data at
the specified addresses in the SRAM using Verilog HDL and Xilinx FPGA board.(Xilinx ISE)
• Verilog / VHDL logic design hardware projects: ALU RTL design, sequence detector design, keypad design,
calculator design, scrolling LCD display, traffic signal controller design, counter design, Real time clock design,
and Moore/Mealy FSM design. (Xilinx ISE, Modelsim)
COMPUTER ARCHITECTURE:
• PCI design/ interface: Designed a 32 bit PCI card to perform PCI read and writes including bus arbitration logic
between 2 PCI devices. Wrote a test bench according to the arbitration required (Verilog HDL, Modelsim)
• Cache Memory design: Designed a Cache Memory system to perform memory reads/ writes from/to the
processor to the main memory. (2-way set cache size = 8kb, page size = 4kb with snooping capability which
observes reads/ writes on the system memory and any miss is acknowledged by virtual memory associative)
(Verilog HDL, Modelsim)
VLSI VALIDATION & TESTING
• Fault Models & ATPG in VLSI circuits
Abstract: This paper focuses on various faults models and ATGs in analog and mixed integrated circuits,
memory integrated circuits and digital integrated circuits.
• Memory ATE architecture and features*
Abstract: This paper focuses on various memory ATE architectures and features for DRAM, SRAM and flash
technology. * Fall08
COURSE DESCRIPTION:
Analog & Mixed circuit design: Theory of MOSFETs, CMOS logic design, CMOS physical design, CMOS models,
electrical analysis of CMOS gates, High-speed CMOS design, MOS & BJT device structures, single-stage amplifiers,
multi-stage amplifiers, cascoded amplifiers, differential amplifiers, current mirrors, operational amplifiers, common
mode feedback, switched capacitor circuits, analog design methodology, device mismatching, analog layout techniques,
PVT independent bias circuits, bandgap reference circuits, CML circuits, noise in IC design, CMOS comparator design,
CMOS ADC design, CMOS DAC design, CMOS PLL design (VCO, PFD, charge pump).
Logic Design: Design of combinational circuits, FSMs & sequential circuits, VHDL / Verilog HDL programming,
Hardware based projects (FPGA, CPLD, SRAM, and ADC) which include digital simulation, synthesis and emulation on
hardware boards, RTL design, synthesis, place and route, test bench design, Perl / Tcl scripting, ASIC design flow, ASIC
design methodology, static timing analysis, timing design constraints, design reports, clock timing issues, timing
exceptions, operating conditions, hierarchical analysis, analyzing designs with asynchronous logic, performance
measurement and power issues.
Computer Architecture: Design of processor based computer system(core, MCH, ICH, bus architecture & interfaces),
Cache memory (Architecture, organization, size), 8086 architecture, x86 programming model, Virtual Memory, Paging,
Segmentation, Study of PCI bus structures, introduction to computer buses (PCI e, hyperTransport, SATA, USB, I2C) ,
MESI protocol, pipelining, Branch prediction, Register renaming, Out-of-Order Execution, CPU power management (P-
states, C-states, G-states), ACPI, Superscalar Architecture, Cache memory (associative, size etc.).
VLSI Validation and testing: Integrated circuit design-for-test-techniques (DFT), IC manufacturing flow (e-test, wafer
sort, class test, packaging, marking, inspecting),economics of manufacturing (yield analysis, failure analysis, cost/quality)
silicon processing, CMOS parametrics, ATE architecture and features, IC testing (optimization of test flow, test program
development), high-accuracy parametric test methods, memory-specific test methodology and special features of memory
designs employed in high volume manufacturing for improved testability, yield and reliability, VLSI failure modes, their
detection and prevention, application of trim, redundancy, wear-leveling, and error correction.
